JP5809877B2 - Manufacturing method of trench gate type power semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a trench gate type power semiconductor equipment.

  Conventionally, trench gate type power MOSFETs have been widely used in various power supply devices such as DC-DC converters (see, for example, Patent Document 1). FIG. 14 is a cross-sectional view of a conventional trench gate type power MOSFET 900.

Conventional trench gate type power MOSFET900, as shown in FIG. 14, the ^{n +} -type drain layer 912, n located on ^{n +} -type drain layer 912 ^- -type drift layer 914, n ^- on the type drift layer 914 P-type body layer 920 positioned, groove 930 formed by opening p-type body layer 920 and reaching n ⁻ -type drift layer 914, disposed in p-type body layer 920, and at least partially Are formed on the inner peripheral surface of the trench 930, an n ⁺ -type source region 940 formed on the inner peripheral surface of the trench 930, a gate insulating film 932 formed on the inner peripheral surface of the trench 930, and an inner peripheral surface of the gate insulating film 932. And a source electrode layer 950 that is insulated from the gate electrode layer 934 and formed in contact with the n ⁺ -type source region 940. In FIG. 14, reference numeral 910 indicates a semiconductor substrate, reference numeral 936 indicates a protective insulating film, reference numeral 942 indicates a p ⁺ -type contact region, and reference numeral 960 indicates a drain electrode layer.

  According to the conventional trench gate type power MOSFET 900, since the unit cell area can be reduced as compared with the case of the normal planar gate type power MOSFET, the on-resistance is reduced as compared with the case of the normal planar gate type power MOSFET. It becomes possible to do.

JP 2002-299619 A

However, the conventional trench gate type power MOSFET 900 has the following problems. FIG. 15 is a diagram showing an impurity concentration profile in the p-type body layer 920. That is, in the conventional trench gate type power MOSFET 900, as shown in FIG. 15, the diffusion depth of the n-type impurity varies when the n ⁺ -type source region is formed. The depth position where the concentration of the p-type impurity shows the maximum value varies. As a result, there is a problem that the maximum concentration of the p-type impurity in the p-type body layer 920 varies, and the threshold value of the trench gate type power MOSFET varies. Such a problem is also seen in the case of a trench gate type power MOSFET in which the p-type and the n-type are reversed. Further, such a problem is not a problem that exists only in the case of a trench gate type power MOSFET, but is also a problem that is found in trench gate type power semiconductor devices in general.

  Accordingly, the present invention has been made to solve the above-described problem, and even if the diffusion depth of the first conductivity type impurity varies when forming the source region of the first conductivity type, the trench gate type power semiconductor. An object of the present invention is to provide a trench gate type power semiconductor device capable of suppressing the problem that the threshold value of the device varies.

[1] A trench gate type power semiconductor device of the present invention includes a first conductivity type drift layer, a second conductivity type body layer disposed on the drift layer and opposite to the first conductivity type, A groove formed by opening the body layer and reaching the drift layer; and a first groove formed in the body layer and exposed at least partially on the inner peripheral surface of the groove. Insulated from the conductive type source region, a gate insulating film formed on the inner peripheral surface of the groove, a gate electrode layer formed on the inner peripheral surface of the gate insulating film, and the gate electrode layer And a source electrode layer formed in contact with the source region, wherein a depth position where the concentration of the second conductivity type impurity in the body layer shows a maximum value is deeper than a lowermost surface of the source region. It is characterized by being.

  According to the trench gate type power semiconductor device of the present invention, as shown in FIG. 2 described later, the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value is deeper than the lowermost surface of the source region. Therefore, even if the diffusion depth of the n-type impurity varies when the source region is formed, the variation in the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value and this result Variation in the maximum concentration of the second conductivity type impurity in the body layer is suppressed. As a result, it is possible to suppress the problem that the threshold value of the trench gate type power semiconductor device varies.

  In addition, according to the trench gate type power semiconductor device of the present invention, since the depth of the body layer and the source region can be reduced, an effect that the input capacitance Ciss and the channel resistance can be reduced is also obtained.

  That is, according to the trench gate type power MOSFET of the present invention, as shown in FIG. 3 described later, the body layer and the source region can be shallowed without reducing the surface impurity concentration in the body layer. This is because the maximum concentration of the second conductivity type impurity in the body layer does not increase even when the body layer and the source region are shallow without reducing the surface impurity concentration in the body layer. This is because it is not necessary to reduce the surface impurity concentration in the body layer in order to suppress punch-through as in the case of the gate type power MOSFET 900. As a result, according to the trench gate type power semiconductor device of the present invention, since the body layer and the source region can be made shallower than in the case of the conventional trench gate type power MOSFET 900, the gate area is reduced and the input capacitance is reduced. Ciss can be reduced, and the channel length can be shortened to reduce the channel resistance.

[2] In the trench gate type power semiconductor device of the present invention, the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value is at a position deeper than 2 μm from the lowermost surface of the source region. Is preferred.

  By adopting such a configuration, the variation in the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value and the variation in the maximum concentration of the second conductivity type impurity in the body layer due to the variation are further increased. It will surely be suppressed. As a result, it is possible to reliably suppress the problem that the threshold value of the trench gate type power semiconductor device varies.

[3] In the trench gate type power semiconductor device of the present invention, the trench gate type power semiconductor device is a trench gate type power MOSFET, and the first conductivity type drift layer is formed on the drain layer of the first conductivity type. It is preferable to arrange | position.

  With such a configuration, the effects of the present invention can be obtained in a trench gate type power MOSFET.

[4] In the trench gate type power semiconductor device of the present invention, the trench gate type power semiconductor device is a trench gate type IGBT, and the first conductivity type drift layer is formed on a second conductivity type collector layer. It is preferable that they are arranged.

  By adopting such a configuration, the effect of the present invention can be obtained in the trench gate type IGBT.

[5] A method for manufacturing a trench gate type power semiconductor device according to the present invention is a method for manufacturing a trench gate type power semiconductor device for manufacturing the trench gate type power semiconductor device according to the present invention. A semiconductor comprising a first semiconductor layer of one conductivity type and a second semiconductor layer of a second conductivity type serving as the body layer, and preparing a semiconductor substrate having a structure in which the second semiconductor layer is stacked on the first semiconductor layer A base preparation step, a groove forming step of forming a groove so as to reach the first semiconductor layer from the surface of the second semiconductor layer, and a gate insulating film forming step of forming a gate insulating film on the inner peripheral surface of the groove; A gate electrode layer forming step of forming a gate electrode layer on the inner peripheral surface of the gate insulating film; and a first conductivity type so that at least a part of the second semiconductor layer is exposed on the inner peripheral surface of the groove. Source region Forming a source region, forming a protective insulating film so as to cover the gate electrode layer, and forming a source electrode so as to cover the second semiconductor layer and the protective insulating film Electrode formation step in this order, and in the semiconductor substrate preparation step, the depth position where the concentration of the second conductivity type impurity in the second semiconductor layer shows the maximum value is the surface of the second semiconductor layer and the A semiconductor substrate existing between the bottom surface of the second semiconductor layer is prepared.

  According to the method for manufacturing a trench gate type power semiconductor device of the present invention, the excellent trench gate type power semiconductor device of the present invention can be manufactured as described above.

[6] In the method of manufacturing a trench gate type power semiconductor device according to the present invention, the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value is a position deeper than the surface of the body layer by 4 μm or more. Preferably there is.

  By adopting such a method, it becomes possible to manufacture a trench gate type power semiconductor device that can more reliably suppress the problem that the threshold value of the element varies.

[7] In the method for manufacturing a trench gate type power semiconductor device according to the present invention, the trench gate type power semiconductor device is a trench gate type power MOSFET, and the drain layer is provided in the first step of preparing the semiconductor substrate. A semiconductor having a conductive third semiconductor layer, the first semiconductor layer, and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are stacked in this order on the third semiconductor layer. It is preferable to prepare a substrate.

  By setting it as such a method, the trench gate type power MOSFET which has the effect of this invention can be manufactured.

[8] In the method for manufacturing a trench gate type power semiconductor device according to the present invention, the trench gate type power semiconductor device is a trench gate type IGBT, and in the semiconductor substrate preparation step, the second conductive material serving as the collector layer. A semiconductor substrate having a structure in which a fourth semiconductor layer of a type, the first semiconductor layer, and the second semiconductor layer are provided, and the first semiconductor layer and the second semiconductor layer are stacked in this order on the fourth semiconductor layer It is preferable to prepare.

  By setting it as such a method, the trench gate type IGBT which has the effect of this invention can be manufactured.

1 is a cross-sectional view of a trench gate type power MOSFET 100 according to Embodiment 1. FIG. 6 is a diagram showing an impurity concentration profile in a p-type body layer 120. FIG. It is a figure shown in order to demonstrate the reason which can make the depth of a p-type body layer and a source region shallow. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. FIG. 5 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the first embodiment. It is a figure shown in order to explain the reason that it becomes possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies even if the diffusion depth of the p-type impurity varies. FIG. 10 is a view for explaining the method for manufacturing the trench gate type power MOSFET according to the second embodiment. It is a figure shown in order to demonstrate the manufacturing method of the trench gate type power MOSFET which concerns on Embodiment 3. FIG. 6 is a cross-sectional view of a trench gate type IGBT according to Embodiment 4. FIG. It is sectional drawing of the conventional trench gate type power MOSFET900. 6 is a diagram showing a concentration profile of impurities in a p-type body layer 920. FIG.

  Hereinafter, a trench gate type power semiconductor device and a manufacturing method thereof according to the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. The trench gate type power MOSFET 100 according to the first embodiment
FIG. 1 is a cross-sectional view of a trench gate type power MOSFET 100 according to the first embodiment. FIG. 2 is a diagram showing an impurity concentration profile in the p-type body layer 120.

As shown in FIG. 1, the trench gate type power MOSFET 100 according to the first embodiment includes an n ⁺ type drain layer 112 and an n ⁻ type drift layer (first conductivity type drift layer) located on the n ⁺ type drain layer 112. ) 114, p-type body layer (second conductivity type body layer) 120 located on n ⁻ -type drift layer 114, and p-type body layer 120 are opened to reach n ⁻ -type drift layer 114. And an n ⁺ -type source region (first conductivity type source region) formed in the p-type body layer 120 and having at least a portion exposed on the inner peripheral surface of the trench 130. 140, a gate insulating film 132 formed on the inner peripheral surface of the trench 130, a gate electrode layer 134 formed on the inner peripheral surface of the gate insulating film 132, and the gate electrode layer 134, and n ⁺ Type A source electrode layer 150 formed in contact with the source region 140 and a drain electrode layer 160 formed in contact with the n ⁺ -type drain layer 112 are provided. As shown in FIG. 2, the depth position at which the concentration of the p-type impurity in the p-type body 120 has the maximum value is deeper than the lowermost surface of the n ⁺ -type source region 140. In FIG. 1, reference numeral 110 denotes a semiconductor substrate, reference numeral 122 denotes a p ⁻ type semiconductor region located on the surface side of the p type body layer 120, and reference numeral 124 denotes a central portion of the p type body layer 120. Reference numeral 126 denotes a p-type semiconductor region, reference numeral 126 denotes a p ⁻ type semiconductor region located on the bottom surface side of the p type body layer 120, and reference numeral 142 denotes a p ⁺ type contact region.

The thickness of the n ⁺ type drain layer 112 is, for example, 300 μm, and the impurity concentration of the n ⁺ type drain layer 112 is, for example, 2 × 10 ¹⁹ cm ⁻³ . Further, the thickness of the n ⁻ type drift layer 114 is, for example, 50 μm, and the impurity concentration of the n ⁻ type drift layer 114 is, for example, 1 × 10 ¹⁴ cm ⁻³ . In addition, the thickness of the p-type body layer 120 is, for example, 10 μm, and the impurity concentration of the p-type body layer 120 is, for example, 1 × 10 ¹⁵ cm ⁻³ on the surface (part of the p ⁻ -type impurity region 122). For example, it is 1 × 10 ¹⁴ cm ⁻³ in the (p ⁻ type impurity region 126 portion), and is 1 × 10 ¹⁶ cm ⁻³ between the front surface and the bottom surface (portion of the p type impurity region 124).

The depth of the trench is, for example, 11 μm, the depth of the n ⁺ -type source region 140 is, for example, 2 μm, and the impurity concentration of the n ⁺ -type source region 140 is, for example, 2 × 10 ¹⁹ cm ⁻³ . The thickness of the gate insulating film 132 is, for example, 2 μm at the bottom surface portion of the groove 130, and is, for example, 0.1 μm at the side surface portion of the groove 130. The gate electrode layer 134 is made of, for example, polysilicon doped with phosphorus. The source electrode layer 150 is made of, for example, aluminum and has a thickness of, for example, 2 μm. The source electrode layer 150 is insulated from the gate electrode layer 134 by the protective insulating film 136. The drain electrode layer 160 is made of, for example, nickel and has a thickness of, for example, 2 μm.

The depth position at which the concentration of the p-type impurity in the p-type body layer 120 has the maximum value is at a position 3 μm deep from the bottom surface of the n ⁺ -type source region 140 as shown in FIG. Further, the depth is 5 μm from the surface of the p-type body layer 120.

2. Effect of trench gate type power MOSFET 100 according to the first embodiment According to the trench gate type power MOSFET 100 according to the first embodiment, as described above, the depth position where the concentration of the p type impurity in the p type body layer 120 shows the maximum value. but, n ⁺ because it is deeper than the lowermost surface of the source region 140, even as the diffusion depth of the n-type impurity varies in forming the n ⁺ -type source region 140, p in p-type body layer 120 Variation in the depth position where the concentration of the p-type impurity shows the maximum value and variation in the maximum concentration of the p-type impurity in the p-type body layer 120 due to this variation are suppressed. As a result, it is possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies.

In addition, according to the trench gate type power MOSFET 100 according to the first embodiment, since the depths of the p-type body layer 120 and the n ⁺ -type source region 140 can be reduced, the input capacitance Ciss and the channel resistance can be reduced. The effect is also obtained.

FIG. 3 is a diagram for explaining the reason why the depths of the p-type body layer 120 and the n ⁺ -type source region 140 can be reduced. FIG. 3A is a diagram showing that the problem is suppressed when the depths of the p-type body layer 120 and the n ⁺ -type source region 140 are reduced in the trench gate type power MOSFET 100 according to the first embodiment. FIG. 3B is a diagram showing a problem when the depths of the p-type body layer 920 and the n ⁺ -type source region 940 are reduced in the conventional trench gate type power MOSFET 900.

That is, according to the trench gate type power MOSFET 100 according to the first embodiment, as shown in FIG. 3A, the p-type body layer 120 and the n ⁺ -type are formed without reducing the surface impurity concentration in the p-type body layer 120. It is possible to make the source region 140 shallow. This is because the maximum concentration of p-type impurities in the p-type body region is low even when the p-type body layer 120 and the n ⁺ -type source region 140 are shallowed without reducing the surface impurity concentration in the p-type body layer 120. This is because it does not increase, so that it is not necessary to reduce the surface impurity concentration in the p-type body layer in order to suppress punch-through as in the case of the conventional trench gate type power MOSFET 900. As a result, according to the trench gate type power MOSFET 100 according to the first embodiment, the p type body layer and the n ⁺ type source region can be made shallower than in the case of the conventional trench gate type power MOSFET 900. Can be reduced to reduce the input capacitance Ciss, and the channel length can be shortened to reduce the channel resistance.

3. Method for Manufacturing Trench Gate Power MOSFET According to Embodiment 1 The trench gate power MOSFET 100 according to Embodiment 1 can be manufactured by the following method.

  4 to 9 are views for explaining the method of manufacturing the trench gate type power MOSFET according to the first embodiment. 4 (a) to 4 (c), 5 (a) to 5 (c), 6 (a) to 6 (c), 7 (a) to 7 (c), 8 FIGS. 9A to 8C and FIGS. 9A to 9C are process diagrams.

(1) Semiconductor Substrate Preparation Step As shown in FIG. 4A, a third semiconductor layer that becomes an n ⁺ -type drain layer 112, a first semiconductor layer that becomes an n ⁻ -type drift layer 114, and a p-type body layer 120 are formed. A semiconductor substrate having a structure in which a second semiconductor layer 120 ′ is provided and the first semiconductor layer and the second semiconductor layer 120 ′ are epitaxially grown in this order on the third semiconductor layer is prepared.

Thereafter, as shown in FIG. 4B, p-type impurities (for example, boron ions) are applied from the surface of the second semiconductor layer 120 ′ to the second semiconductor layer 120 ′ at a high acceleration voltage (for example, 130 keV), 1 × 10 ^12. Ions are implanted at a dose of cm ⁻² , and then the semiconductor substrate is subjected to heat treatment (for example, 400 ° C.) to activate the p-type impurities. As a result, as shown in FIG. 4C, the semiconductor substrate has a depth position (p-type semiconductor layer 124) where the concentration of the p-type impurity in the p-type body layer 120 has a maximum value (p-type body layer 120). The semiconductor substrate is present between the surface (p ⁻ type semiconductor layer 122) and the bottom surface (p ⁻ type semiconductor layer 126) of the p type body layer 120.

(2) Groove Formation Step Thereafter, as shown in FIGS. 5A and 5B, a groove 130 is formed so as to reach the n ⁻ type drift layer 114 from the surface of the p-type body layer 120. The depth of the groove is, for example, 11 μm.

(3) Gate Insulating Film Formation Step Thereafter, as shown in FIG. 5C, a silicon oxide film 131 is formed by a vapor phase method so as to fill the trench 130 from the surface side of the p-type body layer 120.
Thereafter, as shown in FIG. 6A, the silicon oxide film 131 is etched back, and the silicon oxide film 131 is removed with the silicon oxide film 131 left only at the bottom of the trench 130.
Thereafter, as shown in FIG. 6B, the semiconductor substrate is subjected to a heat treatment under an oxidizing atmosphere to form a thermal oxide film 131 ′ on the inner surface of the groove 130.
As a result, gate insulating films 132 (131, 131 ′) are formed on the inner peripheral surface of the trench 130, as shown in FIG.

(4) Gate Electrode Layer Formation Step Thereafter, as shown in FIG. 6C, a doped polysilicon film 133 is formed so as to fill the trench 130 from the surface side of the p-type body layer 120.
Thereafter, as shown in FIG. 7A, the polysilicon film 133 is etched back, and the polysilicon film 133 is removed with the polysilicon film 133 remaining only in the trench 130. Thereby, the gate electrode layer 134 is formed on the inner peripheral surface of the trench 130.

(5) n ⁺ Type Source Region Formation Step After that, as shown in FIG. 7B, after forming a mask M1 in a predetermined region on the surface of the p type body layer 120, an n type impurity ( For example, phosphorus ions are implanted, and then the semiconductor substrate is subjected to a heat treatment to activate n-type impurities. As a result, n ⁺ -type source region 140 is formed in p-type body layer 120 so that at least a part thereof is exposed on the inner peripheral surface of trench 130.

(6) Step of forming p ⁺ -type contact region After that, as shown in FIG. 7C, after forming a mask M2 in a predetermined region on the surface of the p-type body layer 120, a p-type impurity ( For example, boron ions are implanted, and then the semiconductor substrate is heat-treated to activate the p-type impurities. Thereby, ap ⁺ type contact region 142 is formed on the surface of p type body layer 120.

(7) Protective Insulating Film Forming Step After that, as shown in FIG. 8A, after removing the thermal oxide film 131 on the surface of the p-type body layer 120, as shown in FIG. A thermal oxide film 135 of silicon is formed on the surface of the p-type body layer 120 and the inner peripheral surface of the upper portion of the groove 130 by heat treatment, and then the surface side of the p-type body layer 120 as shown in FIG. Then, a PSG film 135 ′ is formed by a vapor phase method, and then the silicon thermal oxide film 135 and the PSG film 135 ′ are removed by etching leaving the upper portion of the gate electrode layer 134. As a result, as shown in FIG. 9A, the protective insulating film 136 is formed on the gate electrode layer 134.

(8) Source Electrode Layer Formation Step Thereafter, as shown in FIG. 9B, the source electrode layer 150 is formed so as to cover the p-type body layer 120 and the protective insulating film 136.

(9) Drain Electrode Layer Formation Step Thereafter, as shown in FIG. 9C, a drain electrode layer 160 is formed on the surface of the n ⁺ type drain layer.

  As described above, the trench gate type power MOSFET 100 according to the first embodiment can be manufactured.

FIG. 10 illustrates the reason why it is possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies even when the diffusion depth of the n-type impurity varies when forming the n ⁺ -type source region. FIG. FIG. 10A is a diagram showing an n ⁺ type source region forming step in the process of manufacturing the trench gate type power MOSFET 100 according to the first embodiment, and FIG. 10B is a conventional trench gate type power as a comparative example. 5 is a diagram showing an n ⁺ type source region forming step in the process of manufacturing a MOSFET 900. FIG.

As can be seen from FIG. 10, in the n ⁺ -type source region forming step, the n-type impurity is an inner peripheral surface of the trench 130 even in a portion where the gate electrode layer 134 is not buried in the trench 130 (plug loss portion). Therefore, the diffusion depth of the n-type impurity varies depending on the degree of plug loss. At this time, in the trench gate type power MOSFET 100 according to the first embodiment, the depth position where the concentration of the p-type impurity in the p-type body layer 120 shows the maximum value is deeper than the bottom surface of the n ⁺ source region 140. Therefore, as shown in FIG. 2, even if the diffusion depth of the n-type impurity varies when forming the n ⁺ -type source region, it is possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies. Become. On the other hand, in the conventional trench gate type power MOSFET 900 as a comparative example, the depth position where the concentration of the p-type impurity in the p-type body layer 920 shows the maximum value is on the surface of the p-type body layer 920. As shown in FIG. 15, when the n ⁺ type source region is formed, the threshold value of the trench gate type power MOSFET varies due to the variation in the diffusion depth of the n type impurity.

[Embodiment 2]
FIG. 11 is a view for explaining the method of manufacturing the trench gate type power MOSFET according to the second embodiment. Fig.11 (a)-FIG.11 (c) are each process drawing.

  The manufacturing method of the trench gate type power MOSFET according to the second embodiment basically includes the same steps as those of the manufacturing method of the trench gate type power MOSFET according to the first embodiment. This is different from the method of manufacturing the trench gate type power MOSFET according to FIG.

  That is, in the method for manufacturing a trench gate type power MOSFET according to the second embodiment, as shown in FIG. 11, the p-type impurity is supplied from the surface of the n − type epitaxial layer 114 ′ at the first acceleration voltage V1 and the first dose. A step of ion-implanting by an amount D1, a step of ion-implanting a p-type impurity by a second acceleration voltage V2 higher than the first acceleration voltage V1 and a second dose amount D2 larger than the first dose amount D1, and p-type Performing a step of ion-implanting impurities at a third acceleration voltage V3 higher than the second acceleration voltage and a third dose amount D3 smaller than the second dose amount, and then subjecting the semiconductor substrate to a heat treatment, The depth position at which the concentration of the p-type impurity in the p-type body layer 120 has the maximum value is between the surface of the p-type body layer 120 and the bottom surface of the p-type body layer. It is to be present semiconductor substrate.

As described above, the manufacturing method of the trench gate type power MOSFET according to the second embodiment differs from the manufacturing method of the trench gate type power MOSFET according to the first embodiment in the content of the semiconductor substrate preparation process, but the first embodiment is different from the first embodiment. As in the case of the trench gate type power MOSFET, the depth position where the concentration of the p-type impurity in the p-type body layer 120 shows the maximum value is deeper than the lowermost surface of the n ⁺ -type source region 140. Even if the diffusion depth of the n-type impurity varies when the n ⁺ -type source region 140 is formed, the variation in the depth position at which the concentration of the p-type impurity in the p-type body layer 120 shows the maximum value and this are caused. Variations in the maximum concentration of p-type impurities in the body layer are suppressed. As a result, it is possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies. In addition, since the depths of the p-type body layer 120 and the n ⁺ -type source region 140 can be reduced, an effect that the input capacitance Ciss and the channel resistance can be reduced is also obtained.

  The method for manufacturing the trench gate type power MOSFET according to the second embodiment is the same as the method for manufacturing the trench gate type power MOSFET according to the first embodiment except for the content of the semiconductor substrate preparation step. 1 has a corresponding effect among the effects of the method for manufacturing a trench gate type power MOSFET according to 1.

[Embodiment 3]
FIG. 12 is a drawing for explaining the method of manufacturing the power MOSFET according to the third embodiment.

  The method for manufacturing a trench gate type power MOSFET according to the third embodiment also includes basically the same steps as the method for manufacturing the trench gate type power MOSFET according to the first embodiment, but the contents of the semiconductor substrate preparation step are the same as those in the first embodiment. This is different from the method of manufacturing the trench gate type power MOSFET according to FIG.

That is, in the method for manufacturing the trench gate type power MOSFET according to the third embodiment, as shown in FIG. 12, the p ⁻ type epitaxial layer 126, the p type epitaxial layer 124, and the p ⁻ type epitaxial layer are formed on the n ⁻ type epitaxial layer 114. A trench gate type power MOSFET is manufactured by using a semiconductor substrate having a structure in which layers 122 are sequentially stacked.

As described above, the manufacturing method of the trench gate type power MOSFET according to the third embodiment differs from the case of the manufacturing method of the trench gate type power MOSFET according to the first embodiment in the content of the semiconductor substrate preparation process, but the first embodiment is different from the first embodiment. As in the case of the trench gate type power MOSFET, the depth position where the concentration of the p-type impurity in the p-type body layer 120 shows the maximum value is deeper than the lowermost surface of the n ⁺ -type source region 140. Even if the diffusion depth of the n-type impurity varies when the n ⁺ -type source region 140 is formed, the variation in the depth position at which the concentration of the p-type impurity in the p-type body layer 120 shows the maximum value and this are caused. Variations in the maximum concentration of p-type impurities in the body layer are suppressed. As a result, it is possible to suppress the problem that the threshold value of the trench gate type power MOSFET varies. In addition, since the depths of the p-type body layer 120 and the n ⁺ -type source region 140 can be reduced, an effect that the input capacitance Ciss and the channel resistance can be reduced is also obtained.

  The method for manufacturing the trench gate type power MOSFET according to the third embodiment is the same as the method for manufacturing the trench gate type power MOSFET according to the first embodiment except for the contents of the semiconductor substrate preparation step. 1 has a corresponding effect among the effects of the method for manufacturing a trench gate type power MOSFET according to 1.

[Embodiment 4]
FIG. 13 is a view for explaining a trench gate type IGBT 200 according to the fourth embodiment.

  In the first to third embodiments described above, the trench gate type power semiconductor device of the present invention has been described taking the trench gate type power MOSFET as an example, but the present invention is not limited to this. The present invention is also applicable to, for example, a trench gate type IGBT.

That is, also in the trench gate type IGBT 200 according to the fourth embodiment, as shown in FIG. 13, the concentration of the p type impurity in the p type body layer 220 is the maximum, as in the case of the trench gate type power MOSFET according to the first embodiment. the depth position indicating the value, by a position deeper than the lowermost surface of the n ⁺ -type source region 240, even as the diffusion depth of the n-type impurity varies in forming the n ⁺ -type source region 240, Variations in the depth position where the concentration of the p-type impurity in the p-type body layer 220 shows the maximum value and variations in the maximum concentration of the p-type impurity in the p-type body layer due to this variation are suppressed. As a result, it is possible to suppress the problem that the threshold value of the trench gate type IGBT varies. In addition, since the depths of the p-type body layer 220 and the n ⁺ -type source region 240 can be reduced, an effect that the input capacitance Ciss and the channel resistance can be reduced is also obtained.

  As mentioned above, although the trench gate type power semiconductor device of the present invention was explained based on the above-mentioned embodiment, the present invention is not limited to this, and can be carried out without departing from the gist thereof, For example, the following modifications are possible.

(1) In each of the above embodiments, the semiconductor device of the present invention has been described with the first conductivity type as n-type and the second conductivity type as p-type. However, the present invention is not limited to this. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

100, 900 ... Power MOSFET, 110,210,910 ... semiconductor substrate, 112,912 ... ^{n +} -type drain layer, 114,214,914 ... n ^- -type drift layer, 114 '... n ^- -type epitaxial layer, 120, 220 920 ... p-type body layer, 120 '... p ^- type epitaxial layer, 122,222 ... p ^- type semiconductor layer, 122' ... p-type impurity introduction region, 124,224 ... p-type semiconductor layer, 124 '... p-type Impurity introduction region, 126, 226... P ⁻ type semiconductor layer, 126 ′... P type impurity introduction region, 130, 230, 930... Trench, 131... Silicon oxide film, 132, 232, 932. silicon layer, 134,934 ... gate electrode layer, 136,936 ... protective insulating film, 140,940 ... ^{n +} -type source region, 142,242,942 ... ⁺ -Type contact region, 150,950 ... source electrode layer, 160,960 ... drain electrode layer, 200 ... IGBT, 212 ... ^{p +} -type collector layer ^{(p +} -type drain layer), 240 ... ^{n +} -type emitter region ^{(n +} Type source region), 250... Emitter electrode layer (source electrode layer), 260... Collector electrode layer (drain electrode layer), M1, M2.

Claims (5)

A first conductivity type drift layer;
A body layer of a second conductivity type located on the drift layer and opposite to the first conductivity type;
A groove formed by opening the body layer and reaching the drift layer;
A source region of a first conductivity type disposed in the body layer and formed by exposing at least a part of the inner peripheral surface of the groove;
A gate insulating film formed on the inner peripheral surface of the groove;
A gate electrode layer formed on the inner peripheral surface of the gate insulating film;
A source electrode layer that is insulated from the gate electrode layer and formed in contact with the source region;
A trench gate type power semiconductor device for manufacturing a trench gate type power semiconductor device in which the depth position where the concentration of the second conductivity type impurity in the body layer shows the maximum value is deeper than the bottom surface of the source region. A manufacturing method of
A first conductivity type first semiconductor layer serving as the drift layer and a second conductivity type second semiconductor layer serving as the body layer, wherein the second semiconductor layer is stacked on the first semiconductor layer; A semiconductor substrate preparation step of preparing a semiconductor substrate;
A groove forming step of forming a groove so as to reach the first semiconductor layer from the surface of the second semiconductor layer;
Forming a gate insulating film on the inner peripheral surface of the groove; and
Forming a gate electrode layer on the inner peripheral surface of the gate insulating film; and
A source region forming step of forming a first conductivity type source region in the second semiconductor layer so that at least a part thereof is exposed on the inner peripheral surface of the groove;
A protective insulating film forming step of forming a protective insulating film so as to cover the gate electrode layer;
A source electrode forming step of forming a source electrode so as to cover the second semiconductor layer and the protective insulating film in this order,
In the semiconductor substrate preparation step, the second conductivity type impurity is ion-implanted from the surface side of the first conductivity type epitaxial layer by the first acceleration voltage V1 and the first dose amount D1, and the second conductivity type impurity is added. A step of ion-implanting a second acceleration voltage V2 higher than the first acceleration voltage V1 and a second dose amount D2 larger than the first dose amount D1, and a second conductivity type impurity from the second acceleration voltage V2. A semiconductor substrate formed by performing ion implantation with a higher third acceleration voltage V3 and a third dose amount D3 smaller than the second dose amount D2, and then subjecting the epitaxial layer to heat treatment. A depth position having a structure in which the second semiconductor layer is stacked on the first semiconductor layer, and the concentration of the second conductivity type impurity in the second semiconductor layer is maximum. The method of the trench gate type power semiconductor device for preparing a semiconductor substrate which exists between the bottom surface of the second semiconductor layer and the second semiconductor layer surface. In the manufacturing method of the trench gate type power semiconductor device according to claim 1,
A method of manufacturing a trench gate type power semiconductor device, wherein a depth position where the concentration of the second conductivity type impurity in the body layer shows a maximum value is at a position deeper than 2 μm from the lowermost surface of the source region. In the manufacturing method of the trench gate type power semiconductor device according to claim 1 or 2,
A method of manufacturing a trench gate type power semiconductor device, wherein a depth position where the concentration of the second conductivity type impurity in the body layer shows a maximum value is at a position deeper than the surface of the body layer by 4 μm or more. In the manufacturing method of the trench gate type power semiconductor device according to any one of claims 1 to 3,
The trench gate type power semiconductor device is a trench gate type power MOSFET,
The semiconductor substrate preparing step includes a first conductive type third semiconductor layer serving as the drain layer, the first semiconductor layer, and the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are provided on the third semiconductor layer A method for manufacturing a trench gate type power semiconductor device, comprising preparing a semiconductor substrate having a structure in which the second semiconductor layers are stacked in this order. In the manufacturing method of the trench gate type power semiconductor device according to any one of claims 1 to 3,
The trench gate type power semiconductor device is a trench gate type IGBT,
The semiconductor substrate preparation step includes a second conductive type fourth semiconductor layer serving as the collector layer, the first semiconductor layer, and the second semiconductor layer, and the first semiconductor layer and the fourth semiconductor layer are provided on the fourth semiconductor layer. A method for manufacturing a trench gate type power semiconductor device, comprising preparing a semiconductor substrate having a structure in which the second semiconductor layers are stacked in this order.

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