JP5805052B2 - Clock circuit - Google Patents

Description

  The present invention relates to a clock circuit.

  There is a clock tree circuit as a circuit for supplying a clock signal to a plurality of logic circuits without delay (see, for example, Patent Document 1).

  In the clock tree circuit, by connecting the inputs of a plurality of clock drivers at the next stage to the output of each clock driver, the clock signal is branched to generate a plurality of clock signals.

JP 2007-336003 A

  In recent years, circuits in electronic devices have become complicated, and a plurality of clock domains are provided, and a logic circuit is designed in each clock domain. Even in this case, it is required to supply the clock signal to the logic circuit of each clock domain so that there is no delay between the clock domains.

  FIG. 3 is a block diagram illustrating an example of a clock circuit that supplies a clock signal to a plurality of clock domains.

  Normally, a clock tree circuit corresponding to the scale of the logic circuit in the clock domain is provided in the clock domain. Therefore, when the scale of the logic circuit is different for each clock domain, the number of stages of the clock tree circuit is different. For example, in the example illustrated in FIG. 3, the clock tree circuit 121 in the second clock domain 102 has more stages than the clock tree circuit 111 in the first clock domain 101, and the clock signal supplied to the logic circuit 112 by the clock tree circuit 111. The number of clock signals that the clock tree circuit 121 supplies to the logic circuit 122 is larger than the number.

  In such a case, the delay of the clock signal in the clock tree circuit 111 is different from the delay of the clock signal in the clock tree circuit 121 due to the difference in the number of stages. Therefore, by inserting the buffer circuit 113 before the clock tree circuit 111 with less delay, the clock signal supplied to the logic circuit 112 of the first clock domain 101 and the logic circuit 122 of the second clock domain 102 are supplied. This eliminates the delay between the clock signal.

  In recent years, there has been a demand for energy saving of electronic devices, and it is required in design to stop supplying power for circuits that do not require operation.

  For example, as described above, in the power saving mode of the first clock domain 101 and the second clock domain 102, the supply of power to the second clock domain 102 is stopped and the operation of the logic circuit 122 is stopped. It is possible. In that case, the circuit in the first clock domain 101 continues to operate.

  However, even when the supply of power to the second clock domain 102 having a large circuit scale is stopped, the buffer 113 continues to operate even though the adjustment of the delay amount by the buffer 113 is unnecessary. Power consumption due to will continue. It is possible to synchronize clocks between clock domains by using a PLL (Phase Locked Loop) without using such a buffer 113. In such a case, however, the circuit scale becomes large due to the PLL circuit. As a result, the cost of the circuit increases.

  The present invention has been made in view of the above problems, and provides a clock circuit that reduces power consumption when power supply to one of the clock domains having clock tree circuits having different numbers of stages is stopped. The purpose is to obtain.

  In order to solve the above problems, the present invention is configured as follows.

  The clock circuit according to the present invention includes a first clock domain having a first clock tree circuit, a second clock domain having a second clock tree circuit having a higher number of stages than the first clock tree circuit, and the second clock domain. A delay circuit provided; and a selection circuit provided in the first clock domain. An original clock signal is input to the second clock tree circuit and the delay circuit, and the selection circuit outputs a clock output from the delay circuit when power is supplied to the second clock domain. A signal is selected and input to the first clock tree circuit. When power is not supplied to the second clock domain, the original clock signal is selected and input to the first clock tree circuit.

  As a result, when the power supply to the second clock domain is stopped, the operation of the delay circuit stops, so that the power supply to one of the clock domains each having a clock tree circuit having a different number of stages is stopped. Less power consumption.

  In addition to the clock circuit described above, the clock circuit according to the present invention may be configured as follows. In this case, the clock circuit further includes a control circuit that is provided in the first clock domain and controls supply of power supply power to the second clock domain. The control circuit controls the selection circuit in response to the control of the supply of power to the second clock domain, and selects one of the clock signal output from the delay circuit and the original clock signal. To the first clock tree circuit.

  In addition to the clock circuit described above, the clock circuit according to the present invention may be configured as follows. In this case, when the control circuit stops the supply of power to the second clock domain, the control circuit receives the clock signal input to the first clock tree circuit from the clock signal from the delay circuit. Then, after switching to the original clock signal, the supply of power to the second clock domain is stopped.

  In addition to the clock circuit described above, the clock circuit according to the present invention may be configured as follows. In this case, the selection circuit is a glitchless selector.

  In addition to the clock circuit described above, the clock circuit according to the present invention may be configured as follows. In this case, the first clock domain and the second clock domain exist in one integrated circuit.

  According to the present invention, it is possible to obtain a clock circuit that consumes less power when the supply of power to one of the clock domains having clock tree circuits having different numbers of stages is stopped.

FIG. 1 is a block diagram showing a configuration of a clock circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of the clock tree circuit in FIG. FIG. 3 is a block diagram illustrating an example of a clock circuit that supplies a clock signal to a plurality of clock domains.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a clock circuit according to an embodiment of the present invention.

  The clock circuit shown in FIG. 1 supplies a clock signal to the first clock domain 1 and the second clock domain 2 based on the original clock signal supplied to the first clock domain 1. In this embodiment, the first clock domain 1 and the second clock domain 2 exist in one integrated circuit.

  A clock tree circuit 11 is provided in the first clock domain 1, and a plurality of clock signals without delay are supplied to the logic circuit 12 by the clock tree circuit 11.

  The clock tree circuit 21 is provided in the second clock domain 2, and a plurality of clock signals without delay are supplied to the logic circuit 22 by the clock tree circuit 21.

  FIG. 2 is a circuit diagram illustrating an example of the clock tree circuit in FIG. In this clock circuit, since the number of clock signals output from the clock tree circuit 21 is larger than the number of clock signals output from the clock tree circuit 11, the clock tree circuit 11 in the first clock domain 1 is shown in FIG. The driver stage number N in the clock tree circuit 21 of the second clock domain 2 is larger than the driver stage number M in FIG. 2, and the delay of the clock signal in the clock tree circuit 21 is larger than the delay of the clock signal in the clock tree circuit 11.

  Returning to FIG. 1, a delay circuit 23 is provided in the second clock domain 2. The delay circuit 23 is a circuit that delays the original clock signal by the difference between the delay of the clock signal in the clock tree circuit 21 and the delay of the clock signal in the clock tree circuit 11.

  On the other hand, the first clock domain 1 is provided with a selection circuit 13 and a control circuit 14. For example, a glitchless selector is used for the selection circuit 13.

  When power is supplied to the second clock domain 2, the selection circuit 13 selects the clock signal output from the delay circuit 23 and inputs it to the first clock tree circuit 11, and supplies power to the second clock domain 2. When power is not supplied, the original clock signal is selected and input to the first clock tree circuit 11.

  The control circuit 14 controls the supply of power to the second clock domain 2. In addition, the control circuit 14 controls the selection circuit 13 in response to the control of the supply of power to the second clock domain 2 to select one of the clock signal output from the delay circuit 23 and the original clock signal. The first clock tree circuit 11 is supplied.

  In this embodiment, the control circuit 14 supplies power to the second clock domain 2 when, for example, the operation mode of the electronic device incorporating the clock circuit shifts from the normal mode to the power saving mode. When stopping, the selection circuit 13 switches the clock signal input to the first clock tree circuit 11 from the clock signal from the delay circuit 23 to the original clock signal, and then the power supply power to the second clock domain 2 is changed. Stop supplying.

  Next, the operation of the clock circuit will be described.

  When the circuit in the second clock domain 2 is operated, the control circuit 14 supplies power to the second clock domain 2 and supplies a clock signal output from the delay circuit 23 to the selection circuit 13 (that is, delayed). The original clock signal) is supplied to the first clock tree circuit 11. As a result, the delay between the clock signal output from the first clock tree circuit 11 and the clock signal output from the second clock tree circuit 21 is eliminated.

  On the other hand, if the circuit in the second clock domain 2 is not operated, the control circuit 14 stops the supply of power to the second clock domain 2 and sends the original clock signal to the selection circuit 13 and the first clock tree circuit. 11 is supplied. Thus, when the first clock domain 1 operates alone, power consumption in the delay circuit 23 does not occur.

  As described above, according to the above embodiment, when the second clock tree circuit 21 in the second clock domain 2 has more stages than the first clock tree circuit 11 in the first clock domain 1, the selection circuit 13 When the power supply power is supplied to the second clock domain 2, the clock signal output from the delay circuit 23 is selected and input to the first clock tree circuit 11, and the power supply power is supplied to the second clock domain 2. If not, the original clock signal is selected and input to the first clock tree circuit 11.

  As a result, when the supply of power to the second clock domain 2 is stopped, the operation of the delay circuit 23 stops, so that the clock tree circuits 11 and 21 having different numbers of stages are respectively supplied to one of the clock domains 1 and 2 When the power supply is stopped, power consumption is reduced.

  The above-described embodiments are preferred examples of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. is there.

  For example, in the above embodiment, a plurality of clock domains similar to the second clock domain 2 may be provided.

  The present invention is applicable to an electronic device having a plurality of clock domains, for example.

DESCRIPTION OF SYMBOLS 1 1st clock domain 2 2nd clock domain 11 1st clock tree circuit 13 Selection circuit 14 Control circuit 21 2nd clock tree circuit 23 Delay circuit

Claims (5)

A first clock domain having a first clock tree circuit;
A second clock domain having a second clock tree circuit having more stages than the first clock tree circuit;
A delay circuit provided in the second clock domain;
A selection circuit provided in the first clock domain,
An original clock signal is input to the second clock tree circuit and the delay circuit,
When the power is supplied to the second clock domain, the selection circuit selects a clock signal output from the delay circuit and inputs it to the first clock tree circuit, and supplies power to the second clock domain. Selecting and inputting the original clock signal to the first clock tree circuit when power is not supplied;
A clock circuit characterized by the above. A control circuit provided in the first clock domain for controlling supply of power to the second clock domain;
The control circuit controls the selection circuit in response to the control of the supply of power to the second clock domain, and selects one of the clock signal output from the delay circuit and the original clock signal. Feeding the first clock tree circuit;
The clock circuit according to claim 1.   When the control circuit stops supplying power to the second clock domain, the control circuit receives a clock signal to be input to the first clock tree circuit from the clock signal from the delay circuit to the original circuit. 3. The clock circuit according to claim 2, wherein the supply of power to the second clock domain is stopped after switching to the clock signal. The clock circuit according to any one of claims 1 to 3 , wherein the selection circuit is a glitchless selector. Wherein the first clock domain and the second clock domain, one clock circuit according to any one of claims 4 to be present in the integrated circuit claim 1, wherein the.

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