JP5772622B2 - Decoding device and decoding method - Google Patents

Description

  The present invention relates to a decoding technique, and more particularly, to a decoding device and a decoding method for decoding data encoded by LDPC.

  In recent years, LDPC (Low Density Parity Check Code) has attracted attention as an error correction code having strong error correction capability even in a low S / N transmission path, and is applied in many fields. In LDPC, data is encoded by an encoding matrix generated on the transmission side based on a sparse check matrix. Here, a sparse check matrix is a matrix having 1 or 0 elements and a small number of 1s. On the other hand, on the receiving side, data decoding and parity check are performed based on the check matrix. In particular, decoding performance is improved by iterative decoding using the BP (Belief Propagation) method or the like.

  In this decoding, a check node process for decoding in the row direction of the check matrix and a variable node process for decoding in the column direction are repeatedly executed. As one of the check node processes, sum-product decoding using a Gallager function or a hyperbolic function is known. In sum-product decoding, a channel value obtained from a variance value of transmission channel noise is used as a prior value. A decoding method that simplifies sum-product decoding is min-sum decoding. Therefore, min-sum decoding is used for simplifying and speeding up the processing. On the other hand, it is desirable to use shuffle decoding in order to accelerate convergence by iterative decoding. In the shuffle decoding, the priori value ratio is sequentially updated by immediately executing the variable node process on the column on which the check node process has been executed.

  In addition, as an example of applying LDPC decoding, a first decoding unit that includes a partial matrix representing a parity constraint and uses a check matrix and a partial matrix used for LDPC decoding to decode data so as to satisfy the parity constraint; There has also been proposed a technique that uses a second decoding unit that performs LDPC decoding of decoded data using a check matrix (see, for example, Patent Document 1).

JP 2009-271156 A

  When the two decoding methods of Viterbi decoding and LDPC decoding are used in combination as in the prior art, performance improvement can be expected, but the amount of calculation for executing Viterbi decoding is required, so the amount of calculation cannot be reduced. On the other hand, according to shuffle decoding, since variable node processing is sequentially executed after check node processing of each bit of each row, convergence can be made faster, but the amount of computation increases. Further, in the min-sum decoding and the sum-product decoding, when the variable node processing is executed after the check node processing of all the rows is completed, there is a feature that the convergence is slow but the calculation amount is small. Under such circumstances, it is desired to increase the speed while suppressing an increase in the amount of computation of LDPC decoding.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for increasing the convergence speed while suppressing an increase in the amount of calculation of LDPC decoding.

In order to solve the above problems, a decoding apparatus according to an aspect of the present invention includes an input unit that inputs data that has been subjected to LDPC encoding, and a first decoding that performs a first decoding process on the data input in the input unit A second decoding processing unit that executes a second decoding process different from the first decoding process, and a first decoding processing unit, the second decoding process for the data input in the input unit; And a control unit that controls the second decoding processing unit. The first decoding process executed in the first decoding processing unit and the second decoding process executed in the second decoding processing unit are both decoding processes that can be repeatedly executed. Based on the receiving unit that receives the decoding result in the repetition unit from the decoding processing unit or the second decoding processing unit, the deriving unit that derives the reliability of the decoding result received in the receiving unit, and the reliability derived in the deriving unit A selection unit that selects a first decoding processing unit or a second decoding processing unit that is to execute the decoding process in the next repetition unit. In the second decoding process executed in the second decoding processing unit, the calculation amount is smaller and the convergence speed is slower than in the first decoding process executed in the first decoding processing unit.

  According to this aspect, since the first decoding process or the second decoding process is selected in the next repetition unit based on the reliability of the decoding result in the repetition unit, the decoding process according to the decoding situation can be used. .

In this case , since the second decoding process with a small amount of computation and the first decoding process with a high convergence speed are combined, the convergence speed can be increased while suppressing an increase in the amount of computation.

Another aspect of the present invention is also a decoding device. The apparatus includes: an input unit that inputs data that has been subjected to LDPC encoding; a first decoding processing unit that executes a first decoding process on data input at the input unit; and a second decoding unit that receives data input at the input unit A second decoding processing unit that performs a second decoding process different from the first decoding process, and a control unit that controls the first decoding processing unit and the second decoding processing unit. Prepare. The first decoding process executed in the first decoding processing unit and the second decoding process executed in the second decoding processing unit are both decoding processes that can be repeatedly executed. Based on the receiving unit that receives the decoding result in the repetition unit from the decoding processing unit or the second decoding processing unit, the deriving unit that derives the reliability of the decoding result received in the receiving unit, and the reliability derived in the deriving unit A selection unit that selects a first decoding processing unit or a second decoding processing unit that is to execute the decoding process in the next repetition unit. The first decoding processing executed in the first decoding processing unit alternately executes row direction processing and column direction processing for each bit, and the second decoding processing executed in the second decoding processing unit is executed in the row direction. The column direction processing may be collectively executed after the processing is collectively executed. In this case, the processing amount is increased because the processing in which the row direction processing and the column direction processing are alternately executed for each bit and the processing in which the row direction processing is executed collectively and then the column direction processing are executed collectively are combined. Convergence speed can be increased while suppressing.

The selection unit may select the second decoding processing unit when the reliability degree is higher than another threshold value, and may select the first decoding processing unit in other cases. In this case, the amount of calculation can be reduced when the degree of reliability is higher than the threshold value, and the convergence speed can be increased in other cases.

  When the selection unit selects the second decoding processing unit, the decoding processing in the remaining repetition units may continuously select the second decoding processing unit. In this case, since the second decoding processing unit is continuously selected, an increase in the calculation amount can be suppressed.

The derivation unit may use a count value in a bit repetition unit having a log posterior probability ratio equal to or less than a threshold value as the reliability of the decoding result. In this case, since a log posterior probability ratio is used, new derivation can be made unnecessary.

Yet another embodiment of the present invention is a decoding method. This method includes a step of inputting data subjected to LDPC encoding, a step of executing a first decoding process on the input data, a second decoding process on the input data, and the first decoding A step of executing a second decoding process different from the process; a step of controlling the step of executing the first decoding process; and the step of executing the second decoding process. The first decoding process and the second decoding process are both decoding processes that can be repeatedly executed, and the controlling step is performed from the step of executing the first decoding process or the step of executing the second decoding process. A step of receiving a decoding result in the repetition unit, a step of deriving a reliability degree of the received decoding result, and a first decoding process to be executed in the next repetition unit based on the derived reliability degree Selecting a step of executing or a step of executing the second decoding process. In the second decoding process, the amount of calculation is smaller and the convergence speed is slower than in the first decoding process.
Yet another embodiment of the present invention is also a decoding method. This method includes a step of inputting data subjected to LDPC encoding, a step of executing a first decoding process on the input data, a second decoding process on the input data, and the first decoding A step of executing a second decoding process different from the process; a step of controlling the step of executing the first decoding process; and the step of executing the second decoding process. The first decoding process and the second decoding process are both decoding processes that can be repeatedly executed, and the controlling step is performed from the step of executing the first decoding process or the step of executing the second decoding process. A step of receiving a decoding result in the repetition unit, a step of deriving a reliability degree of the received decoding result, and a first decoding process to be executed in the next repetition unit based on the derived reliability degree Selecting a step of executing or a step of executing the second decoding process. In the first decoding process, the row direction process and the column direction process are alternately executed for each bit, and in the second decoding process, the row direction process is executed collectively, and then the column direction process is executed collectively.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to increase the convergence speed while suppressing an increase in the amount of computation of LDPC decoding.

It is a figure which shows the structure of the communication system which concerns on the Example of this invention. It is a figure which shows the test matrix used in the LDPC encoding part of FIG. It is a figure which shows the structure of the decoding part of FIG. It is a figure which shows the Tanner graph which represented typically the operation | movement of the decoding part of FIG. It is a figure which shows the outline | summary of the update of the external value ratio in the decoding part of FIG. It is a figure which shows the outline | summary of the update of the prior value ratio in the decoding part of FIG. FIGS. 7A to 7B are diagrams showing an outline of the operation of the decoding unit in FIG. It is a flowchart which shows the decoding procedure by the decoding part of FIG. It is a flowchart which shows another decoding procedure by the decoding part of FIG.

  Before describing the present invention specifically, an outline will be given first. Embodiments of the present invention include a transmission apparatus that performs LDPC encoding, and reception that repeatedly performs decoding on data encoded in the transmission apparatus (hereinafter referred to as “encoded data”) based on a check matrix. The present invention relates to a communication system including an apparatus. As described above, in the receiving apparatus, it is desired to increase the convergence speed while suppressing an increase in the amount of computation of LDPC decoding. In order to cope with this, the communication system according to the present embodiment, particularly the receiving apparatus, is configured as follows.

  The receiving apparatus can perform two types of decoding as LDPC decoding. The first is shuffle decoding, in which one row of check node processing in the row direction is executed, and then variable node processing in the column direction is sequentially executed (hereinafter referred to as “first decoding”). Second, the check node processing in the row direction is collected and then the variable node processing in the column direction is executed collectively (hereinafter referred to as “second decoding”). In both the first decoding and the second decoding, the min-sum algorithm is used for the check node process. When the reception apparatus acquires the decoding result of the repetition unit in the first decoding or the second decoding, the receiving apparatus derives the reliability for the decoding result. If the reliability is low, the receiving apparatus performs the first decoding on the next repetition unit. On the other hand, if the reliability is high, the receiving apparatus performs the second decoding on the next repetition unit. The receiving apparatus repeats such processing. That is, if the reliability is low, the convergence speed is increased by the first decoding, and if the reliability is high, an increase in the amount of calculation is suppressed by the second decoding.

  FIG. 1 shows a configuration of a communication system 100 according to an embodiment of the present invention. The communication system 100 includes a transmission device 10 and a reception device 12. The transmission apparatus 10 includes an information data generation unit 20, an LDPC encoding unit 22, and a modulation unit 24. The receiving device 12 includes a demodulator 26, a decoder 28, and an information data output unit 30.

  The information data generation unit 20 acquires data to be transmitted and generates information data. The acquired data may be used as information data as it is. The information data generation unit 20 outputs the information data to the LDPC encoding unit 22. The LDPC encoding unit 22 receives information data from the information data generation unit 20. The LDPC encoding unit 22 adds a parity (hereinafter referred to as “LDPC parity”) based on a parity check matrix in LDPC to information data. Information data to which the LDPC parity is added corresponds to the encoded data described above. The LDPC encoding unit 22 outputs the encoded data to the modulation unit 24. FIG. 2 shows a parity check matrix used in the LDPC encoding unit 22. The check matrix Hmn is a matrix of m rows and n columns. Here, in order to clarify the explanation, it is assumed that the parity check matrix Hmn is 4 rows and 8 columns and the elements of the parity check matrix are 1 and 0. However, the present invention is not limited to these. Returning to FIG.

  The modulation unit 24 receives encoded data from the LDPC encoding unit 22. The modulation unit 24 modulates the encoded data. As a modulation method, PSK (Phase Shift Keying), FSK (Frequency Shift Keying), or the like is used. The modulation unit 24 transmits the modulated encoded data as a modulation signal. The demodulator 26 receives the modulated signal from the modulator 24 via a communication path, for example, a wireless transmission path. The demodulator 26 demodulates the modulated signal. Since a known technique may be used for demodulation, the description is omitted here. The demodulator 26 outputs a demodulation result (hereinafter referred to as “demodulated data”) to the decoder 28.

The decoder 28 receives the demodulated data from the demodulator 26. The decoding unit 28 repeatedly performs a decoding process using a parity check matrix in LDCP on the demodulated data. The decoding process is executed in the following procedure.
1. Initialization: The prior value ratio is initialized and the maximum number of decoding iterations is set.
2. Check node processing: The external value ratio is updated in the row direction of the check matrix.
3. Variable node processing: The priori value ratio is updated in the column direction of the check matrix.
4). Calculate temporary estimated words.
Here, 2. 2. Check node processing and As described above, one of the first decoding and the second decoding is selected and executed for the variable node processing. The selection is made in units of repetition. For example, the first decoding is executed in the initial stage of decoding, and then the second decoding is executed. In the first decoding and the second decoding, 2. For the check node process, for example, a min-sum algorithm is executed.

  The decoding unit 28 outputs the decoding result (hereinafter referred to as “decoded data”) to the information data output unit 30. The information data output unit 30 inputs the decoded data from the decoding unit 28. The information data output unit 30 generates information data based on the decoded data. The decoded data may be used as information data as it is. The information data output unit 30 includes an outer code decoding unit, and may decode an outer code such as a CRC (Cyclic Redundancy Check), for example.

  This configuration can be realized in terms of hardware by a CPU, memory, or other LSI of any computer, and in terms of software, it can be realized by a program loaded in the memory, but here it is realized by their cooperation. Draw functional blocks. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  FIG. 3 shows the configuration of the decoding unit 28. The decoding unit 28 includes a frame configuration unit 40, a control unit 42, a data storage unit 44, a decoding result calculation unit 48, a first decoding processing unit 50, and a second decoding processing unit 52. The control unit 42 includes a reception unit 54, a derivation unit 56, and a selection unit 58.

  The frame configuration unit 40 inputs demodulated data from the demodulation unit 26 (not shown). The demodulated data can be said to be data that has been subjected to LDPC encoding via a communication channel. The frame configuration unit 40 detects a frame synchronization signal included in the demodulated data. The frame configuration unit 40 specifies a unit of a frame formed by the demodulated data based on the frame synchronization signal. For example, when the frame synchronization signal is arranged at the head portion of the frame and the frame period has a fixed length, the frame configuration unit 40 identifies the fixed-length period as a frame after detecting the frame synchronization signal. The unit of LDPC encoding may be a frame. The frame configuration unit 40 causes the data storage unit 44 to store the demodulated data collected in units of frames. The data storage unit 44 temporarily stores demodulated data in units of frames.

  The second decoding processing unit 52 performs second decoding on the data from the data storage unit 44, for example, demodulated data. As described above, in the second decoding, the row direction processing is collectively performed, and then the column direction processing is collectively performed. In the min-sum algorithm, check node processing and variable node processing are executed alternately. FIG. 4 is a Tanner graph schematically showing the operation of the decoding unit 28. In the Tanner graph, b1 to b8 are called variable nodes, and c1 to c4 are called check nodes. Here, the number of variable nodes is n, and bn is the nth variable node. The number of check nodes is m, and cm is the mth check node. Data y1 to y8 stored in the data storage unit 44 of FIG. 3 are connected to the variable nodes b1 to b8. Returning to FIG.

  As the check node process, a min-sum algorithm is executed. In the check node process, the priori value ratio β is initialized at the beginning of the iterative decoding. Here, the demodulated data stored in the data storage unit 44 is used as it is. Next, in the check node process, a minimum value min | βmn ′ | of the absolute value of the prior value ratio is obtained. In the check node process, the external value ratio αmn from cm to bm is updated with the variable node connected to the check node. The calculation of αmn is performed as follows for all pairs (m, n) satisfying the check matrix Hmn = 1.

αmn = a (Πsign (βmn ′)) · min | βmn ′ | (1)
Here, n ′ is A (m) \ n: A (m) is a variable node set connected to the check node m, and \ n indicates a difference set not including n. Further, sign represents a signature function, and min | βmn ′ | represents selection of the absolute minimum value. Here, a is a normalization constant. FIG. 5 shows an outline of the update of the external value ratio in the decoding unit 28. The external value ratio α11 is derived from β11 ′. That is, in the check node process, the external value ratio is updated based on the prior value ratio. Returning to FIG. The minimum value min | βmn ′ | of the absolute value of the prior value ratio is derived for each iteration.

In the variable node process, the prior value ratio βmn from bn to cm is updated between αmn and a check node connected to the variable node. The calculation of βmn is performed as follows for all pairs (m, n) satisfying the check matrix Hmn = 1.
βmn = Σαm′n + λn (2)
Here, λn is equal to the input data yn. The input data yn corresponds to demodulated data from the demodulator 26. M ′ is B (n) \ m: B (n) is a check node set connected to the variable node n, and \ m is a difference set not including m. FIG. 6 shows an overview of updating the prior value ratio in the decoding unit 28. The prior value ratio β11 is derived from α1′1. That is, in the variable node process, the prior value ratio is updated based on the external value ratio. Returning to FIG. When the decoding process for the repetition unit is completed, the second decoding processing unit 52 outputs the result (hereinafter referred to as “decoding result”) to the data storage unit 44. The decoding result includes the external value ratio αmn, the prior value ratio βmn, and the log posterior probability ratio Ln.

  The first decoding processing unit 50 performs first decoding on data from the data storage unit 44, for example, demodulated data. As described above, the first decoding corresponds to shuffle decoding, and the variable node processing in the column direction is executed after the check node processing in the row direction is executed by 1 bit. This corresponds to executing the row direction processing and the column direction processing alternately for each bit. That is, the first decoding and the second decoding are different. Note that the min-sum algorithm is also executed in the first decoding check node processing in the first decoding processing unit 50. Thus, the first decoding and the second decoding are both decoding processes that can be repeatedly executed. Further, the second decoding has a smaller calculation amount and a lower convergence speed than the first decoding. When the decoding process for each repetition unit is completed, the first decoding processing unit 50 outputs the result (hereinafter referred to as “decoding result”) to the data storage unit 44.

  The control unit 42 controls the first decoding processing unit 50 and the second decoding processing unit 52. Specifically, one of the first decoding processing unit 50 and the second decoding processing unit 52 is operated for each repetition unit. The reception unit 54 receives a decoding result from the data storage unit 44 every time the decoding process of the repetition unit is completed. This is a decoding result of a repetition unit made in the first decoding processing unit 50 or the second decoding processing unit 52.

  The deriving unit 56 derives the reliability of the decoding result received by the receiving unit 54. More specifically, the derivation unit 56 compares the log posterior probability ratio for each bit with a threshold value. Here, a bit having a log posterior probability ratio equal to or less than a threshold corresponds to a bit with low reliability. That is, the derivation unit 56 uses the log posterior probability ratio as the reliability of the decoding result. The deriving unit 56 counts the number of detected low reliability bits in the repetition unit. The deriving unit 56 outputs the count value to the selection unit 58.

  The selection unit 58 inputs the count value from the derivation unit 56. Based on the count value, the selection unit 58 selects the first decoding processing unit 50 or the second decoding processing unit 52 that is to execute the decoding processing in the next iteration unit. The selection unit 58 selects the first decoding processing unit 50 when the count value is equal to or greater than the threshold value, and selects the second decoding processing unit 52 when the count value is lower than the threshold value. This corresponds to selecting the second decoding processing unit 52 when the reliability is higher than the threshold and selecting the first decoding processing unit 50 in other cases. The control unit 42, the first decoding processing unit 50, and the second decoding processing unit 52 repeat the above-described processing until the number of repeated decoding is reached. In addition, when the selection unit 58 selects the second decoding processing unit 52 during the iterative decoding, the decoding processing in the remaining repetition units may continuously select the second decoding processing unit 52. When the number of iterations is reached, iterative decoding is terminated and the final decoding result is stored in the data storage unit 44.

  The decoding result calculation unit 48 calculates a temporary estimated word based on the decoding result stored in the data storage unit 44 after the processes in the first decoding processing unit 50 and the first decoding processing unit 50 are repeated a predetermined number of times. To do. Note that the decoding result calculation unit 48 may calculate a temporary estimated word even if the result of the parity check is correct even before being repeated a predetermined number of times. The decoding result calculation unit 48 outputs the temporary estimated word as a decoding result.

  7A to 7B show an outline of the operation of the decoding unit 28. FIG. Here, as an example, a case where the number of repetitions is 8 and the threshold value of the low reliability bit is “100” is shown. Therefore, the first decoding is selected when the low reliability bit is 100 or more, and the second decoding is selected when the low reliability bit is less than 100. FIG. 7A shows a result when the number of low reliability bits is confirmed every time for each repeating unit. As shown in the figure, the first decoding is selected because the number of low reliability bits is 200 for the first iteration, and similarly, the first decoding is selected for the second and third iterations. In the fourth iteration, since the number of low reliability bits is 90, the second decoding is selected. In the fifth iteration, since there are 105 low reliability bits, the first decoding is selected again. Hereinafter, since the number of low reliability bits is less than 100 at the sixth to eighth iterations, the second decoding is selected.

  FIG. 7B shows the result when the number of low reliability bits is confirmed until the number of low reliability bits becomes less than the threshold value. As shown in the figure, the first decoding is selected because the number of low reliability bits is 200 for the first iteration, and similarly, the first decoding is selected for the second and third iterations. In the fourth iteration, since the number of low reliability bits is 90, the second decoding is selected. Once the second decoding is selected, the number of low reliability bits is not counted in subsequent iterations, and the second decoding is selected. The amount of calculation is reduced by omitting the count of the number of low reliability bits and executing the second decoding.

  The operation of the communication system 100 configured as above will be described. FIG. 8 is a flowchart showing a decoding procedure by the decoding unit 28. The data storage unit 44 stores the demodulated data (S10). The deriving unit 56 derives the reliability from the log posterior probability ratio Ln, determines that the bit is a low reliability bit when the reliability is equal to or less than a threshold value, and counts the number of low reliability bits. (S12). If the low reliability bit count value is equal to or greater than the threshold value (Y in S14), the selection unit 58 selects the first decoding processing unit 50 (S16). On the other hand, if the low reliability bit count value is not equal to or greater than the threshold value (N in S14), the selection unit 58 selects the second decoding processing unit 52 (S18). If the decoding process has not been repeated a predetermined number of times (N in S20), the process returns to step 12. If the decoding process has been repeated a predetermined number of times (Y in S20), the decoding result calculation unit 48 calculates and outputs the decoding result (S22).

  FIG. 9 is a flowchart showing another decoding procedure by the decoding unit 28. The difference from FIG. 8 is that once the second decoding is selected, the second decoding is always selected in the subsequent repetition unit. The data storage unit 44 stores demodulated data (S50). The deriving unit 56 derives the reliability from the log posterior probability ratio Ln, determines that the bit is a low reliability bit when the reliability is equal to or less than a threshold value, and counts the number of low reliability bits. (S52). If the low reliability bit count value is equal to or greater than the threshold value (Y in S54), the selection unit 58 selects the first decoding processing unit 50 (S56). If the decoding process has not been repeated a predetermined number of times (N in S58), the process returns to step 52. On the other hand, if the low reliability bit count value is not equal to or greater than the threshold value (N in S54), the selection unit 58 selects the second decoding processing unit 52 (S60). If the decoding process has not been repeated a predetermined number of times (N in S62), the process returns to step 60. If the decoding process has been repeated a predetermined number of times (Y in S58) (Y in S62), the decoding result calculation unit 48 calculates and outputs the decoding result (S22).

  According to the embodiment of the present invention, since the first decoding or the second decoding is selected in the next repetition unit based on the reliability of the decoding result in the repetition unit, the decoding process according to the decoding situation can be used. . In addition, since the second decoding with a small amount of calculation and the first decoding with a high convergence speed are combined, the convergence speed can be increased while suppressing an increase in the amount of calculation. In addition, since the first decoding in which the row direction processing and the column direction processing are alternately executed for each bit and the second decoding in which the row direction processing is collectively performed and then the column direction processing is collectively performed are combined, The convergence speed can be increased while suppressing an increase in the amount. Further, since the first decoding is selected in a situation where the reliability is low, and the second decoding is selected if the reliability is high, the convergence speed can be increased in a situation where the reliability is low, and the reliability becomes high. The amount of calculation can be reduced. When the second decoding is selected, the second decoding is continuously selected thereafter, so that an increase in the amount of computation can be suppressed. Further, since the log posterior probability ratio is used as the reliability, a new derivation can be eliminated.

  In addition, for each iterative decoding according to the count value of the bits with low reliability, the first decoding with fast convergence is selected when there are many bits with low reliability, and the amount of calculation is small when there are few bits with low reliability. By selecting the second decoding, it is possible to improve the performance while suppressing the amount of calculation. Further, by counting the bits with low reliability and selecting the first decoding if the count value is greater than or equal to the threshold, and selecting the second decoding if the count value is less than the threshold, Compared with the case where 2 decoding is used fixedly and with the same amount of computation, decoding performance can be improved. Further, when compared with these in the same performance, the amount of calculation can be reduced.

  In the above, this invention was demonstrated based on the Example. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. .

  In the embodiment of the present invention, since the communication system 100 is premised on a wireless communication system, the transmission device 10 and the reception device 12 are included in the wireless communication device. However, the present invention is not limited to this. For example, the communication system 100 may be based on a wired communication system. At that time, the transmission device 10 and the reception device 12 are included in the wired communication device. According to this modification, the present invention can be applied to various devices.

  In the embodiment of the present invention, the derivation unit 56 uses the log posterior probability ratio as the reliability. However, not limited to this, for example, the derivation unit 56 may use a log likelihood ratio as the reliability. According to this modification, the degree of freedom in design can be improved.

  In the embodiment of the present invention, the first decoding processing unit 50 or the second decoding processing unit 52 is selected for each repetition unit. However, the present invention is not limited to this, and switching from the first decoding processing unit 50 to the second decoding processing unit 52 may be performed in the middle of the repetition unit. According to this modification, two types of decoding can be switched in detail.

  In the embodiment of the present invention, the decoding unit 28 executes a min-sum algorithm. However, the present invention is not limited to this. For example, the decoding unit 28 may execute a sum-product algorithm instead of the min-sum algorithm. According to this modification, decoding characteristics can be improved.

  In the embodiment of the present invention, the first decoding processing unit 50 and the second decoding processing unit 52 have different configurations. However, the present invention is not limited to this. For example, even if the configuration for executing the check node processing and the configuration for executing the variable node processing are shared among the first decoding processing unit 50 and the second decoding processing unit 52. Good. According to this modification, the circuit scale can be reduced.

  DESCRIPTION OF SYMBOLS 10 Transmitter, 12 Receiver, 20 Information data generation part, 22 LDPC encoding part, 24 Modulation part, 26 Demodulation part, 28 Decoding part, 30 Information data output part, 40 Frame structure part, 42 Control part, 44 Data storage Unit, 48 decoding result calculation unit, 50 first decoding processing unit, 52 second decoding processing unit, 54 reception unit, 56 derivation unit, 58 selection unit, 100 communication system.

Claims (7)

An input unit for inputting LDPC-encoded data;
A first decoding processing unit that performs a first decoding process on data input in the input unit;
A second decoding processing unit that executes a second decoding process different from the first decoding process, which is a second decoding process for data input in the input unit;
A control unit that controls the first decoding processing unit and the second decoding processing unit;
The first decoding process executed in the first decoding processing unit and the second decoding process executed in the second decoding processing unit are both decoding processes that can be repeatedly executed,
The controller is
A receiving unit for receiving a decoding result in a repetition unit from the first decoding processing unit or the second decoding processing unit;
A derivation unit for deriving the degree of reliability of the decryption result received by the reception unit;
A selection unit that selects the first decoding processing unit or the second decoding processing unit to execute the decoding processing in the next iteration unit based on the reliability degree derived by the derivation unit;
In the second decoding processing executed in the second decoding processing unit, than the first decoding processing executed in the first decoding processing unit, the calculation amount is small, and characterized in that the convergence speed is slow Decoding device . An input unit for inputting LDPC-encoded data;
A first decoding processing unit that performs a first decoding process on data input in the input unit;
A second decoding processing unit that executes a second decoding process different from the first decoding process, which is a second decoding process for data input in the input unit;
A control unit that controls the first decoding processing unit and the second decoding processing unit;
The first decoding process executed in the first decoding processing unit and the second decoding process executed in the second decoding processing unit are both decoding processes that can be repeatedly executed,
The controller is
A receiving unit for receiving a decoding result in a repetition unit from the first decoding processing unit or the second decoding processing unit;
A derivation unit for deriving the degree of reliability of the decryption result received by the reception unit;
A selection unit that selects the first decoding processing unit or the second decoding processing unit to execute the decoding processing in the next iteration unit based on the reliability degree derived by the derivation unit;
The first decoding processing executed in the first decoding processing unit alternately performs row direction processing and column direction processing for each bit,
The second second decoding process performed in the decoding processing unit, run together in the row direction processing, decoding apparatus and executes collectively column process. The decoding device according to claim 1, wherein the derivation unit uses a count value in a repetition unit of bits having a log posterior probability ratio equal to or less than a threshold value as a reliability degree of a decoding result . The said selection part selects the said 2nd decoding process part, when a reliability degree is higher than another threshold value, and selects the said 1st decoding process part in the other cases, The decoding device described . The selection unit according to any one of claims 1 to 4, wherein when the second decoding processing unit is selected, the decoding processing in the remaining repetitive units continuously selects the second decoding processing unit. The decoding device described. Inputting LDPC-encoded data;
Performing a first decryption process on the input data;
Executing a second decoding process for the input data, which is a second decoding process different from the first decoding process;
Controlling the step of executing the first decoding process and the step of executing the second decoding process,
The first decoding process and the second decoding process are both decoding processes that can be repeatedly executed,
The controlling step includes
Receiving a decoding result in a repetition unit from the step of executing the first decoding process or the step of executing the second decoding process;
Deriving the reliability of the received decryption result;
Selecting the step of executing the first decoding process or the step of executing the second decoding process to be executed based on the derived degree of reliability ;
In the second decoding process, the amount of calculation is smaller and the convergence speed is slower than in the first decoding process. Inputting LDPC-encoded data;
Performing a first decryption process on the input data;
Executing a second decoding process for the input data, which is a second decoding process different from the first decoding process;
Controlling the step of executing the first decoding process and the step of executing the second decoding process,
The first decoding process and the second decoding process are both decoding processes that can be repeatedly executed,
The controlling step includes
Receiving a decoding result in a repetition unit from the step of executing the first decoding process or the step of executing the second decoding process;
Deriving the reliability of the received decryption result;
Selecting the step of executing the first decoding process or the step of executing the second decoding process to be executed based on the derived degree of reliability ;
The first decoding process alternately performs a row direction process and a column direction process for each bit,
In the decoding method, the second decoding process is performed by collectively executing the row direction process and then the column direction process .

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