JP5761308B2 - LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a structure of a light emitting device using a light emitting material such as an organic EL (ElectroLuminescent) material.

  2. Description of the Related Art Conventionally, an active matrix light-emitting device in which a transistor that controls the amount of current supplied to a light-emitting element in accordance with a gate potential (hereinafter referred to as “driving transistor”) is arranged for each light-emitting element has been proposed (for example, Patent Document). 1). A capacitive element for setting and holding the potential is connected to the gate electrode of the driving transistor. The drive transistor is electrically connected to the light emitting element through a source metal patterned in a predetermined shape.

JP 2004-119219 A

  In order to meet the demand for higher definition of light emitting elements and downsizing of light emitting devices, it is necessary to reduce the area of each light emitting element by arranging the elements related to the light emitting element close to each other. However, capacitance is parasitic between elements adjacent to each other. For example, since the source metal and each electrode of the capacitive element in the above configuration are arranged close to each other via the insulating layer, capacitance is easily parasitic between the two. In addition, there is a problem that high-precision control of the behavior of the light-emitting element (light emission time length and light amount) is hindered due to the parasitic capacitance of each element. In the background as described above, the present invention aims to solve the problem of suppressing parasitic capacitance that affects light emission of a light emitting element.

One embodiment of the present invention is a driving transistor that controls the amount of current supplied to the light emitting element, and a capacitive element electrically connected to the gate electrode of the driving transistor (for example, the capacitive element C1 in FIG. 2, FIG. 25, and FIG. 26 capacitive elements C2) and element conduction portions (for example, element conduction portions 71, 72 and 73 in the respective embodiments) for electrically connecting the driving transistor and the light emitting elements are disposed on the substrate. Thus, the element conduction portion is disposed in a region opposite to the capacitor element with the driving transistor interposed therebetween. Specific examples of this aspect will be described later as first to third embodiments.
According to one aspect of the present invention, a data line extending in a first direction on a substrate, a scanning line extending in a second direction intersecting the first direction, and in the second direction and power lines that Mashimasu extension, a first electrode, a second electrode facing the first electrode, and a light emitting layer provided between the second electrode and the first electrode a light emitting element having a, a first transistor electrically connected between said power supply line and the light emitting element, between the source or drain of the gate and the first transistor of said first transistor A second transistor that is electrically connected; and a connection portion that electrically connects a gate of the first transistor and a source or drain of the second transistor ; view, the fact that disposed between the scanning line and the connecting portion And features.
One embodiment of the present invention is characterized in that the power supply line overlaps with the gate of the first transistor in a plan view and does not overlap with the gate of the second transistor.
In one aspect of the present invention, the power supply line includes a first portion extending in the first direction and a second portion extending in a direction intersecting the first direction. The data line includes a first data line and a second data line, and the first portion is between the first data line and the second data line in plan view. The second portion intersects the first data line and the second data line.
One embodiment of the present invention further includes a capacitive element electrically connected to the first transistor and the second transistor on the substrate, and the power supply line includes the first transistor in a plan view. And the capacitor element.

  According to this configuration, the element conduction portion is disposed on the opposite side of the capacitive element across the drive transistor, and therefore the element conduction portion is disposed in the gap between the drive transistor and the capacitance element when viewed from the direction perpendicular to the substrate. Compared to the configuration, the capacitance parasitic on the capacitive element and the element conduction portion is reduced. Therefore, it is possible to reduce the influence of the potential fluctuation in one of the capacitor element and the element conduction portion on the other potential.

  Note that the capacitor element is typically used for setting or holding the potential of the gate electrode of the driving transistor. For example, the capacitive element in one embodiment (for example, the capacitive element C1 in FIG. 2) is interposed between the gate electrode of the driving transistor and the data line. In this configuration, the gate electrode of the drive transistor is set to a potential corresponding to the amount of variation in the potential of the data line by capacitive coupling in the capacitive element. Further, the capacitive element (for example, the capacitive element C2 in FIGS. 25 and 26) in other modes is interposed between the gate electrode of the driving transistor and a wiring (for example, a power supply line) supplied with a constant potential. In this configuration, the potential supplied from the data line to the gate electrode of the driving transistor is held in the capacitor element.

  In a preferred aspect of the present invention, the driving transistor includes a semiconductor layer in which a channel region is formed and a gate electrode facing the channel region with the gate insulating layer interposed therebetween, and the capacitor is electrically connected to the gate electrode. A first electrode (for example, the electrode E1 in FIG. 2) and a second electrode (for example, the electrode E2 in FIG. 2) opposed to the first electrode with the gate insulating layer interposed therebetween. It is formed on the surface of an insulating layer (for example, the first insulating layer L1 in FIG. 4) covering the first electrode. According to this aspect, since the element conduction portion is formed from a different layer from the drive transistor and the capacitor element, the parasitic capacitance between the element conduction portion and the capacitance element is further reduced.

In a more preferred aspect, the first electrode of the capacitive element is continuous with the gate electrode of the driving transistor (for example, the intermediate conductors 51, 52 and 53 in each embodiment). According to this aspect, it is possible to reduce the space of the gap between the drive transistor and the capacitive element as compared with the configuration in which the first electrode and the gate electrode are formed apart from each other.
In another embodiment, the semiconductor layer of the driving transistor and the second electrode of the capacitor are formed from the same layer. According to this configuration, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the case where the semiconductor layer and the capacitor are formed from different layers. In the present invention, a plurality of elements are “formed from the same layer” means that a plurality of elements are formed by selective removal of a common film body (whether it is a single layer or a plurality of layers). It means that it is formed in the same process, and it does not matter whether each element is separated from each other or continuous.

  In a specific aspect of the present invention, a selection transistor that is turned on or off according to a selection signal is provided, and the gate electrode of the driving transistor is supplied from the data line through the selection transistor that is turned on. The selection transistor is arranged in a region opposite to the driving transistor across the capacitor. In a further preferred embodiment, the semiconductor layer of the selection transistor is continuous with the second electrode (for example, the semiconductor layers 41, 42, and 43), and the potential of the gate electrode of the driving transistor varies with the potential of the second electrode due to the supply of the data signal. It is set according to the amount (capacitive coupling by a capacitive element). In this aspect, since the semiconductor layer of the selection transistor is continuously formed on the second electrode, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the configuration in which each is formed from a different layer. .

  In a preferred aspect of the present invention, an initialization transistor that is turned on or off according to an initialization signal is provided, and the drive transistor is diode-connected via the initialization transistor that is turned on, and is initialized. The transistor is disposed in a region opposite to the capacitor element with the driving transistor interposed therebetween. According to this aspect, the gate electrode of the drive transistor diode-connected through the initialization transistor is set to a potential corresponding to the threshold voltage of the drive transistor. Therefore, it is possible to compensate for an error in the threshold voltage of the driving transistor.

In yet another aspect, the selection transistor is disposed on the opposite side of the drive transistor with the capacitor interposed therebetween, and is turned on or off according to the selection signal, and on the opposite side of the capacitance element with the selection transistor interposed therebetween. And an initialization transistor that is turned on or off according to the initialization signal, and the gate electrode of the driving transistor is connected to the data signal supplied from the data line through the selection transistor that is turned on. The drive transistor is diode-connected via the initialization transistor that is turned on, and the initialization transistor is connected to the gate electrode of the drive transistor via the connection portion (for example, the connection portion 62 in FIG. 15). The gate electrode of the selection transistor and the connection portion do not overlap each other.
According to this aspect, since the connection portion is formed so as not to overlap the gate electrode of the selection transistor, the selection transistor (or the selection line for transmitting the selection signal) is compared with the configuration in which the gate electrode and the connection portion overlap. ) And the connection are reduced. Therefore, the dullness (noise) of the waveform of the selection signal due to the fluctuation of the potential of the connection portion is suppressed, and as a result, the selection transistor can be operated at high speed at a predetermined timing.

  In this embodiment, the selection transistor includes a first gate electrode (for example, the first gate electrode 111 in FIG. 14) and a second gate electrode (for example, the second gate electrode in FIG. 14) that are spaced apart from each other. The connecting portion is located in the gap between the first gate electrode and the second gate electrode. According to this aspect, the selection transistor has a dual gate structure, thereby reducing current leakage in the selection transistor. Furthermore, since the connection portion is disposed so as not to overlap with either the first gate electrode or the second gate electrode, capacitive coupling between the selection transistor and the connection portion can be reliably suppressed.

  The light emitting device according to the present invention is used in various electronic devices. A typical example of this electronic device is a device that uses a light emitting device as a display device. Examples of this type of electronic device include a personal computer and a mobile phone. However, the use of the light emitting device according to the present invention is not limited to image display. For example, an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light, a device (backlight) that is arranged on the back side of the liquid crystal device and illuminates it, or The light emitting device of the present invention can be applied to various uses such as various illumination devices such as a device that illuminates a document by being mounted on an image reading device such as a scanner.

It is a block diagram which shows a mode that several unit elements are arranged in a light-emitting device. It is a circuit diagram which shows the electric constitution of each unit element. It is a top view which shows the structure of the unit element in 1st Embodiment of this invention. It is sectional drawing seen from the IV-IV line in FIG. It is a top view which shows the step in which the gate insulating layer was formed. It is a top view which shows the step in which the 1st insulating layer was formed. It is a top view which shows the step in which the 2nd insulating layer was formed. It is a top view which shows the several unit element in the step in which the 1st insulating layer was formed. It is a top view which shows the several unit element in the step in which the 2nd insulating layer was formed. It is sectional drawing for demonstrating the effect of embodiment. It is a circuit diagram for demonstrating the effect of embodiment. It is a top view which shows the structure of the unit element in 2nd Embodiment of this invention. It is a top view which shows the step in which the gate insulating layer was formed. It is a top view which shows the step in which the 1st insulating layer was formed. It is a top view which shows the step in which the 2nd insulating layer was formed. It is a top view which shows the several unit element in the step in which the 2nd insulating layer was formed. It is a top view which shows the step in which the 1st insulating layer was formed in the modification of 2nd Embodiment. It is a top view which shows the step in which the 2nd insulating layer was formed in the modification of 2nd Embodiment. It is a top view which shows the structure of the unit element in 3rd Embodiment of this invention. It is a top view which shows the step in which the gate insulating layer was formed. It is a top view which shows the step in which the 1st insulating layer was formed. It is a top view which shows the step in which the 2nd insulating layer was formed. It is a top view which shows the several unit element in the step in which the 2nd insulating layer was formed. It is a circuit diagram which shows the structure of the unit element which concerns on a modification. It is a circuit diagram which shows the structure of the unit element which concerns on a modification. It is a circuit diagram which shows the structure of the unit element which concerns on a modification. It is a perspective view of the personal computer which is a specific example of the electronic device which concerns on this invention. It is a perspective view of the mobile telephone which is a specific example of the electronic device which concerns on this invention. FIG. 11 is a perspective view of a portable information terminal which is a specific example of the electronic apparatus according to the invention.

<A: Electrical configuration of light emitting device>
FIG. 1 is a block diagram showing an electrical configuration of a light emitting device D according to the first to third embodiments of the present invention. As shown in the figure, the light emitting device D includes a plurality of selection lines 11, a plurality of initialization lines 12, and a plurality of data lines 13. Each selection line 11 and each initialization line 12 extend in the X direction. Each data line 13 extends in the Y direction orthogonal to the X direction. A unit element (pixel) P is disposed at each intersection of each pair of the selection line 11 and the initialization line 12 and the data line 13. Therefore, these unit elements P are arranged in a matrix form in the X direction and the Y direction. One unit element P is an element which becomes a minimum unit of light emission. Each unit element P is supplied with a high-potential power supply potential Vdd via a power supply line 15.

  FIG. 2 is a circuit diagram showing a configuration of each unit element P. As shown in the figure, the light emitting element E and the drive transistor Tdr are arranged on the path from the power supply line 15 to the ground line (ground potential Gnd). The light emitting element E is an element in which a light emitting layer 23 made of an organic EL material is interposed between a first electrode 21 (anode) and a second electrode 22 (cathode). The first electrodes 21 are formed so as to be separated from each other for each unit element P. The second electrode 22 is continuously formed over the plurality of unit elements P and grounded (Gnd). The light emitting layer 23 emits light with a light amount corresponding to the amount of current flowing from the first electrode 21 to the second electrode 22.

  The drive transistor Tdr is a p-channel thin film transistor for controlling the amount of current supplied to the light emitting element E in accordance with the potential of the gate electrode (hereinafter referred to as “gate potential”) Vg. The source electrode (S) of the driving transistor Tdr is connected to the power supply line 15, and the drain electrode (D) thereof is connected to the first electrode 21 of the light emitting element E.

  Between the gate electrode and the drain electrode of the drive transistor Tdr (the first electrode 21 of the light emitting element E), an n-channel transistor (hereinafter referred to as “initializing transistor”) for controlling the electrical connection between the two is provided. ) Tint intervenes. The gate electrode of the initialization transistor Tint is connected to the initialization line 12. An initialization signal Sb is supplied to the initialization line 12 from a drive circuit (not shown). When the initialization signal Sb becomes active level and the initialization transistor Tint is turned on, the gate electrode and the drain electrode of the drive transistor Tdr are electrically connected (diode connection).

  As shown in FIG. 2, the unit element P includes a capacitive element C1 composed of an electrode E1 and an electrode E2. The electrode E1 is connected to the gate electrode of the drive transistor Tdr. Between the electrode E 2 and the data line 13, an n-channel transistor (hereinafter referred to as “selection transistor”) Tsl for controlling the electrical connection therebetween is interposed. The gate electrode of the selection transistor Tsl is connected to the selection line 11. A selection signal Sa is supplied to the selection line 11 from a drive circuit (not shown). Note that the conductivity types of the drive transistor Tdr, the selection transistor Tsl, and the initialization transistor Tint are appropriately changed from the example of FIG.

  Next, the operation of one unit element P will be described by dividing it into an initialization period, a writing period, and a driving period. First, in the initialization period, a predetermined potential Vref is supplied from the drive circuit (not shown) to the data line 13, and the selection signal Sa of the selection line 11 and the initialization signal Sb of the initialization line 12 are active levels ( High level). Therefore, the potential Vref is supplied from the data line 13 to the electrode E2 of the capacitive element C1 via the selection transistor Tsl. Further, the drive transistor Tdr is diode-connected as the initialization transistor Tint is turned on. Therefore, the gate potential Vg of the drive transistor Tdr converges to a difference value (Vg = Vdd−Vth) between the power supply potential Vdd supplied to the power supply line 15 and the threshold voltage Vth of the drive transistor Tdr.

  Next, in the writing period after the lapse of the initialization period, the initialization signal Sb changes to the inactive level (low level). Accordingly, the initialization transistor Tint changes to the off state, and the diode connection of the drive transistor Tdr is released. Further, the potential Vref supplied from the data line 13 to the electrode E2 is changed to the data potential Vdata while the selection transistor Tsl is maintained in the on state. The data potential Vdata is a potential corresponding to the gradation specified for the unit element P.

Since the impedance of the gate electrode of the drive transistor Tdr is sufficiently high, when the electrode E2 changes by the change amount ΔV (= Vref−Vdata) from the potential Vref to the data potential Vdata, the potential of the electrode E1 is changed to capacitive coupling in the capacitive element C1. Therefore, the potential Vg (= Vdd−Vth) set in the initialization period varies. The amount of change in the potential of the electrode E1 at this time is determined according to the capacitance ratio between the capacitive element C1 and other parasitic capacitance (for example, the gate capacitance of the driving transistor Tdr or the capacitance parasitic on other wiring). More specifically, when the capacitance value of the capacitive element C1 is “C” and the capacitance value of the parasitic capacitance is “Cs”, the amount of change in the potential of the electrode E1 is expressed as “ΔV · C / (C + Cs)”. . Therefore, the gate potential Vg of the drive transistor Tdr is set to the level of the following formula (1) at the end of the writing period.
Vg = Vdd-Vth-k. [Delta] V (1)
However, k = C / (C + Cs)

  Next, in the driving period after the lapse of the writing period, the selection signal Sa changes to the inactive level and the selection transistor Tsl changes to the off state. Then, a current corresponding to the gate potential Vg of the drive transistor Tdr is supplied from the power supply line 15 to the light emitting element E via the source electrode and the drain electrode of the drive transistor Tdr. By supplying this current, the light emitting element E emits light with a light amount corresponding to the data potential Vdata.

Assuming that the driving transistor Tdr operates in the saturation region, the amount of current I supplied to the light emitting element E during the driving period is expressed by the following equation (2). In Equation (2), “β” is the gain coefficient of the drive transistor Tdr, and “Vgs” is the voltage between the gate and the source of the drive transistor Tdr.
I = (β / 2) (Vgs−Vth) ² (2)
= (Β / 2) (Vdd−Vg−Vth) ²
By substituting equation (1), equation (2) is transformed as follows.
I = (β / 2) (k · ΔV) ²
That is, the amount of current I supplied to the light emitting element E does not depend on the threshold voltage Vth of the drive transistor Tdr. Therefore, according to the present embodiment, an error in the light amount of the light emitting element E (due to variations in the threshold voltage Vth of each drive transistor Tdr (difference from the design value or difference from the drive transistors Tdr of other unit elements P)) ( (Unevenness in brightness) can be suppressed.

<B: Specific Structure of Unit Element P>
Next, a specific structure of the unit element P described above will be described with reference to the drawings. In each drawing referred to below, for convenience of explanation, the dimensions and ratios of the elements are appropriately changed from actual devices.

<B-1: First Embodiment>
First, a specific configuration of the unit element P of the light emitting device D according to the first embodiment of the present invention will be described. 3 is a plan view showing a configuration of one unit element P, and FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. Although FIG. 3 is a plan view, elements that are the same as those in FIG. 3 are appropriately hatched in the same manner as in FIG. The same applies to other plan views referred to below.

  As shown in FIG. 4, each element in FIG. 2 such as the drive transistor Tdr and the light emitting element E is formed on the surface of the substrate 10. The substrate 10 is a plate-like member made of various insulating materials such as glass and plastic. Each element of the unit element P may be formed on the surface of the substrate 10 with an insulating film covering the substrate 10 (for example, a film of silicon oxide or silicon nitride) as a base. Further, the light emitting device D of the present embodiment is a top emission type. Therefore, the substrate 10 is not required to have optical transparency.

  5 to 7 are plan views showing a state on the surface of the substrate 10 at each stage where the unit element P is formed. 5 to 7, the region A in which the first electrode 21 shown in FIG. 3 is to be formed is also indicated by a two-dot chain line.

  As shown in FIGS. 4 and 5, a semiconductor layer 31 and a semiconductor layer 41 are formed of a semiconductor material such as silicon on the surface of the substrate 10. The semiconductor layer 31 and the semiconductor layer 41 are collectively formed in the same process by patterning a film body formed continuously over the entire area of the substrate 10. As in the relationship between the semiconductor layer 31 and the semiconductor layer 41, a plurality of elements can be removed in the same process by selectively removing a common film body (whether it is a single layer or a plurality of layers). Hereinafter, the formation is simply referred to as “formed from the same layer”. Naturally, each element formed from the same layer is made of the same material, and the film thicknesses thereof are substantially the same. According to the configuration in which a plurality of elements are formed from the same layer, there is an advantage that the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with a configuration in which each of the elements is formed from another layer.

  As shown in FIGS. 4 and 5, the semiconductor layer 31 includes a first element unit 311 and a second element unit 312. The first element portion 311 is a substantially rectangular portion that functions as a semiconductor layer of the drive transistor Tdr. The second element portion 312 is a portion that functions as a semiconductor layer of the initialization transistor Tint, and is a region on the positive side in the X direction and the negative side in the Y direction as viewed from the first element portion 311 (that is, the upper right side of the first element portion 311). Part). More specifically, as shown in FIG. 5, the second element portion 312 extends from the first element portion 311 to the negative side in the Y direction, and extends from the portion 312a to the positive side in the X direction. A portion 312b and a portion 312c extending from the portion 312b to the positive side in the Y direction are included.

  The semiconductor layer 41 is a portion arranged on the positive side in the Y direction when viewed from the semiconductor layer 31, and is a substantially rectangular electrode E2 constituting the capacitive element C1 in FIG. 2 and an element extending from the electrode E2 in the Y direction. Part 411. The element portion 411 is a portion that functions as a semiconductor layer of the selection transistor Tsl, and is formed in a region on the negative side in the X direction and the positive side in the Y direction as viewed from the electrode E2 (that is, the lower left portion of the electrode E2).

  As shown in FIG. 4, the surface of the substrate 10 on which the semiconductor layer 31 and the semiconductor layer 41 are formed is covered with the gate insulating layer L0 over the entire area. As shown in FIGS. 4 and 6, the selection line 11, the initialization line 12, the intermediate conductor 51, and the first data line portion 131 are formed from the same layer by a conductive material on the surface of the gate insulating layer L0. Is done.

  The selection line 11 extends in the X direction over the plurality of unit elements P and overlaps the element portion 411 of the semiconductor layer 41. A region of the element portion 411 facing the selection line 11 with the gate insulating layer L0 interposed therebetween is a channel region of the selection transistor Tsl. The initialization line 12 extends in the X direction across the plurality of unit elements P and overlaps the second element portion 312 of the semiconductor layer 31. Of each of the portion 312a and the portion 312c of the second element portion 312, the region facing the initialization line 12 with the gate insulating layer L0 interposed therebetween is the channel region of the initialization transistor Tint. That is, the initialization transistor Tint in this embodiment is a dual gate transistor.

  The intermediate conductor 51 is a portion formed in a gap region between the selection line 11 and the initialization line 12 and includes an electrode E1, a gate electrode 511, and a connecting portion 513. The electrode E1 is a substantially rectangular portion that overlaps the electrode E2 of the semiconductor layer 41 when viewed from the direction perpendicular to the substrate 10. As shown in FIGS. 4 and 6, the electrode C1 and the electrode E2 face each other with the gate insulating layer L0 (dielectric material) interposed therebetween, so that the capacitive element C1 shown in FIG.

  The connecting portion 513 extends from the upper right portion of the electrode E1 to the negative side in the Y direction. The gate electrode 511 is a portion that extends from the connecting portion 513 to the negative side in the X direction with a gap from the electrode E1, and extends substantially across the entire width (dimension in the X direction) of the first element portion 311 from the first element portion 311. overlap. As shown in FIG. 4, in the first element portion 311, a region facing the gate electrode 511 across the gate insulating layer L0 is a channel region 311c of the driving transistor Tdr. Further, a region of the first element portion 311 closer to the electrode E2 than the channel region 311c (that is, a region located in the gap between the gate electrode 511 and the electrode E1 as viewed from the direction perpendicular to the substrate 10 as shown in FIG. 6). It is a source region 311s, and the opposite region is a drain region 311d.

  The first data line part 131 is a part constituting the data line 13 of FIG. The first data line portion 131 is disposed in a negative region in the X direction when viewed from the intermediate conductor 51, and extends in the Y direction at a gap between the selection line 11 and the initialization line 12.

  FIG. 8 is a plan view showing a state where the four unit elements P in the stage of FIG. 6 are arranged in the X direction and the Y direction. As shown in FIGS. 6 and 8, in each unit element P, the second element portion 312 (initializing transistor Tint) formed on the negative edge in the Y direction is located on the positive side in the X direction, and is in the Y direction. The element part 411 (selection transistor Tsl) formed on the peripheral edge on the positive side is located on the negative side in the X direction.

  Now, a configuration is assumed in which the second element unit 312 and the element unit 411 are arranged on the same side in the X direction in each unit element P. In this configuration, in order to ensure the separation between the second element portion 312 and the element portion 411, a gap region (a region corresponding to the region B in FIG. 8) between the unit elements P adjacent in the Y direction is sufficiently provided. Since it is necessary to ensure, there is a problem that high definition of the unit element P is hindered. On the other hand, in the present embodiment, since the positions of the second element portion 312 and the element portion 411 in the X direction are different, the second element portion 312 and the element portion 411 are in the region B as shown in FIG. Are alternately arranged along the X direction. According to this configuration, even when the region B is narrowed, the second element portion 312 and the element portion 411 are surely separated from each other, so that there is an advantage that the high definition of the unit element P is easy.

  As shown in FIG. 4, the surface of the gate insulating layer L0 on which the intermediate conductor 51 and the first data line portion 131 are formed is covered with the first insulating layer L1 over the entire area. As shown in FIGS. 4 and 7, the connecting portion 61, the element conducting portion 71, the power supply line 15, and the second data line portion 132 are formed from the same layer on the surface of the first insulating layer L1 by a conductive material. Is done.

  When viewed from the direction perpendicular to the substrate 10 as shown in FIG. 7, the connecting portion 61 overlaps the Y-direction positive end of the portion 312 c of the second element portion 312 and the intermediate conductor 51 (gate electrode 511). . The connecting portion 61 is electrically connected to the portion 312c through a contact hole Ha1 that passes through the first insulating layer L1 and the gate insulating layer L0, and is intermediately conductive through a contact hole Ha2 that passes through the first insulating layer L1. Conducted to the body 51. That is, the gate electrode 511 of the drive transistor Tdr (the electrode E1 of the capacitive element C1) and the initialization transistor Tint are electrically connected via the connection portion 61. Note that the contact hole in this specification is a portion for electrically connecting an element located on one side of the insulating layer and an element located on the other side of the insulating layer, more specifically. A portion (hole or hole) that penetrates the insulating layer in the thickness direction. The planar shape of the contact hole is arbitrary.

  The element conduction portion 71 is a portion that is interposed between the driving transistor Tdr and the light emitting element E and electrically connects them. When viewed from the direction perpendicular to the substrate 10, the element C1 sandwiches the driving transistor Tdr. Is disposed in a region opposite to (i.e., a region on the negative side in the Y direction with respect to the drive transistor Tdr). The element conduction portion 71 of this embodiment includes a portion 711 that overlaps the drain region 311d of the first element portion 311 and a portion that is located on the opposite side of the portion 711 across the initialization line 12 when viewed from the direction perpendicular to the substrate 10. 712 is a continuous shape.

  A plurality of contact holes Ha3 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region overlapping the drain region 311d in the first insulating layer L1 when viewed from the direction perpendicular to the substrate 10. These contact holes Ha3 are arranged in the X direction in which the gate electrode 511 extends (that is, the channel width direction of the driving transistor Tdr). The portion 711 of the element conducting portion 71 is conducted to the drain region 311d through each contact hole Ha3.

  Next, FIG. 9 is a plan view showing a state in which the four unit elements P in the stage of FIG. 8 are arranged over the X direction and the Y direction. As shown in FIGS. 7 and 9, the power supply line 15 is a strip-like wiring extending in the X direction along the arrangement of the plurality of unit elements P. The power supply line 15 overlaps with both the capacitive element C1 of each unit element P and the source region 311s of the drive transistor Tdr when viewed from the direction perpendicular to the substrate 10. As shown in FIG. 7, a plurality of contact holes Ha4 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region overlapping the source region 311s in the first insulating layer L1. These contact holes Ha4 are arranged in the X direction in which the gate electrode 511 extends. The power supply line 15 is electrically connected to the source region 311s of the drive transistor Tdr through each contact hole Ha4.

  The power supply line 15 of the present embodiment overlaps with the selection transistor Tsl (element unit 411), the selection line 11, the initialization transistor Tint (second element unit 312), and the initialization line 12 when viewed from the direction perpendicular to the substrate 10. The shape and dimensions are selected so that there is no such thing. In other words, as shown in FIG. 9, the power supply line 15 is X in the region of the gap between the arrangement of the selection transistors Tsl along the selection line 11 and the arrangement of the initialization transistors Tint along the initialization line 12. Extend in the direction.

  The second data line portion 132 is a portion constituting the data line 13 in cooperation with the first data line portion 131, and extends in the Y direction at the gap between the power supply lines 15 as shown in FIGS. Exists. As shown in FIG. 7, the positive end (lower) end 132 a in the Y direction of the second data line portion 132 is the negative end (upper) end 131 a (in the Y direction of the first data line portion 131). (See FIG. 6). The end portion 132a and the end portion 131a are electrically connected to each other through a contact hole Ha5 that penetrates the first insulating layer L1. Similarly, the negative end 132b in the Y direction in the second data line portion 132 and the positive end 131b in the Y direction in the first data line portion 131 (see FIG. 6) are connected via the contact hole Ha6. Conducts with each other. As described above, the first data line portions 131 and the second data line portions 132 that are alternately arranged along the Y direction are electrically connected to each other, whereby the data lines 13 extending linearly in the Y direction. Is configured.

  As shown in FIG. 7, a branch portion 134 is connected to the second data line portion 132. The branching portion 134 is a portion located on the opposite side of the capacitive element C1 across the selection line 11, extends in the X direction, and overlaps the element portion 411 of the semiconductor layer 41. The branch portion 134 is electrically connected to the element portion 411 through a contact hole Ha7 that penetrates the first insulating layer L1 and the gate insulating layer L0. That is, the selection transistor Tsl and the data line 13 are electrically connected via the branch part 134.

  As shown in FIGS. 7 and 9, the capacitive element C1 of each unit element P is adjacent to the data line 13 corresponding to another unit element P adjacent to the positive side in the X direction. FIG. 10 is an enlarged sectional view showing the vicinity of an arbitrary unit element P1 and another unit element P2 adjacent to the positive side in the X direction. In the drawing, an intermediate conductor 51 of the unit element P1 (here, particularly an electrode E1 of the capacitive element C1) and a first data line portion 131 of the data line 13 corresponding to the unit element P2 are shown.

  Since the intermediate conductor 51 and the first data line portion 131 are formed from the same layer and are close to each other, the electrode E1 of the intermediate conductor 51 and the first data line portion 131 are capacitive as shown in FIG. And a capacitance (parasitic capacitance) Ca accompanies them. Therefore, the potential Vg of the electrode E1 of the unit element P1 (and also the gate electrode 511 of the drive transistor Tdr) is originally a variation amount of the potential of the data line 13 corresponding to the unit element P1 (according to the gradation of the unit element P1). In fact, it is also influenced by the amount of fluctuation in the potential of the first data line portion 131 corresponding to the unit element P2 (voltage corresponding to the gradation of the unit element P2). . That is, the gate potential Vg in the drive transistor Tdr of each unit element P cannot be set accurately, and as a result, an error may occur in the light amount of the light emitting element E.

  As shown in FIG. 7, the first data line portion 131 and the power supply line 15 face each other with the first insulating layer L1 interposed therebetween. Therefore, a capacitor is formed between the first data line portion 131 and the power supply line 15. In the present embodiment, as shown in FIG. 10, the capacitance value c2 of the capacitor Cb formed between the first data line portion 131 of the unit element P2 and the power supply line 15 is the same as the first data line portion 131. It is larger than the capacitance value c1 of the capacitance Ca associated with the intermediate conductor 51 (electrode E1) of the unit element P1. According to this configuration, the capacitance Cb reduces the influence exerted on the intermediate conductor 51 (electrode E1) of the unit element P1 by the fluctuation of the potential of the first data line portion 131 of the unit element P2. Therefore, the gate potential Vg of the drive transistor Tdr in each unit element P and the light amount of the light emitting element E according to the gate potential Vg can be set to the desired values with high accuracy.

  In the present embodiment, the distance (the film thickness of the first insulating layer L1) between the first data line portion 131 and the power supply line 15 and the middle of the unit element P1 so that the above condition (c2> c1) is satisfied. The distance between the conductor 51 and the first data line portion 131 of the unit element P2 is selected. More specifically, the distance between the first data line portion 131 of the unit element P2 and the power supply line 15 (film thickness of the first insulating layer L1) is the first data of the intermediate conductor 51 of the unit element P1 and the unit element P2. It is smaller than the interval with the line part 131. In addition, the first data line portion 131 and the power supply line 15 of the unit element P2 are opposed to each other with the first insulating layer L1 interposed therebetween (that is, when viewed from the direction perpendicular to the substrate 10) Is an area where the first data line portion 131 and the intermediate conductor 51 of the unit element P1 face each other (that is, the first end of the side end surfaces (side surfaces perpendicular to the substrate 10) of the intermediate conductor 51). Larger than the area facing the side end face of the data line portion 131). As described above, the capacitance value c2 can be made larger than the capacitance value c1 by selecting the dimensions and intervals of the respective parts.

  However, in order to accurately set the gate potential Vg of the drive transistor Tdr according to the data potential Vdata of the data line 13, the capacitance value c2 of the capacitance Cb in the arbitrary unit element P2 is set to the capacitance element C1 of the unit element P2. Is preferably smaller than the capacitance value C (the combined capacitance of the capacitive element C1 and the parasitic capacitance Cs when the capacitance Cs is parasitic on the gate electrode 511). In order to satisfy this condition, for example, the gap between the first data line portion 131 and the power supply line 15 is selected to be larger than the gap between the electrode E1 and the electrode E2 in the capacitive element C1. More specifically, the thickness of the first insulating layer L1 (that is, the dielectric of the capacitor Cb) interposed between the first data line portion 131 and the power supply line 15 is interposed between the electrode E1 and the electrode E2. The dimension is selected to be larger than the film thickness of the gate insulating layer L0 (the dielectric of the capacitive element C1). In addition, the capacitance Cb is also increased by the configuration in which the area where the electrode E1 and the electrode E2 face each other (that is, the area of the capacitive element C1) is larger than the area where the first data line portion 131 and the power supply line 15 face each other. The capacitance value c2 is smaller than the capacitance value C of the capacitive element C1.

  As shown in FIG. 4, the surface of the first insulating layer L1 on which the second data line portion 132 and the power supply line 15 are formed is covered with the second insulating layer L2 over the entire area. As shown in FIGS. 3 and 4, the first electrode 21 is formed on the surface of the second insulating layer L2. The first electrode 21 is a substantially rectangular electrode that overlaps the element conducting portion 71, the drive transistor Tdr, and the capacitive element C 1 when viewed from the direction perpendicular to the substrate 10. The first electrode 21 of the present embodiment is formed of a light-reflective conductive material such as a metal such as aluminum or silver or an alloy containing these metals as a main component. The first electrode 21 is electrically connected to the portion 712 of the element conductive portion 71 through a contact hole Ha8 that penetrates the second insulating layer L2. In other words, the drain region 311 d of the drive transistor Tdr and the first electrode 21 of the light emitting element E are electrically connected via the element conducting portion 71.

  On the surface of the second insulating layer L2 on which the first electrode 21 is formed, partition walls 25 having a shape (lattice shape) that partitions the boundaries of the unit elements P are formed. The partition wall 25 plays a role of electrically insulating the adjacent first electrodes 21 (that is, a role enabling individual control of the potential of the first electrode 21). The light emitting layer 23 of each light emitting element E is formed in a recess surrounded by the inner peripheral surface of the partition wall 25 and having the first electrode 21 as a bottom surface. Various functional layers (a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, a hole block layer, and an electron block layer) for promoting or improving the light emission by the light emitting layer 23 are the light emitting layers. It is good also as a structure laminated | stacked on 23. FIG.

  As shown in FIG. 4, the second electrode 22 is an electrode that is formed continuously over the plurality of unit elements P and covers the light emitting layer 23 and the partition walls 25. Therefore, the partition wall 25 electrically insulates the first electrode 21 and the second electrode 22 in the gap region between the light emitting elements E. In other words, the partition wall 25 defines a region where current flows between the first electrode 21 and the second electrode 22 (that is, a region that actually emits light). The second electrode 22 is formed of a light transmissive conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Therefore, the light emitted from the light emitting layer 23 to the opposite side of the substrate 10 and the light emitted from the light emitting layer 23 toward the substrate 10 and reflected by the surface of the first electrode 21 are transmitted through the second electrode 22 and emitted. . That is, the light emitting device D of this embodiment is a top emission type.

  The second electrode 22 is covered with a sealing material (not shown) over the entire area. The sealing material includes a first layer that protects the second electrode 22, a second layer that flattens the step on the surface of the second electrode 22, and impurities (for example, moisture) to the second electrode 22 and the light emitting layer 23. A third layer (barrier layer) for preventing the intrusion of the first electrode 22 is laminated in this order from the second electrode 22 side.

  As described above, in the present embodiment, the element conduction portion 71 is disposed in a region opposite to the capacitive element C1 with the drive transistor Tdr interposed therebetween. According to this configuration, there is an effect that the capacitance value required for the capacitive element C1 can be reduced. This effect will be described in detail as follows.

  Now, a configuration (hereinafter referred to as “configuration 1”) in which the element conduction portion 71 is disposed in the gap between the drive transistor Tdr and the capacitive element C1 when viewed from the direction perpendicular to the substrate 10 is assumed. In Configuration 1, the electrode E1 of the capacitive element C1 and the element conduction portion 71 are close to each other with the first insulating layer L1 interposed therebetween. Therefore, as shown by a broken line in FIG. 11, a capacitance Cx is attached between the electrode E1 and the element conduction portion 71 (first electrode 21).

  In the writing period, the potential of the electrode E1 changes by “ΔV · C / (C + Cs)”. The capacitance value Cs in the configuration 1 increases by the capacitance Cx as compared with the case where the electrode E1 and the element conduction portion 71 are not capacitively coupled, and therefore the drive transistor Tdr of the drive transistor Tdr with respect to the fluctuation amount ΔV of the potential of the data line 13. A variation amount of the gate potential Vg is limited. Therefore, in order to vary the gate potential Vg over a wide range according to the variation amount ΔV (that is, to ensure a sufficient light amount range of the light emitting element E), the gate insulating layer L0 can be reduced in film thickness or the electrode E1. It is necessary to ensure a sufficient capacitance value C for the capacitive element C1 by measures such as increasing the area of the electrode E2. Since there is a limit to reducing the thickness of the gate insulating layer L0, in the configuration 1, it is necessary to increase the area of the electrode E1 and the electrode E2 after all. However, when the area of the capacitive element C1 is increased, there is a problem that the high definition of the unit element P is limited.

  If the electrode E1 and the element conducting portion 71 are separated from each other by forming the first insulating layer L1 to a sufficient thickness, the capacitance Cx can be reduced even in the configuration 1. However, when the first insulating layer L1 is formed thick, there is a problem that film formation defects such as cracks are likely to occur, and contact hole defects (for example, the contact hole portion of the first insulating layer L1 is not completely removed). There is a limit to the reduction of the capacitance Cx by this method because there may be a problem that each element is not completely conducted due to a failure.

  On the other hand, in the present embodiment, since the element conduction portion 71 is disposed in a region opposite to the capacitance element C1 across the drive transistor Tdr, the capacitance Cx associated with the electrode E1 and the element conduction portion 71 is Compared with the configuration 1, it is sufficiently reduced. Therefore, the gate potential Vg of the gate electrode 511 of the drive transistor Tdr (and the light amount of the light emitting element E) can be changed over a wide range without increasing the area of the capacitive element C1 as much as the configuration 1.

  In the present embodiment, both the element conduction portion 71 and the connection portion 61 formed from the same layer as the power supply line 15 are connected to the negative side of the drive transistor Tdr in the Y direction as viewed from the direction perpendicular to the substrate 10 (that is, the power supply line). One side of the line 15 in the width direction). According to this configuration, a sufficient space for forming the power supply line 15 is provided on the positive side in the Y direction (the other side in the width direction of the power supply line 15) of the surface of the first insulating layer L1 with respect to the drive transistor Tdr. It is possible to ensure. Therefore, there is an effect that the power line 15 can be formed wide to reduce its resistance. In particular, in the present embodiment, since the power supply line 15 is formed so as to overlap with the capacitive element C1, for example, the resistance of the power supply line 15 is compared with a configuration in which the power supply line 15 overlaps only the source region 31s of the drive transistor Tdr. Is greatly reduced. Since the voltage drop in the surface of the power supply line 15 is suppressed by this low resistance, the variation in the power supply potential Vdd supplied to each unit element P and the variation in the amount of light of each light emitting element E due to this are reduced. it can.

  For example, in a configuration in which the element conduction portion 71 and the connection portion 61 are arranged in the gap between the drive transistor Tdr and the capacitive element C1, it is necessary to form the power supply line 15 in a shape that avoids the element conduction portion 71 and the connection portion 61. is there. However, if the shape of the power supply line 15 is complicated as described above, there is a problem that the power supply line 15 is likely to be disconnected or damaged due to manufacturing technology. On the other hand, according to the present embodiment, since the space of the power supply line 15 is secured on the opposite side of the element conduction portion 71 and the connection portion 61 with the drive transistor Tr interposed therebetween, as illustrated in FIG. 15 can be a simple strip shape. As a result, disconnection or breakage of the power supply line 15 is suppressed, and according to this embodiment, the yield of the light emitting device D can be improved.

  By the way, from the standpoint of reducing the resistance of the power supply line 15 alone, the power supply line 15 overlaps not only the drive transistor Tdr and the capacitive element C1, but also the selection transistor Tsl and the initialization transistor Tint (hereinafter referred to as “configuration 2”). It is good. However, in the configuration 2, the selection transistor Tsl and the selection line 11 are capacitively coupled to the power supply line 15 (that is, a capacitance is parasitic between both), and the waveform of the selection signal Sa is dull due to this capacitance. There is a problem that it is likely to occur. Similarly, the capacitance accompanying the initialization transistor Tint or the initialization line 12 and the power supply line 15 can also cause the waveform of the initialization signal Sb to become dull. Therefore, in the configuration 2, there is a problem that switching of the selection transistor Tsl and the initialization transistor Tint is delayed.

  On the other hand, in the present embodiment, the power supply line 15 does not overlap the selection transistor Tsl, the selection line 11, and the initialization transistor Tint or the initialization line 12 when viewed from the direction perpendicular to the substrate 10. And the parasitic capacitance between the power supply line 15 and the configuration 2 are reduced. Therefore, according to the present embodiment, it is possible to operate the selection transistor Tsl and the initialization transistor Tint at high speed while suppressing the dullness of the waveform of the selection signal Sa and the initialization signal Sb.

<B-2: Second Embodiment>
Next, a specific configuration of the unit element P in the second embodiment of the present invention will be described. FIG. 12 is a plan view showing a configuration of the unit element P in the present embodiment, and FIGS. 13 to 15 are plan views showing states on the surface of the substrate 10 at each stage where the unit element P is formed. . In the following embodiments, elements common to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  As shown in FIG. 13, the semiconductor layer 32, the semiconductor layer 42, and the semiconductor layer 45 are formed from the same layer on the surface of the substrate 10 by a semiconductor material. The semiconductor layer 32 is a substantially rectangular portion constituting the drive transistor Tdr. The semiconductor layer 42 is a portion formed on the positive side in the Y direction when viewed from the semiconductor layer 32, and includes a substantially rectangular electrode E2 and an element portion 421 extending in the X direction from the lower left portion of the electrode E2. The element portion 421 is a portion that functions as a semiconductor layer of the selection transistor Tsl. The semiconductor layer 45 is a part constituting the initialization transistor Tint, and extends in the X direction in a region opposite to the semiconductor layer 32 with the semiconductor layer 42 interposed therebetween.

  The surface of the substrate 10 on which the above portions are formed is covered with the gate insulating layer L0. As shown in FIG. 14, on the surface of the gate insulating layer L0, the first data line portion 131, the selection line 11, the initialization line 12, the intermediate conductor 52, and the first relay wiring portion 171 are formed from the same layer. Is done. The first data line part 131 is a part constituting the data line 13 as in the first embodiment, and extends in the Y direction in the positive region in the X direction when viewed from the intermediate conductor 52.

  The initialization line 12 includes a first gate electrode 121 and a second gate electrode 122 that branch from the portion extending in the X direction to the negative side in the Y direction and overlap the semiconductor layer 45. A portion of the semiconductor layer 45 that overlaps each of the first gate electrode 121 and the second gate electrode 122 is a channel region of the initialization transistor Tint. Similarly, the selection line 11 includes a first gate electrode 111 and a second gate electrode 112 that branch from the portion extending in the X direction to the negative side in the Y direction and overlap the element portion 421 of the semiconductor layer 42. The first gate electrode 111 and the second gate electrode 112 are adjacent to each other in the X direction with a space therebetween. A portion of the element portion 421 that overlaps each of the first gate electrode 111 and the second gate electrode 112 with the gate insulating layer L0 interposed therebetween is a channel region of the selection transistor Tsl. As described above, the selection transistor Tsl and the initialization transistor Tint of this embodiment are thin film transistors having a dual gate structure.

  The intermediate conductor 52 includes an electrode E1 that constitutes the capacitive element C1 facing the electrode E2, a gate electrode 521 that is continuous from the electrode E1 on the negative side in the Y direction, and the Y direction from approximately the center of the electrode E1 in the X direction. And a connecting portion 523 that protrudes to the positive side. The gate electrode 521 extends in the Y direction so as to overlap the semiconductor layer 32 over the entire dimension along the Y direction of the semiconductor layer 32. As shown in FIG. 14, in the semiconductor layer 32, a region facing the gate electrode 521 across the gate insulating layer L0 is a channel region 32c of the driving transistor Tdr. Further, the negative region in the X direction across the channel region 32c is the drain region 32d, and the opposite region is the source region 32s.

  The first relay wiring portion 171 is a portion constituting a wiring (hereinafter referred to as “relay wiring”) for electrically connecting the initialization transistor Tint and the drain region 32d of the driving transistor Tdr. As a result, it extends in the Y direction in the negative region in the X direction. That is, the intermediate conductor 52 in the present embodiment is disposed in the gap between the first data line part 131 and the first relay wiring part 171.

  The surface of the gate insulating layer L0 on which the above portions are formed is covered with the first insulating layer L1 over the entire area. As shown in FIGS. 12 and 15, the second data line part 132, the connection part 62, the second relay wiring part 172, the element conduction part 72, and the power supply line 15 are formed on the surface of the first insulating layer L1. Is done.

  Similar to the first embodiment, the second data line part 132 is a wiring that forms the data line 13 in cooperation with the first data line part 131. That is, the second data line portion 132 extends in the Y direction from the end portion 132a that conducts to the upper end portion 131a (see FIG. 14) of the first data line portion 131 through the contact hole Hb1, and reaches the end portion 132b. . The end portion 132b is electrically connected to the lower end portion 131b (see FIG. 14) of the first data line portion 131 through the contact hole Hb2. In addition, the second data line portion 132 of this embodiment is electrically connected to the end portion of the element portion 421 through a contact hole Hb3 penetrating the first insulating layer L1 and the gate insulating layer L0. That is, the data line 13 and the selection transistor Tsl are electrically connected via the contact hole Hb3.

  As shown in FIGS. 14 and 15, the connecting portion 62 extends in the Y direction so as to overlap the connecting portion 523 of the intermediate conductor 52 and the positive end portion 451 in the X direction of the semiconductor layer 45. The connecting portion 62 is electrically connected to the connecting portion 523 (electrode E1 and gate electrode 521) through a contact hole Hb4 that passes through the first insulating layer L1, and also passes through the first insulating layer L1 and the gate insulating layer L0. It conducts to the end 451 of the semiconductor layer 45 through the contact hole Hb5. That is, the electrode E1 of the capacitive element C1 (and the gate electrode 521 of the driving transistor Tdr) and the initialization transistor Tint are electrically connected via the connection portion 62.

  As seen from the direction perpendicular to the substrate 10 as shown in FIG. 15, the connecting portion 62 is located in the region of the gap between the first gate electrode 111 and the second gate electrode 112 of the selection transistor Tsl. Therefore, the connection part 62 does not overlap the first gate electrode 111 and the second gate electrode 112. Here, for example, in the configuration in which the first gate electrode 111 (or the second gate electrode 112) and the connection portion 62 overlap, both are capacitively coupled. Accordingly, the potential of the first gate electrode 111 also changes in accordance with the fluctuation of the potential of the connection portion 62 (that is, the potential of the electrode E1 and the gate electrode 511 of the drive transistor Tdr), and as a result, the waveform of the initialization signal Sb becomes dull. There is a case. The dullness of the waveform of the initialization signal Sb causes a delay in the operation of the initialization transistor Tint.

  In contrast, in the present embodiment, since the connection portion 62 is formed so as not to overlap the first gate electrode 111 and the second gate electrode 112, the connection portion 62 and the first gate electrode 111 and the second gate are formed. Capacitive coupling with the electrode 112 is suppressed. Therefore, the influence of the fluctuation of the potential of the connecting portion 62 on the initialization transistor Tint is reduced, and as a result, the initialization transistor Tint can be operated at high speed.

  Further, as described above, according to the configuration in which the initialization transistor Tint and the electrode E1 of the capacitive element C1 are conducted through the connection portion 62, the channel length of the selection transistor Tsl and the initialization transistor Tint can be sufficiently secured. Compared with a configuration in which the channel length is limited, current leakage in the selection transistor Tsl and the initialization transistor Tint can be suppressed. Since the selection transistor Tsl and the initialization transistor Tint are connected to the gate electrode 521 of the driving transistor Tdr, variation in the potential of the gate electrode 521 during the driving period is suppressed by reducing current leakage in each. Therefore, according to this embodiment, it is possible to maintain the light quantity of the light emitting element E at a predetermined value with high accuracy.

  15 is interposed between the drain electrode of the drive transistor Tdr and the first electrode 21 of the light emitting element E, and electrically connects both, similarly to the element conduction unit 71 of the first embodiment. Part. The element conduction portion 72 has a shape (substantially L-shaped) in which a portion 721 extending in the Y direction and a portion 722 located on the opposite side of the capacitive element C1 across the drive transistor Tdr are continuous. The portion 721 overlaps the end 171 a (see FIG. 14) of the first relay wiring portion 171 and the drain region 32 d of the semiconductor layer 32. The portion 721 is electrically connected to the upper end portion 171a through a contact hole Hb6 that penetrates the first insulating layer L1.

  A plurality (two in this case) of contact holes Hb7 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region of the first insulating layer L1 overlapping the drain region 32d. These contact holes Hb7 are arranged in the Y direction (that is, the channel width direction of the drive transistor Tdr) in which the gate electrode 521 extends. The portion 721 of the element conduction portion 72 is conducted to the drain region 32d through each contact hole Hb7.

  As shown in FIGS. 14 and 15, the second relay wiring portion 172 is a wiring extending in the Y direction so as to overlap the negative end portion 452 in the X direction and the first relay wiring portion 171 in the semiconductor layer 45. It is. The second relay wiring portion 172 is electrically connected to the end 452 through a contact hole Hb8 that passes through the first insulating layer L1 and the gate insulating layer L0, and via a contact hole Hb9 that passes through the first insulating layer L1. To the lower end portion 171b of the first relay wiring portion 171. As described above, the initialization transistor Tint and the drain region 32d (and the element conduction portion 72) of the drive transistor Tdr are connected to the relay wiring 17 composed of the first relay wiring portion 171 and the second relay wiring portion 172. Electrically connected.

  FIG. 16 is a plan view showing a state in which the four unit elements P in the stage of FIG. 15 are arranged in the X direction and the Y direction. As shown in FIGS. 15 and 16, the power supply line 15 in the present embodiment includes a first portion 151 extending in the X direction over the plurality of unit elements P and a first portion 151 extending in the Y direction over the plurality of unit elements P. This is a wiring having a shape (lattice shape) intersecting with the two portions 152.

  As shown in FIG. 15, in the region of the first insulating layer L1 that overlaps the source region 32s of the semiconductor layer 32, a plurality of (here, two) contacts penetrating the first insulating layer L1 and the gate insulating layer L0. Hole Hb10 is formed. These contact holes Hb10 are arranged in the Y direction in which the gate electrode 521 extends. The power supply line 15 (second portion 152) is electrically connected to the source region 32s through each contact hole Hb10.

  The first portion 151 extends in the X direction so as to pass through the gap region between the second data line portions 132 and the gap region between the second relay wiring portion 172 and the element conduction portion 72 (portion 721). . Therefore, when viewed from the direction perpendicular to the substrate 10 as shown in FIGS. 15 and 16, the first portion 151 overlaps the first data line portion 131, the first relay wiring portion 171 and the capacitive element C1. The second portion 152 passes through the gap region between the element conduction portion 72 (portion 722) and the second data line portion 132 and the gap region between the connection portion 62 and the second data line portion 132. Extend in the direction. As shown in FIGS. 15 and 16, the power supply line 15 does not overlap the selection transistor Tsl or the initialization transistor Tint.

  The surface of the first insulating layer L1 on which the above elements are formed is covered with the second insulating layer L2 over the entire area. As shown in FIG. 12, the light emitting element E and the partition wall 25 that partitions the gap are formed on the surface of the second insulating layer L2. The portion 722 of the element conducting portion 72 is conducted to the first electrode 21 through the contact hole Hb11 penetrating the second insulating layer L2 as in the first embodiment. As shown in FIG. 12, the specific configurations of the light emitting element E and the partition 25 are the same as those in the first embodiment.

  As described above, in the present embodiment, the element conduction portion 72 is disposed on the opposite side of the capacitive element C1 across the drive transistor Tdr. Therefore, as in the first embodiment, the parasitic capacitance (capacitance Cx in FIG. 11) in the electrode E1 and the element conducting portion 72 is reduced, and as a result, the capacitance value of the capacitive element C1 can be reduced. Further, since the power supply line 15 is formed so as not to overlap with the selection transistor Tsl and the initialization transistor Tint, the selection transistor Tsl and the initialization transistor Tint can be moved at high speed at a predetermined timing as in the first embodiment. It can be operated.

  Further, in the present embodiment, the element conduction portion 72, the connection portion 62, and the second relay wiring portion 172 are formed from the same layer as the power supply line 15, and the negative side in the X direction (that is, the power supply) The element conduction portion 72 is disposed on one side in the width direction of the line 15 and the connection portion 62 and the second relay wiring portion 172 are disposed on the opposite side (the other side in the width direction of the power supply line 15). . Therefore, a sufficient space for forming the first portion 151 extending in the X direction of the power supply line 15 in the gap between the element conduction portion 72 and the connection portion 62 (second relay wiring portion 172) is ensured. Is possible. Further, the space overlapping the capacitive element C 1 when viewed from the direction perpendicular to the substrate 10 can also be used for forming the power supply line 15. Therefore, as in the first embodiment, the power line 15 (first portion 151) can be formed wide to reduce its resistance.

  In addition, in the present embodiment, since the first portions 151 are connected by the second portions 152 extending in the Y direction, the power source line 15 has a power source as compared with the case where the power source line 15 is configured only by the first portion 151. The resistance of the line 15 can be further reduced. In addition, since the shape of the first portion 151 of the power supply line 15 is a simple band shape, the power supply line 15 is provided so as to avoid elements (element conduction part 72 and connection part 62) formed from the same layer as the power supply line 15. Compared to a configuration formed in a complicated shape, disconnection or breakage of the power supply line 15 can be suppressed.

  Further, in the present embodiment, the data line 13 extends along the peripheral edge on the positive side in the X direction in each unit element P, and the relay wiring 17 extends along the peripheral edge on the negative side in the X direction. In this configuration, for example, as shown in FIG. 16, when attention is paid to an arbitrary unit element P1 and another unit element P2 adjacent to the negative side in the X direction, the capacitive element C1 and the unit element P2 of the unit element P1 Between the corresponding data line 13, the relay wiring 17 of the unit element P1 is interposed. Therefore, compared with the configuration of the first embodiment in which the capacitive element C1 of one unit element P and the data line 13 of the unit element P adjacent thereto are close to each other, the capacitive element C1 and the unit element P2 of the unit element P1 The capacitance formed between the data lines 13 is reduced. According to this configuration, since the influence of the fluctuation of the potential of the data line 13 of the unit element P2 on the capacitive element C1 of the unit element P1 is reduced, the gate potential Vg of the drive transistor Tdr in each unit element P and this gate potential The light quantity of the light emitting element E according to Vg can be set to a desired value with high accuracy.

<Modification of Second Embodiment>
Next, a modification of the second embodiment described above will be described. FIG. 17 is a plan view showing a stage (stage of FIG. 14) in which the first insulating layer L1 is formed in the present modification. In the second embodiment, the configuration in which the gate electrode 521 of the drive transistor Tdr extends in the Y direction is exemplified. On the other hand, in this modification, the gate electrode 521 extends in the X direction as shown in FIG. In addition, the same code | symbol is attached | subjected about the element similar to 2nd Embodiment among this modification, and the description is abbreviate | omitted suitably.

  As shown in FIG. 17, the intermediate conductor 52 of the present embodiment includes a connecting portion 525 extending from the upper left part of the electrode E1 to the negative side in the Y direction, and extending from the connecting portion 525 in the X direction to the semiconductor. A gate electrode 521 that overlaps the layer 32 is included. The gate electrode 521 extends in the X direction over the entire dimension of the semiconductor layer 32 in the X direction. A region of the semiconductor layer 32 that faces the gate electrode 521 across the gate insulating layer L0 is a channel region 32c of the drive transistor Tdr. A region on the electrode E1 side with the channel region 32c interposed therebetween is a source region 32s, and a region on the opposite side is a drain region 32d.

  18 is a plan view showing a stage (stage of FIG. 15) in which the power supply line 15 and the element conduction portion 72 are further formed from the stage of FIG. As shown in FIG. 18, the element conducting portion 72 is formed in a substantially rectangular shape in a region opposite to the capacitive element C1 across the drive transistor Tdr. As shown in FIGS. 17 and 18, the element conduction portion 72 is connected to the drain region 32d via a plurality of contact holes Hb7 arranged in the X direction (that is, the channel length direction of the drive transistor Tdr) in which the gate electrode 511 extends. Conducted to. The power supply line 15 is electrically connected to the source region 32s through a plurality of contact holes Hb10 arranged in the X direction along the gate electrode 511.

  As described above, since the gate electrode 521 of the drive transistor Tdr extends in the X direction, the drain region 32d is long in the X direction in a region opposite to the capacitive element C1 across the gate electrode 521. It is formed in a scale. In this configuration, it is not necessary to form a portion (the portion 721 in the first embodiment) extending in the Y direction along the drive transistor Tdr in the element conduction portion 72. Therefore, according to the present modification, as can be understood from the comparison between FIG. 18 and FIG. 15, the first portion 151 extending in the direction of the gate electrode 521 of the power supply line 15 is made more than that of the second embodiment. There is an advantage that it can be formed wide.

  Further, in this modification, each contact hole Hb7, contact hole Hb6 (a portion where the relay wiring 17 and the element conducting portion 72 are conducted), and contact hole Hb1 (the first data line portion 131 and the second data line portion 132, Are arranged in a straight line along the X direction. Therefore, the line width of the first portion 151 extending in a straight line (strip shape) along the X direction is sufficiently large as compared with the configuration in which the positions of the contact holes (Hb7, Hb6, Hb1) in the Y direction are different. Can be secured.

  By the way, in the second embodiment, the gate electrode 521 extends in a direction orthogonal to the first portion 151 of the power supply line 15. Therefore, the line width of the first portion 151 is reduced as the length of the gate electrode 521 (more precisely, the length of the portion 721 of the element conducting portion 72) is increased. On the other hand, in the present modification, the gate electrode 521 extends in a direction parallel to the first portion 151, so that the length of the gate electrode 521 is increased without reducing the line width of the first portion 151. Can do. Since the length of the gate electrode 521 corresponds to the channel width of the drive transistor Tdr, according to the present modification, the channel width of the drive transistor Tdr can be increased while maintaining the line width of the first portion 151. The driving transistor Tdr having such a large channel width has an advantage that a sufficient amount of current can be secured from the power supply line 15 to the light emitting element E via the driving transistor Tdr.

<B-3: Third Embodiment>
Next, a specific configuration of the unit element P in the third embodiment of the present invention will be described. FIG. 19 is a plan view showing the configuration of the unit element P in the present embodiment, and FIGS. 20 to 22 are plan views showing the state on the surface of the substrate 10 at each stage where the unit element P is formed. .

  As shown in FIG. 20, on the surface of the substrate 10, a semiconductor layer 33 and a semiconductor layer 43 are formed from the same layer using a semiconductor material. The shape of the semiconductor layer 33 is the same as that of the semiconductor layer 31 of the first embodiment. The semiconductor layer 43 includes a substantially rectangular electrode E2 constituting the capacitive element C1, and an element portion 431 continuous with the electrode E2. The element portion 431 is a portion that functions as a semiconductor layer of the selection transistor Tsl. The portion 431a extends from the lower right portion of the electrode E2 to the positive side in the Y direction, and extends from the portion 431a to the positive side in the X direction. A portion 431b and a portion 431c extending from the end of the portion 431b to the negative side in the Y direction are included.

  On the surface of the gate insulating layer L0 covering the semiconductor layer 33 and the semiconductor layer 43, as shown in FIG. 21, the intermediate conductor 53, the selection line 11 and the initialization line 12 are formed from the same layer. The shapes of the intermediate conductor 53 and the initialization line 12 and the relationship with other elements are the same as those of the intermediate conductor 51 and the initialization line 12 of the first embodiment. The selection line 11 extends in the X direction so as to overlap the element portion 431 of the semiconductor layer 43 when viewed from the direction perpendicular to the substrate 10. Of each of the portion 431a and the portion 431c in the element portion 431, a portion overlapping the selection line 11 is a channel region of the selection transistor Tsl. That is, the selection transistor Tsl of this embodiment has a dual gate structure.

  On the surface of the first insulating layer L 1 covering the intermediate conductor 53, the selection line 11, and the initialization line 12, as shown in FIG. 22, the connection part 63, the element conduction part 73, the data line 13, and the power line 15 Are formed from the same layer. The shape of the connection part 63 and the relationship with other elements are the same as those of the connection part 61 of the first embodiment. The data line 13 is a wiring extending in the Y direction in a region on the positive side in the X direction when viewed from the driving transistor Tdr and the capacitive element C1, and the element portion 431 (part 431c) of the semiconductor layer 43 through the contact hole Hc1. Conducted to.

  The element conduction portion 73 is a substantially rectangular portion formed in a region opposite to the capacitive element C1 across the drive transistor Tdr, and the semiconductor layer 33 (drain region of the drive transistor Tdr) via the contact hole Hc2. Conducted to. As shown in FIGS. 19 and 22, the first electrode 21 of the light emitting element E is electrically connected to the element conducting portion 73 through a contact hole Hc3 penetrating the second insulating layer L2.

  FIG. 23 is a plan view showing a state where the four unit elements P in the stage of FIG. 22 are arranged in the X direction and the Y direction. As shown in FIGS. 22 and 23, the power supply line 15 of the present embodiment extends in the Y direction so as to overlap the drive transistor Tdr and the capacitive element C1 of each unit element P when viewed from the direction perpendicular to the substrate 10. . As in the first embodiment, the power supply line 15 is electrically connected to the semiconductor layer 33 (the source region of the drive transistor Tdr) through the contact hole Ha4. As shown in FIG. 22, a notch 155 is formed in the shape of the power supply line 15 so as to avoid the element conduction portion 73 at the periphery on the negative side in the X direction, and the connection portion 63 is avoided at the periphery on the positive side in the X direction. A notch 157 is formed in the shape.

  Now, as shown in FIG. 23, attention is focused on one arbitrary unit element P1 and another unit element P2 adjacent to the negative side in the X direction. In the present embodiment, as described with reference to FIG. 11 for the first embodiment, the capacitance Ca associated between the electrode E1 (intermediate conductor 53) of the unit element P1 and the data line 13 of the unit element P2. Of the data line 13 and the power supply line 15 so that the capacitance value c1 of the unit element P2 becomes smaller than the capacitance value c2 of the capacity Cb attached between the data line 13 and the power supply line 15 of the unit element P2 (c1 <c2). The distance (film thickness of the first insulating layer L1) and the distance between the intermediate conductor 53 of the unit element P1 and the data line 13 of the unit element P2 are selected. According to this configuration, similarly to the first embodiment, it is possible to reduce the influence of the fluctuation of the potential of the data line 13 of the unit element P2 on the potential of the capacitive element C1 of the unit element P1.

  In the present embodiment, since the element conducting portion 73 is disposed on the opposite side of the capacitive element C1 across the drive transistor Tdr, the capacitance between the electrode E1 and the element conducting portion 73 is the same as in the first embodiment. Coupling (parasitic capacitance Cx shown in FIG. 11) is suppressed. Therefore, it is possible to reduce the capacity (and further reduce the area) of the capacitive element C1. In the first embodiment and the second embodiment, the data line 13 is configured by connecting the first data line portion 131 and the second data line portion 132, whereas in the present embodiment, the data line 13 is It is formed from a single conductive film. Therefore, compared with the first embodiment and the second embodiment, there is an advantage that the resistance value of the data line 13 can be reduced and the disconnection can be prevented.

<C: Modification>
Various modifications are added to the above embodiment. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

<C-1: Modification 1>
The electrical configuration of the unit element P in each of the above embodiments is appropriately changed. Specific embodiments of the unit element P applied to the present invention are exemplified below.

  (1) As shown in FIG. 24, a transistor (hereinafter referred to as “light emission control transistor”) Tcnt may be interposed between the drive transistor Tdr and the light emitting element E. The light emission control transistor Tcnt is a switching element that controls the electrical connection between the drain electrode of the drive transistor Tdr and the first electrode 21 of the light emitting element E according to the light emission control signal Sc supplied to the light emission control line 14. is there. When the light emission control transistor Tcnt is turned on, a current path from the power supply line 15 to the light emitting element E is formed and light emission of the light emitting element E is permitted. When the light emission control transistor Tcnt is turned off, this path is blocked. Accordingly, the light emission of the light emitting element E is prohibited. Therefore, according to this configuration, the light emitting element E actually emits light such that the light emitting control transistor Tcnt is turned on and the light emitting element E emits light only in the driving period excluding the initialization period and the writing period. Can be accurately defined.

  In each of the first to third embodiments, the light emission control transistor Tcnt is disposed, for example, on the opposite side (that is, the negative side in the Y direction) from the capacitive element C1 across the drive transistor Tdr. According to this aspect, for example, the power supply line 15 overlaps with both the drive transistor Tdr and the capacitive element C1 as compared with a configuration in which the light emission control transistor Tcnt is disposed in the gap region between the drive transistor Tdr and the capacitive element C1. There is an advantage that it can be formed wide.

  (2) As shown in FIG. 25, a configuration may be adopted in which a capacitive element C2 is interposed between the gate electrode and the source electrode (power supply line 15) of the drive transistor Tdr. According to this configuration, there is an advantage that the gate potential Vg of the driving transistor Tdr set in the writing period can be held in the capacitive element C2 in the driving period. However, in the configuration in which the area of the gate electrode (channel area) of the drive transistor Tdr is sufficiently secured, the gate potential Vg is held by the gate capacitance of the drive transistor Tdr. Therefore, the gate potential Vg can be held in the driving period even when the capacitor C2 is not disposed as in the first to third embodiments.

  (3) The unit element P having the configuration shown in FIG. 26 is also employed. In this unit element P, the capacitive element C1 and the initialization transistor Tint (initialization line 12) in each of the above embodiments are not formed, and the electrical connection between the gate electrode of the drive transistor Tdr and the data line 13 is a selection transistor. Controlled by Tsl. A capacitive element C2 is interposed between the gate electrode and the source electrode (power supply line 15) of the drive transistor Tdr.

  In this configuration, when the selection transistor Tsl changes to the ON state, the data potential Vdata corresponding to the gradation designated for the light emitting element E is supplied from the data line 13 to the gate electrode of the driving transistor Tdr via the selection transistor Tsl. . At this time, charges corresponding to the data potential Vdata are accumulated in the capacitive element C2, and therefore the gate potential Vg of the drive transistor Tdr is maintained at the data potential Vdata even when the selection transistor Tsl is turned off. Therefore, a current corresponding to the gate potential Vg of the drive transistor Tdr (current corresponding to the data potential Vdata) is continuously supplied to the light emitting element E. By supplying this current, the light emitting element E emits light with a luminance corresponding to the data potential Vdata.

  The capacitive element C2 of FIG. 26 is disposed on the surface of the substrate 10 in the same manner as the capacitive element C1 in each of the above embodiments, for example. This form also achieves the same operations and effects as the first to third embodiments. As described above, the capacitive element connected to the gate electrode of the driving transistor Tdr may be the capacitive element C1 for setting the gate potential Vg of the driving transistor Tdr by capacitive coupling, or may be driven from the data line 13. It may be a capacitive element C2 for holding the data potential Vdata supplied to the gate electrode of the transistor Tdr.

<C-2: Modification 2>
In the above embodiment, the configuration in which the first electrode 21 is formed of a light-reflective material has been illustrated. However, the light emitted from the light emitting layer 23 toward the substrate 10 is reflected by the reflective layer separate from the first electrode 21. It is good also as a structure reflected on the opposite side. In this configuration, a reflective layer is formed on the surface of the first insulating layer L1 with a light reflective material, and the first electrode 21 is formed so as to cover the reflective layer. The first electrode 21 is formed of a light-transmitting conductive material such as ITO or IZO. In the above embodiment, the configuration in which the second electrode 22 is formed of a light-transmitting material is exemplified. However, an electrode formed by sufficiently thinning a light-blocking or light-reflecting conductive material is the second electrode 22. The emitted light from the light emitting layer 23 can be transmitted also by the configuration.

  However, the present invention is also applied to a bottom emission type light emitting device in which light emitted from the light emitting layer 23 passes through the substrate 10 and is emitted. In this configuration, for example, the second electrode 22 is formed of a light-reflective conductive material, and the first electrode 21 is formed of a light-transmissive conductive material. The light emitted from the light emitting layer 23 toward the substrate 10 and the light emitted from the light emitting layer 23 to the opposite side of the substrate 10 and reflected by the surface of the second electrode 22 are the first electrode 21 and the substrate 10. Is transmitted through.

<C-3: Modification 3>
In the first and second embodiments, the configuration in which the power supply line 15 does not overlap with either the selection transistor Tsl or the initialization transistor Tint is illustrated. However, the configuration in which the power supply line 15 overlaps with the selection transistor Tsl or the power supply line 15 is illustrated. A configuration in which is overlapped with the initialization transistor Tint is also employed.

<C-4: Modification 4>
In the second embodiment, the configuration in which the connecting portion 62 is formed in the region of the gap between the first gate electrode 111 and the second gate electrode 112 of the selection transistor Tsl is exemplified. Similarly, the second portion 152 of the power supply line 15 may be formed in the region of the gap between the first gate electrode 121 and the second gate electrode 122 of the initialization transistor Tint.

<C-5: Modification 5>
In the first embodiment, the configuration including only the portion (the “first portion” in the present invention) in which the power supply line 15 extends in the X direction is illustrated, but each of these portions is provided as in the second embodiment. The power supply line 15 may include a portion (hereinafter referred to as “second portion”) extending in the Y direction so as to be connected to each other. For example, the second portion extends in the Y direction in the gap region between the connection portion 61 and the element conduction portion 71 illustrated in FIG. 7 and the gap region between the unit elements P, and is adjacent to the Y direction. The power lines 15 (first part) are connected to each other. According to this configuration, it is possible to reduce the resistance of the power supply line 15 compared to the first embodiment.

<C-6: Modification 6>
In each of the above embodiments, the configuration in which the light emitting layer 23 is formed only in the inner region of the inner periphery of the partition wall 25 is exemplified. However, light emission is performed over the entire surface of the substrate 10 (more specifically, the entire surface of the second insulating layer L2). The layer 23 may be formed continuously. According to this configuration, for example, there is an advantage that an inexpensive film forming technique such as a spin coating method can be adopted for forming the light emitting layer 23. In addition, since the 1st electrode 21 is formed separately for every light emitting element E, even if it says that the light emitting layer 23 continues over several light emitting elements E, the light quantity of the light emitting layer 23 is controlled separately for every light emitting element E. Is done. As described above, in the configuration in which the light emitting layer 23 is continuous over the plurality of light emitting elements E, the partition walls 25 may be omitted.

  In the case where the light emitting layer 23 is formed by the ink jet method (droplet discharge method) in which the droplets of the light emitting material are discharged in the spaces partitioned by the partition walls 25, the second insulating layer L2 as in the above embodiments. The structure which has arrange | positioned the partition 25 on this surface is employ | adopted suitably. However, the method for forming the light emitting layer 23 for each light emitting element E is appropriately changed. More specifically, the light emitting layer 23 is also obtained by various patterning techniques such as a method of selectively removing a film body of a light emitting material formed over the entire area of the substrate 10 and a laser transfer (LITI: Laser-Induced Thermal Imaging) method. Is formed for each light emitting element E. In this case, the light emitting layer 23 can be formed independently for each light emitting element E without forming the partition wall 25. As described above, the partition 25 is not necessarily a necessary element in the light emitting device of the present invention.

<C-7: Modification 7>
In each of the above embodiments, the light emitting element E including the light emitting layer 23 made of an organic EL material has been exemplified, but the light emitting element in the present invention is not limited to this. For example, various light emitting elements such as a light emitting element including a light emitting layer made of an inorganic EL material and an LED (Light Emitting Diode) element can be employed. The light-emitting element in the present invention may be an element that emits light by supplying electric energy (typically supplying current), and its specific structure and material are not limited.

<D: Application example>
Next, specific modes of electronic devices using the light-emitting device according to the present invention will be described. FIG. 27 is a perspective view showing the configuration of a mobile personal computer that employs the light-emitting device D according to any one of the embodiments described above as a display device. The personal computer 2000 includes a light emitting device D as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the light emitting device D uses the light emitting layer 23 of the organic EL material for the light emitting element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 28 shows a configuration of a mobile phone to which the light emitting device D according to each embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device D as a display device. By operating the scroll button 3002, the screen displayed on the light emitting device D is scrolled.

  FIG. 29 shows a configuration of a personal digital assistant (PDA) to which the light emitting device D according to each embodiment is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device D as a display device. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device D.

  Note that electronic devices to which the light emitting device according to the present invention is applied include those shown in FIGS. 27 to 29, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators. , Word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like. Further, the use of the light emitting device according to the present invention is not limited to the display of images. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. The light emitting device of the present invention can also be used.

  D: Light emitting device, P: Unit element, E: Light emitting element, 10: Substrate, 11: Selection line, 12: Initialization line, 13 ... Data line, 15 ... Power line, 21 ... ... 1st electrode, 22 ... 2nd electrode, 23 ... Light emitting layer, 31, 32, 33, 41, 42, 43, 45 ... Semiconductor layer, 51, 52, 53 ... Intermediate conductor, 61, 62 , 63... Connection, 71, 72, 73... Element conduction portion, 511, 521... Gate electrode, Tdr... Driving transistor, Tsl ... selection transistor, Tint. , E1, E2... Electrode, L0... Gate insulating layer, L1... First insulating layer, L2.

Claims (5)

On the board
A data line extending in a first direction;
A scan line extending in a second direction intersecting the first direction;
A power line extending in the second direction;
A light-emitting element having a first electrode, a second electrode facing the first electrode, and a light-emitting layer provided between the first electrode and the second electrode;
A first transistor that electrically connects the power line and the light emitting element;
A second transistor that electrically connects the gate of the first transistor and the source or drain of the first transistor;
A connection part for electrically connecting the gate of the first transistor and the source or drain of the second transistor;
The power line is disposed between the connection portion and the scanning line in plan view ,
The light-emitting device , wherein the power supply line overlaps with a gate of the first transistor in a plan view and does not overlap with a gate of the second transistor . A capacitive element electrically connected to the first transistor and the second transistor on the substrate;
The light emitting device according to claim 1 , wherein the power supply line overlaps with the capacitor element. The second extending direction, further comprising a second control signal line gate control device signals is supplied to the transistor,
The light emitting device according to claim 1 , wherein the power supply line is disposed between the control signal line and the scanning line in a plan view. 4. The light emitting device according to claim 3 , wherein the scanning line and the control signal line are formed in the same layer. An electronic device including the light-emitting device as claimed in any one of claims 4.

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