JP5757888B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a termination circuit for matching with the impedance of a transmission line that propagates an input signal, and particularly to a semiconductor device that incorporates an on-die termination (ODT) whose impedance can be changed. It relates to effective technology.

  In the case of transmitting a high-frequency signal, a termination circuit that matches the impedance between the transmission line and the device is required to prevent signal distortion due to reflection noise. For example, when high-speed signal transmission / reception is performed between two ICs, an external termination circuit is often provided between the ICs. In the field of memory ICs such as high-speed SRAMs, the number of components is reduced. Many products have built-in termination circuits in memory ICs.

  Patent Document 1 discloses a conventional technique for a termination circuit built in a semiconductor device. Patent Document 1 discloses an ODT circuit (termination circuit) that can change the impedance of a node by switching connection of a plurality of resistors provided between a node to which a high-frequency signal is input and a power supply line. ) Is disclosed.

JP 2007-179725 A

  In the ODT circuit of Patent Document 1, the corresponding switch is turned on / off by a signal (impedance code) instructing which one of the plurality of resistors provided between the node and the power supply line is connected. Is controlled. This makes the impedance of the node variable.

  Prior to the present invention, the inventor of the present application considered incorporating a termination circuit whose impedance can be changed as described above into a semiconductor device that operates in synchronization with an internal clock signal generated based on an external clock signal. . As a result of the examination, the present inventor has found that there are the following problems.

  FIG. 15 illustrates a block diagram of a semiconductor device in which an ODT circuit whose impedance can be changed is applied to an input circuit for inputting an external clock signal, which was examined in advance by the inventor of the present application.

  The semiconductor device 8 shown in the figure is a logic circuit that generates an internal clock signal based on an external clock signal input from an input terminal K and operates in synchronization with the internal clock signal. The semiconductor device 8 is supplied with a power supply voltage VDDQ, a power supply voltage VDDI, and a ground voltage GND from a power supply terminal (not shown).

  The semiconductor device 8 includes an input terminal K to which an external clock signal is input, an input terminal VREF to which a reference voltage is supplied, an ODT circuit (ODT) 80 for matching the impedance of the input terminal K, and an ODT circuit 80 A control unit (CNT) 81 that adjusts impedance, a comparator (CMP) 82 that generates an internal clock signal CLK, and a core logic circuit 83 that operates based on the internal clock signal CLK are configured. Although not shown, the semiconductor device 8 further includes a power supply terminal, and the power supply voltage VDDQ, the power supply voltage VDDI, and the ground voltage GND are supplied from the power supply terminal.

  The core logic circuit 83 is, for example, a memory circuit, and includes a memory array for storing data, a memory control unit for controlling writing and reading of data with respect to the memory array, and the like, and is synchronized with the internal clock signal CLK. Then, writing and reading of data with respect to the memory array are controlled.

  In FIG. 15, the external clock signal input to the input terminal K is input to the comparator 82 via the ODT circuit 80. The external clock signal is, for example, an HSTL (High Speed Transceiver Logic) level signal and has a relatively small amplitude. The comparator 82 compares the reference voltage VREF with the voltage of the external clock signal input via the ODT circuit 80, and outputs the comparison result. The reference voltage VREF is, for example, a voltage that becomes 1 / 2VDDQ, and is generated by dividing the resistance of the power supply voltage VDDQ. The clock signal K input to the comparator 82 is, for example, a high-frequency signal, and reflection or the like is suppressed by impedance matching by the ODT circuit 80. As a result, the clock signal K input to the comparator 82 becomes a signal having a voltage amplitude substantially centered on the reference voltage VREF. As a result, the comparison result by the comparator 52 is output as a clock signal CLK having a period substantially equal to the period of the external clock signal K. The clock signal (internal clock signal) CLK is supplied as an operation clock for the core logic circuit 83, the control unit 81, and the like.

  The control unit 81 is a circuit for adjusting the impedance of the ODT circuit 80. For example, the control unit 81 generates an impedance code in synchronization with the internal clock signal CLK so that the impedance of the ODT circuit 80 becomes a target impedance. The ODT circuit 80 is adjusted in resistance value by controlling on / off of the MOS transistors MP0 to MP7 and MN0 to MN7 by the generated impedance code. Among the impedance codes, a P-side impedance code for controlling the gates of the P-channel MOS transistors MP0 to MP7 is represented as pcode [7: 0], and an N-side impedance code for controlling the gates of the N-channel MOS transistors MN0 to MN7 is represented by ncode. [7: 0]. Here, the initial values of the P-side impedance code pcode and the N-side impedance code ncode are substantially equal to the pull-up resistor on the power supply VDDQ side of the termination circuit 50 and the pull-down resistor on the ground side. The P-side impedance code pcode at that time is, for example, “10000000”, and the N-side impedance code ncode is, for example, “10000000”.

  FIG. 16 is a timing chart showing an example of a voltage change at each node in the semiconductor device 8. The figure illustrates the operation of the semiconductor device 8 in an ideal environment where noise or the like does not occur.

  First, when the power VDDI serving as a power source for the core logic circuit 83 or the like is supplied, a power-on reset signal rst_p is output by a reset circuit (not shown), and an initial value (initial code) is output as an impedance code. Thereafter, supply of the power supply VDDQ and the reference voltage VREF is started. At this time, when the external driver circuit 6 that supplies the clock signal K is in an inactive state (output is in a high impedance (Hi-Z) state), the voltage of the node connected to the input terminal K is the reference voltage VREF. Voltage close to. When the external driver circuit 6 is activated and the clock signal K is supplied, the comparator 82 generates the internal clock signal CLK. The control unit 81 starts adjusting the impedance of the ODT circuit 80 in synchronization with the generated internal clock signal CLK, and adjusts the resistance value of the ODT circuit 80 so that the target impedance is obtained. This figure illustrates the case where the P-side impedance code pcode is “10000001” and the N-side impedance code ncode is “01111111” as the impedance code corresponding to the target impedance.

  FIG. 17 is a timing chart showing another example of the voltage change at each node in the semiconductor device 8. The figure illustrates the operation of the semiconductor device 8 when noise occurs when the power is turned on.

  For example, when a ground noise is generated when the power supply voltage VDDQ is turned on and the noise is superimposed on a node to which the input terminal K is connected, the magnitude relationship between the voltages of the two input terminals in the comparator 82 is inverted, and the internal clock The signal CLK may be generated. Once such an illegal internal clock signal CLK is generated, the control unit 81 starts updating the impedance code using the illegal internal clock signal CLK as an operation clock. However, if the power supply voltage VDDQ or the reference voltage VREF does not rise sufficiently or if the pulse width and cycle of the clock signal CLK are not normal, the control unit 81 cannot perform impedance adjustment normally, There is a possibility that a simple impedance code is set in the ODT circuit 80. For example, as shown in FIG. 17, the P-side impedance code “11111111” that maximizes the pull-up resistance of the ODT circuit 80 is set as an erroneous impedance code, and the N-side that minimizes the pull-down resistance of the ODT circuit 80 When the impedance code “00000000” is set, the high level voltage of the clock signal K input to the comparator 80 becomes lower than the reference voltage VREF. Once in this state, the magnitude relationship between the voltages at the two input terminals of the comparator 82 does not change, and the internal clock signal CLK is not generated. That is, the control circuit 81 cannot update the impedance code because the internal clock signal CLK as the operation clock is not supplied. As a result, the impedance of the ODT circuit 80 is maintained in an abnormal state, and a deadlock state occurs in which the internal clock signal CLK is not generated even though the clock signal K is supplied from the outside. As a result, the core logic circuit 83 cannot operate and cannot accept any read / write command. When such a deadlock state occurs, it cannot be restored unless, for example, the power supply voltage is turned on again.

  An object of the present invention is to improve the stability of a termination circuit in a semiconductor device incorporating a termination circuit whose impedance can be changed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An outline of typical inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor device includes a clock signal generation unit that generates a clock signal based on an input signal that is input via a termination circuit configured to change impedance, and the termination circuit based on the clock signal. And a controller for adjusting impedance. The control unit performs processing for adjusting the impedance of the termination circuit so as to achieve a target impedance in synchronization with the clock signal, and determines that the clock signal is abnormal. Is changed to a predetermined impedance.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to this semiconductor device, the stability of the termination circuit whose impedance can be changed can be improved.

FIG. 1 is a block diagram of a semiconductor device to which an ODT circuit capable of changing impedance according to the first embodiment is applied. FIG. 2 is a block diagram illustrating an example of the circuit configuration of the impedance detection circuit 201. FIG. 3 is a block diagram illustrating an example of a circuit configuration of the clock signal abnormality detection circuit 204. FIG. 4 is a timing chart illustrating the operation of the low level detection unit 2040. FIG. 5 is a flowchart showing an example of the flow of the impedance adjustment method of the ODT circuit 10. FIG. 6 is a timing chart illustrating an example of a voltage change at each node in the semiconductor device 1. FIG. 7 is a block diagram of a semiconductor device to which an ODT circuit with variable impedance according to the second embodiment is applied. FIG. 8 is a block diagram showing an example of the circuit configuration of the clock signal abnormality detection circuit 214. FIG. 9 is a timing chart illustrating the operation of the low level detection unit 2140. FIG. 10 is a block diagram of a semiconductor device to which an ODT circuit with variable impedance according to the third embodiment is applied. FIG. 11 is a flowchart illustrating an example of a flow of an impedance adjustment method for the ODT circuit 10 in the semiconductor device 3. FIG. 12 is a timing chart showing an example of a voltage change at each node in the semiconductor device 3. FIG. 13 is a block diagram of a semiconductor device to which an ODT circuit with variable impedance according to the fourth embodiment is applied. FIG. 14 is a detailed block diagram of a peripheral circuit of the input terminal K. FIG. 15 is a block diagram of a semiconductor device to which a termination circuit capable of changing impedance, which was examined in advance by the inventors of the present application. FIG. 16 is a timing chart showing an example of a voltage change at each node in the semiconductor device 8. FIG. 17 is a timing chart showing another example of the voltage change at each node in the semiconductor device 8.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (If an abnormal state of the internal clock signal is detected, the impedance of the ODT circuit is changed)
The semiconductor devices (1 to 4) according to the representative embodiments of the present invention are configured so that the internal impedance can be changed, and are terminated to match the impedance of an external transmission line that propagates the input signal (K). A circuit (10), a clock signal generator (50) for generating a clock signal (intCLK) according to the signal level of the input signal input via the termination circuit, and the termination based on the clock signal And a control unit (20-22) for adjusting the impedance of the circuit. The control unit performs processing for adjusting the impedance of the termination circuit so as to achieve a target impedance in synchronization with the clock signal, and determines that the clock signal is abnormal. Is changed to a predetermined impedance.

  For example, let us consider a case where the signal level of the input signal becomes abnormal because the impedance of the termination circuit is not set to an appropriate value, and the clock signal becomes a signal fixed at a high level or a low level. In the semiconductor device 8 of FIG. 15 described above, in such a case, the clock signal is not substantially output, and therefore the adjustment of the impedance of the termination circuit synchronized with the clock signal by the control unit is stopped. Therefore, according to the semiconductor device of Item 1, when the control unit detects an abnormality of the clock signal, the impedance of the termination circuit is changed to the predetermined impedance, so that the input input to the clock signal generation unit The signal level of the signal can be changed. As a result, it is possible to escape from the state in which an abnormal clock signal is generated.

[2] (predetermined impedance)
In the semiconductor device according to Item 1, the input signal is an external clock signal, and the clock signal generation unit includes a comparison circuit (50) that compares the signal level of the external clock signal with the signal level of a reference voltage (VREF). And the comparison circuit outputs the comparison result as the clock signal. The predetermined impedance is such that a high level voltage of the external clock signal input to the clock signal generation unit is larger than the reference voltage, and a low level voltage of the external clock signal is smaller than the reference voltage. Impedance.

  According to this, it is possible to output again the clock signal that has been stopped due to an abnormal signal level of the input signal due to an abnormal impedance of the termination circuit. Thereby, after detecting the abnormality of the clock signal, the process for setting the impedance of the termination circuit to the target value can be resumed.

[3] (Specific example of clock abnormality detection circuit)
In the semiconductor device (1, 3, 4) according to Item 1 or 2, the control unit becomes a high level or a low level for a predetermined period (td) longer than a high level period or a low level period in which the clock signal is expected. Then, it is determined that the clock signal is abnormal.

  According to this, for example, not only when the clock signal is fixed at high level or low level, but also when the duty ratio of the clock signal is out of the target range, it can be detected as an abnormality of the clock signal. .

[4] (The detection period of abnormal conditions can be changed)
In the semiconductor device (2) according to Item 3, the predetermined period is configured to be changeable.

  According to this, for example, the reference for determining that the clock signal is abnormal can be changed according to the specification of the semiconductor device.

[5] (When an abnormal state of the clock signal is detected, a reset signal is output)
In the semiconductor device according to any one of Items 2 to 4, the initial value of the impedance of the termination circuit is the predetermined impedance. The control unit monitors the clock signal with an impedance adjustment unit (201, 202, 205) that adjusts the impedance of the termination circuit, and outputs a reset signal when it is determined that the clock signal is abnormal ( 204). The impedance adjustment unit adjusts the impedance of the termination circuit to be a target impedance in synchronization with the clock signal, and when the reset signal is output, the impedance of the termination circuit is set to the initial value. Reset it.

  According to this, it is possible to easily realize a function to escape from the abnormal state of the clock signal due to the impedance of the termination circuit.

[6] (Initial value is an intermediate impedance value)
In the semiconductor device according to any one of Items 2 to 5, the predetermined impedance is determined based on an intermediate value within a range that can be set as the impedance of the termination circuit.

  According to this, for example, if the high level of the external clock signal is the power supply voltage, the low level is the ground voltage, and the reference voltage is half the power supply voltage, the clock signal is often easily The high level voltage of the external signal input to the generation unit can be made higher than the reference voltage, and the low level voltage can be made lower than the reference voltage.

[7] (Used as a reset signal for the core logic circuit)
The semiconductor device (4) according to Item 5 further includes an internal circuit (60, 61) that operates based on the clock signal. The internal circuit is configured to be initialized by the reset signal.

  According to this, when the clock signal becomes abnormal, the internal circuit can be reset. For example, by stopping the external clock signal, the internal circuit can be reset without turning on the power again, and there is no need to further provide an external terminal dedicated to resetting.

[8] (Memory circuit)
In the semiconductor device (4) according to Item 7, the internal circuit includes a memory unit (613) including a storage area for storing data, and data for the memory unit in synchronization with a signal (C_CLK) based on the clock signal. Memory control units (610, 611, 612, 614) for writing and reading data.

  According to this, for example, by stopping the external clock signal, it is possible to reset the memory unit and the memory control unit without turning on the power again, and it is necessary to further provide an external terminal dedicated to resetting. Nor.

[9] (Forced off of ODT circuit)
In the semiconductor device (3) according to any one of Items 2 to 5, 7, and 8, the predetermined impedance is determined by the termination circuit being in a high impedance state.

  According to this, for example, if the high level of the external clock signal is the power supply voltage, the low level is the ground voltage, and the reference voltage is half the power supply voltage, the quality of the waveform is reduced, but the clock signal The high level voltage of the external signal input to the generation unit is a voltage about the power supply voltage, and the low level voltage is a voltage about the ground voltage. That is, the high level voltage of the external signal input to the clock signal generation unit can be easily made higher than the reference voltage, and the low level voltage can be made lower than the reference voltage.

[10] (A predetermined period Hiz after reset detection)
In the semiconductor device (3) according to any one of Items 2 to 4, the control unit monitors an impedance adjustment unit (201, 202, 205, 210) that adjusts an impedance of the termination circuit, the clock signal, and And a monitoring unit (204) that outputs a reset signal (stopc) when it is determined that the clock signal is abnormal. When the reset signal is output, the impedance adjusting unit sets the termination circuit to a high impedance state, performs a process of calculating the target impedance value in synchronization with the clock signal, and performs a predetermined time (for example, After the 1024 cycles), the impedance of the termination circuit is updated to the calculated value.

  An impedance code capable of generating the clock signal by propagating a pulse of the input signal to the inside of the semiconductor device depending on conditions such as an on-resistance and a power supply voltage range of an external driver circuit that supplies the input signal It may be difficult to find the initial value of. On the other hand, as described in Item 9, for example, when the external clock signal has a high level of the power supply voltage, a low level of the ground voltage, and the reference voltage is half the power supply voltage, the termination circuit is The clock signal can be generated more reliably by setting the high impedance (Hi-Z) state. Therefore, as in the semiconductor device of item 10, the clock signal is generated more reliably by setting the termination circuit in a high impedance state for a certain period after detecting the abnormal state of the clock signal. Based on the above, the target impedance value is calculated. As a result, the impedance of the termination circuit can be set to a target value more reliably than in the case where the abnormality is detected in the clock signal and then reset to the initial value.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates a block diagram of a semiconductor device to which an ODT circuit whose impedance can be changed is used as a termination circuit for an input terminal to which an external clock signal is input.

  The semiconductor device 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

  The semiconductor device 1 is a logic circuit that operates based on an external clock signal input from an input terminal K. Specifically, the semiconductor device 1 generates an ODT circuit (ODT) 10 for matching the impedance of the input terminal K, a control unit (IMP_CNT) 20 for adjusting the impedance of the ODT circuit 10, and a reference voltage ZREF. A reference voltage generation circuit 30, a reset circuit (RESET) 40, a comparator (CMP) 50 that generates an internal clock signal CLK, and a core logic circuit (CIR) 60 that operates based on the internal clock signal CLK. Consists of including. The core logic circuit 60 is, for example, a memory circuit, and includes a memory array for storing data, a memory control unit for controlling writing and reading of data with respect to the memory array, and the like, and is synchronized with the internal clock signal CLK. Then, writing and reading of data with respect to the memory array are controlled. In addition, although not shown, an input interface circuit for receiving input signals such as an address signal, a read signal, and a write signal for the memory circuit, and an output interface circuit for outputting data and the like are also provided.

  In addition, the semiconductor device 1 connects, as external terminals, an input terminal K to which an external clock signal is input, an input terminal VREF to which a reference voltage is supplied, and an external resistor that serves as a reference for determining the impedance of the ODT circuit. Input terminal ZQ. In addition, although not shown, a power supply terminal VDDQ to which a power supply voltage is supplied, a power supply terminal VDDI to which a power supply voltage is supplied, a ground terminal GND to which a ground voltage is supplied, and the like are also provided. Note that reference numerals VDDQ, VDDI, and GND represent not only terminals but also voltages supplied to the terminals. The power supply voltage VDDI is supplied as power for internal circuits such as the core logic circuit 60. The power supply voltage VDDQ is supplied as a power supply for the I / O unit of the ODT circuit 10 or the like. Although the power supply voltage VDDI and the power supply voltage VDDQ depend on the manufacturing process of the semiconductor device 1, for example, the power supply voltage VDDI is 1.1V and the power supply voltage VDDQ is 1.5V to 1.8V.

  In the following description, the reference symbol K represents not only an input terminal but also a node connected to the terminal and an external clock signal supplied to the terminal. The reference symbol VREF represents not only an input terminal but also a node connected to the terminal and a reference voltage supplied to the terminal. Further, the reference symbol ZQ represents not only the input terminal but also a node connected to the terminal and a voltage generated at the terminal.

  As shown in FIG. 1, an external clock signal is supplied to the input terminal K from the external driver circuit 6. The input external clock signal K is input to one input terminal of the comparator 50 via the ODT circuit 10. The external clock signal K supplied from the external driver circuit 6 to the input terminal K is, for example, an HSTL (High Speed Transceiver Logic) level signal and has a relatively small amplitude. For this reason, the comparison circuit 50 compares the voltage level of the external clock signal K with the voltage level of the reference voltage VREF, and outputs the comparison result, whereby a large amplitude (VDDQ-GND) is generated from the external clock signal K having a small amplitude. ) Internal clock signal intCLK. This enables high-speed transmission of the external clock signal K while reducing the common-mode noise of the external clock signal K. The reference voltage VREF is, for example, a voltage that becomes 1 / 2VDDQ, and is generated by dividing the power supply voltage VDDQ by the external resistor R.

  The external clock signal K is a signal having a relatively high frequency, for example, a signal having a frequency of 500 MHz or more. Therefore, in order to suppress the reflection of the signal at the input terminal K, it is necessary to match the impedance of the external transmission path that propagates the external clock signal K. Therefore, the semiconductor device 1 includes an ODT circuit 10 connected to the input terminal K. Although details will be described later, the ODT circuit 10 adjusts the resistance value of the termination resistor so that the external clock signal K having a signal level suitable for generating the internal clock signal intCLK is propagated to the comparator 50. For example, the resistance value is adjusted so that the external clock signal K input to the comparator 50 becomes a signal having an amplitude that is substantially centered on the reference voltage VREF. As a result, the internal clock signal intCLK has a cycle substantially equal to the cycle of the external clock signal K, and the high level is a VDDQ level and the low level is a GND level signal. The internal clock signal intCLK is supplied to the core logic circuit 60, the control unit 20, and the like.

  The reset circuit 40 monitors the power supply voltage VDDI and generates a reset signal rst. For example, the reset signal rst is set to the high level for a certain period immediately after the power supply VDDI is turned on.

  The ODT circuit 10 is configured so that the connection of a plurality of resistors connected to the node K can be switched in order to change the impedance of the node K. The ODT circuit is, for example, a termination circuit constituting a Thevenin termination, and includes pull-up resistors RP0 to RP7, pull-down resistors RN0 to RN7, PMOS transistors MP0 to MP7, and NMOS transistors MN0 to MN0. MN7 is provided. Specifically, one end of each of the plurality of pull-up resistors RP0 to RP7 is connected to the node K, the other end of the pull-up resistors RP0 to RP7 is connected to the drain side of the corresponding PMOS transistor MP0 to MP7, and the PMOS transistor MP0. The source side of .about.MP7 is connected to the power supply node VDDQ. Also, one end of each of the plurality of pull-down resistors RN0 to RN7 is connected to the node K, the other end of the pull-down resistors RN0 to RN7 is connected to the drain side of the corresponding NMOS transistor MN0 to MN7, and the source side of the NMOS transistors MN0 to MN7 is connected to the node K. Connected to ground node GND. The PMOS transistors MP0 to MP7 and the NMOS transistors MN0 to MN7 function as switches, and are turned on / off by the impedance code supplied from the control unit 20, so that the pull-up resistance value and the pull-down resistance value of the node K are increased. Adjusted. As in FIG. 16, the P-side impedance code for controlling the gates of the P-channel MOS transistors MP0 to MP7 among the impedance codes is represented by pcode, and the N-side impedance for controlling the gates of the N-channel MOS transistors MN0 to MN7. The code is represented as ncode. In FIG. 1, the number of bits of the P-side impedance code pcode and the N-side impedance code ncode is set to 8 bits in order to control 8 PMOS transistors and 8 NMOS transistors. In FIG. 1, an ODT circuit including eight PMOS transistors and eight NMOS transistors is illustrated to control connection and disconnection of eight pull-up resistors and eight pull-down resistors. However, the number of resistors and MOS transistors may be arbitrarily changed according to the impedance adjustment range.

  The control unit 20 is a circuit for adjusting the impedance of the ODT circuit 10. The control unit 20 adjusts the pull-up resistor and the pull-down resistor of the ODT circuit 10 so that the target impedance is obtained. The target impedance is determined based on an external resistor RQ connected to the input terminal ZQ. For example, the control unit 20 adjusts the pull-up resistor and the pull-down resistor of the ODT circuit 10 so as to have the same resistance value as that of the external resistor RQ.

  Specifically, the control unit 20 includes an impedance detection circuit (REP) 201, an impedance code generation circuit (IMPC_GEN) 202, an impedance code holding register 205, a counter (CTR) 203, a clock signal abnormality detection circuit 204, and an OR circuit 206. Consists of including.

  The impedance detection circuit 201 is a circuit for detecting the resistance value of the resistor RQ connected to the input terminal ZQ. Specifically, the impedance detection circuit 201 compares the voltage generated based on the resistor RQ connected to the input terminal ZQ with the reference voltage ZREF, and outputs comparison results n_up and p_dn.

  FIG. 2 shows an example of the circuit configuration of the impedance detection circuit 201. The impedance detection circuit 201 includes a replica circuit 2011 for determining the pull-up resistance value of the ODT circuit 10 and a replica circuit 2012 for determining the pull-down resistance value of the ODT circuit 10.

  In the replica circuit 2011, one end of each of the plurality of pull-up resistors RPR0 to RPR7 is connected to the node ZQ to which the input terminal ZQ is connected, and the other end of each of the pull-up resistors RPR0 to RPR7 is the corresponding PMOS transistor MPR0. ~ Connected to the drain side of MPR7. The source sides of the PMOS transistors MPR0 to MPR7 are connected to the power supply line VDDQ. For example, the pull-up resistors RPR0 to RPR7 have the same resistance value as the pull-up resistors RP0 to RP7 of the ODT circuit 10.

  The control signal pre_pcode output from the impedance code generation circuit 202 is inverted by the level conversion circuit 2013, converted into a signal of the power supply voltage VDDQ level, and supplied to the gates of the PMOS transistors MPR0 to MPR7. The control signal pre_pcode is an impedance code for determining the pull-up resistance value of the replica circuit 2011, and is a gate drive signal for controlling on / off of the PMOS transistors MPR0 to MPR7. The control signal pre_pcode is, for example, a signal having the number of bits corresponding to the number of gates of the PMOS transistors MPR0 to MPR7. In the case of FIG. 2, the control signal pre_pcode is an 8-bit signal. By controlling on / off of the PMOS transistors MPR0 to MPR7 by the control signal pre_pcode, the resistance value of the pull-up resistor of the node ZQ is adjusted.

  The comparator (CMP) 2014 compares the voltage of the node ZQ with the reference voltage ZREF generated by the reference voltage generation circuit 30, and outputs a comparison result p_dn. The reference voltage ZREF is, for example, a voltage that becomes 1 / 2VDDQ, and is generated by resistance voltage division. The voltage at node ZQ is determined by the resistance voltage division between pull-up resistor at node ZQ and external resistor RQ. Therefore, for example, when the pull-up resistor at the node ZQ is smaller than the external resistor RQ, the voltage at the node ZQ is higher than ½ VDDQ.

  The comparison result p_dn by the comparator 2014 is supplied to the impedance code generation circuit 202. The impedance code generation circuit 202 operates in synchronization with the internal clock signal intCLK, and generates control signals pre_pcode and pre_ncode based on the comparison results p_dn and n_up. Specifically, the impedance code generation circuit 202 updates the control signal pre_pcode as needed in synchronization with the internal clock signal intCLK according to the comparison result p_dn, thereby controlling the node ZQ until it has the same potential as the reference voltage ZREF. The signal pre_pcode is repeatedly updated. For example, when the comparison result p_dn is high (High), the impedance code generation circuit 202 is a code obtained by setting the control signal pre_pcode to “−1” from the current code value when the next code value is updated (at the time of update). Change to a value. When the comparison result p_dn is low, the impedance code generation circuit 202 sets the code obtained by adding “+1” to the control signal pre_pcode from the current code value when the next code value is updated (code update). Change to a value. These processes are repeated until the node ZQ has the same potential as the reference voltage ZREF. As a result, the control signal pre_pcode is generated so that the resistance value of the pull-up resistor at the node ZQ is approximately the same as that of the external resistor RQ.

  The replica circuit 2012 includes a resistance group and a MOS transistor group having a circuit configuration similar to that of the ODT circuit 10 between the power supply node VDDQ and the ground node GND.

  A specific circuit configuration on the power supply node VDDQ side of the replica circuit 2012 is as follows. One end of each of the plurality of pull-up resistors RNPR0 to RNPR7 is connected to the node ZN, the other end of the pull-up resistors RNPR0 to RNPR7 is connected to the drain side of the corresponding PMOS transistor MNPR0 to MNPR7, and the PMOS transistors MNPR0 to MNPR7 The source side is connected to the power supply line VDDQ. For example, the pull-up resistors RNPR0 to RNPR7 have the same resistance value as the pull-up resistors RPR0 to RPR7 of the replica circuit 2011. That is, the resistance value is the same as the pull-up resistors RP0 to RP7 of the ODT circuit 10. Similar to the replica circuit 2011, the on / off of the PMOS transistors MPR0 to MPR7 is controlled based on the control signal pre_pcode output from the impedance code generation circuit 202, so that the resistance value on the pull-up side of the node ZN is adjusted. The

  A specific circuit configuration on the ground node GND side of the replica circuit 2012 is as follows. One end of each of the plurality of pull-down resistors RNNR0 to RNNR7 is connected in parallel to the node ZN, the other end of each of the pull-down resistors RNNR0 to RNNR7 is connected to the drain side of the corresponding NMOS transistor MNNR0 to MNNR7, and the NMOS transistors MNNR0 to MNNR7 Is connected to the ground line GND. The pull-down resistors RNNR0 to RNNR7 have the same resistance value as the pull-down resistors RN0 to RN7 of the ODT circuit 10, for example.

  The control signal pre_ncode [7: 0] output from the impedance code generation circuit 202 is converted into a signal of the power supply voltage VDDQ level by the level conversion circuit 2016 and supplied to the gates of the NMOS transistors MNNR0 to MNNR7. The control signal pre_ncode is an impedance code for determining the pull-down resistance value of the replica circuit 2012. Thereby, the on / off state of the NMOS transistors MNNR0 to MNNR7 is controlled, so that the pull-down resistance value of the node ZN is adjusted.

  The comparator (CMP) 2015 compares the voltage of the node ZN with the reference voltage ZREF and outputs a comparison result n_up. The voltage at the node ZN is determined by the resistance voltage division between the pull-up resistor and the pull-down resistor at the node ZN. Therefore, for example, when the pull-up resistance of the node ZN is smaller than the pull-down resistance, the voltage of the node ZQ becomes higher than ZVREF (= 1 / 2VDDQ).

  The comparison result n_up by the comparator 2015 is supplied to the impedance code generation circuit 202. The impedance code generation circuit 202 updates the control signal pre_ncode until the node ZN becomes the same potential as the reference voltage ZREF by updating the control signal pre_ncode as needed in synchronization with the internal clock signal intCLK according to the comparison result n_dn. Repeat. For example, when the comparison result n_up is High, the impedance code generation circuit 202 changes the control signal pre_ncode to a code value that is “+1” from the current code value, and when the comparison result n_up is Low. The control signal pre_ncode is changed to a code value obtained by subtracting “−1” from the current code value. As a result, the resistance value on the pull-down side of the node ZN is finally adjusted to be the same resistance value as the resistance value on the pull-up side of the node ZN. That is, the control signal pre_ncode is generated so that the pull-down resistor of the node ZN has substantially the same resistance value as the external resistor RQ.

  The impedance code generation unit 202 inputs the signal rsdot as a reset signal. The signal rstdot is a signal obtained by ORing the reset signal rst output from the reset circuit 40 and the detection signal stopc output from the clock signal abnormality detection circuit 204. For example, the impedance code generation unit 202 resets the code values of the control signals pre_pcode and nre_pcode to initial values when the signal level of the signal rsdot reaches a high level. The initial value is a code such that the high level voltage of the external clock signal K input to the comparator 50 is larger than the reference voltage VREF and the low level voltage of the external clock signal K is smaller than the reference voltage VREF. Value. For example, a code value that makes the impedance of the ODT circuit 10 an intermediate value within a settable impedance range is set as an initial value. Here, as an example, the initial values of the control signals pre_pcode and pre_ncode are set to intermediate values of 8-bit values that can be set as the control signals pre_pcode and pre_ncode, that is, “8′b10000000”.

  The control signals pre_pcode and pre_ncode generated by the impedance code generation unit 202 are output to the impedance detection circuit 201 and also output to the impedance code holding register 205. The impedance code holding register 205 includes a flip-flop (FF) circuit 2051 that holds a P-side control signal pre_pcode and an FF circuit 2052 that holds an N-side control signal pre_ncode. The FF circuit 2051 inputs, for example, a strb signal obtained by dividing the internal clock signal intCLK by 256 by the counter 203 as a clock input and a signal rsdot as a reset signal. As a result, the FF circuit 2051 takes in the value of the control signal pre_pcode every 256 cycles. The acquired value is output to the ODT circuit 10 as the P-side impedance code pcode [7: 0]. Similarly, the FF circuit 2052 takes in the control signal pre_ncode [7: 0] every 256 cycles, and outputs the taken value to the ODT circuit 10 as the N-side impedance code ncode [7: 0]. That is, the control signals pre_pcode and pre_ncode adjusted to have the same resistance value as the external resistor RQ are supplied to the ODT circuit 10 as the impedance codes pcode and ncode. Thereby, the pull-up resistor and the pull-down resistor of the ODT circuit 10 are adjusted so as to have the same resistance value as that of the external resistor RQ. The time interval for updating the P-side impedance code pcode and the N-side impedance code ncode is not limited to 256 cycles, and can be arbitrarily set.

  The clock signal abnormality detection circuit 204 monitors the internal clock signal intCLK and, when detecting the abnormality of the internal clock signal intCLK, switches the signal level of the detection signal stopc from, for example, a low level to a high level. In the present embodiment, the abnormality of the internal clock signal intCLK is, for example, that the internal clock signal intCLK is at a low level for a predetermined period (td) longer than the expected low level period, and the internal clock signal intCLK is expected. The high level for a predetermined period (td) longer than the high bell period.

  FIG. 3 shows an example of the circuit configuration of the clock signal abnormality detection circuit 204. As shown in the figure, the clock signal abnormality detection circuit 204 has two detection units. One detection unit is a low level detection unit 2040, which detects that the internal clock signal intCLK has been at a low level for a period longer than the expected low level period. The robel detection circuit 2040 includes the delay circuit 101. The delay circuit 101 receives the internal clock signal intCLK, and switches the output signal LFIX from a high level to a low level when the internal clock signal intCLK is at a low level for a predetermined period td or longer. The predetermined period td is a time until the voltage of the node N1 exceeds the threshold voltage of the next-stage inverter (INV), and is determined by a time constant based on the resistor R1 and the capacitor C1 in FIG. Here, the resistance value of the resistor R1 is sufficiently larger than that of the resistor R2. As a result, the time required for the voltage rise is longer than the time required for the voltage drop at the node N1. The output signal LFIX of the low level detection circuit 2040 is input to the NAND circuit 100, and the output of the NAND circuit 100 becomes the detection signal stopc.

  FIG. 4 is a timing chart illustrating the operation of the low level detection unit 2040.

  As shown in the figure, for example, when the internal clock signal intCLK becomes low level at time t40, the voltage of the node N1 rises. Then, at time t41 when a predetermined time td determined based on the time constant between the resistor R1 and the capacitor C1 has elapsed, the output signal LFIX switches from the high level to the low level. As a result, the signal level of the detection signal stopc is switched from the low level to the high level. Thereafter, when the internal clock signal intCLK is normally output again at time t42, the output signal LFIX changes from low level to high level at time t43 when a time determined based on the time constant of the resistor R2 and the capacitor C1 has elapsed. The signal level of the detection signal stopc is switched from the high level to the low level.

  Another detection unit in the clock signal abnormality detection circuit 204 is a high level detection unit 2041, which detects that the internal clock signal intCLK has been at a high level for a period longer than the expected high level period. The high level detection circuit 2041 includes the inverter 104 and the delay circuit 101. The internal clock signal intCLK is input to the inverter 104, and the signal inverted by the inverter 104 is input to the delay circuit 101 at the subsequent stage. The subsequent operation is the same as that of the delay circuit 101 of the low level detection circuit 2040. The output signal HFIX from the high bell detection circuit 2041 is input to the NAND circuit 100 in the same manner as the output signal LFIX.

  The detection signal stopc is input to the OR circuit 206 together with the reset signal rst from the reset circuit 40, and the output signal rstott of the OR circuit 206 becomes a reset signal for the impedance code generation circuit 202, the impedance code holding register 205, and the counter 203. . Therefore, the P-side impedance code pcode, the N-side impedance ncode, and the control signals pre_pcode and pre_ncode are not only immediately after the power is turned on, but also the impedance code of the ODT circuit 10 becomes abnormal, and the internal clock signal intCLK is fixed at the high level or the low level. It is also reset when it becomes.

  FIG. 5 is a flowchart showing an example of the flow of the impedance adjustment method of the ODT circuit 10.

  First, power supply voltages VDDI and VDDQ are input to the semiconductor device 1 (S101). When the reset signal rst is validated after the power is turned on, the impedance code generation circuit 202 sets an initial value “8′b10000000” as the control signals pre_pcode and pre_ncode (S102). Thereafter, when the external clock signal K is input and the internal clock signal intCLK is generated, the impedance code generation circuit 202 starts updating pre_pcode and pre_ncode (S103). Then, the counter 203 starts counting the internal clock signal intCLK (S104). When the count value of the counter 203 reaches N (N is an integer of 1 or more) times 256 cycles, the impedance code generation circuit 202 updates the values of the control signals pcode and ncode to the values of pre_pcode and pre_ncode, respectively. (S104). Thereby, the resistance value of the ODT circuit 10 is updated, and impedance matching of the input terminal K is performed.

  Meanwhile, the clock signal abnormality detection circuit 204 determines whether or not the internal clock signal intCLK has become a low level or a high level for a predetermined period td or more (S106). When the internal clock signal intCLK is normally output, the process proceeds to step 103, and the control signals pre_pcode and pre_ncode are continuously updated. On the other hand, when the internal clock signal intCLK becomes the low level or the high level for the predetermined period td or longer, the clock signal abnormality detection circuit 204 switches the detection signal stopc from the low level to the high level (S107). As a result, the impedance code generation circuit 202 and the like are reset, and the process proceeds to step 102.

  FIG. 6 is a timing chart illustrating an example of a voltage change at each node in the semiconductor device 1.

  First, when the power supply voltage VDDI is turned on at time t60, the reset signal rst from the reset circuit 40 is set to a high level, so that the reset signal rstdot is set to a high level. As a result, the impedance code generation circuit 202 and the like are reset, and the impedance code generation circuit 202 sets initial values (8'10000000) as the P-side impedance code pcode and the N-side impedance code ncode. At this time, it is assumed that the external driver circuit 6 that generates the external clock signal K is in an inactive state (output is in a high impedance (Hi-Z) state).

  Thereafter, at time t61, the power supply voltage VDDQ is supplied and the reference voltage VREF is supplied. If the external driver circuit 6 is inactive while the power supply voltage VDDQ is rising, the voltage at the node K connected to the input terminal K becomes a voltage close to the reference voltage VREF. In this state, when ground noise is generated for some reason and the ground noise is superimposed on the node connected to the input terminal K, the magnitude relationship between the voltages of the two input terminals in the comparator 50 is inverted as described above. Then, an abnormal internal clock signal intCLK is generated. Since the abnormal internal clock signal intCLK is supplied as an operation clock of the impedance code generation circuit 202, the impedance code generation circuit 202 starts updating the impedance code. However, if the power supply voltage VDDQ or the reference voltage VREF does not rise sufficiently and the pulse width and cycle of the clock signal CLK are not normal, an incorrect impedance code may be set in the ODT circuit 10. . In FIG. 6, as an example of an improper impedance code, a P-side impedance code pcode “11111111” that maximizes the pull-up resistance is set, and an N-side impedance code ncode “00000000” that minimizes the pull-down resistance is set. It is shown. In this case, since the pull-down resistance of the input terminal K has a resistance value sufficiently smaller than the pull-up resistance, the signal level of the external clock signal K propagated to the comparator 50 is lowered. For example, the high level voltage of the external clock signal K falls below the reference voltage VREF. Once in this state, the magnitude relationship between the voltages at the two input terminals of the comparator 52 does not change, and the internal clock signal CLK is fixed at a low level at time t62. At time t63 when td time has elapsed after the internal clock signal intCLK is fixed at the low level, the clock signal abnormality detection circuit 204 detects an abnormality in the internal clock signal intCLK and switches the detection signal stopc from the low level to the high level. . As a result, the reset signal rssdot becomes high level, the impedance code generation circuit 202 and the like are reset, and the P-side impedance code pcode and the N-side impedance code ncode are reset to the initial value (8'10000000). Is done. Thereby, since the impedance of the node K can be removed from the abnormal state, the external clock signal K having an appropriate signal level is propagated to the comparison circuit 50, and the internal clock signal intCLK is normally output. Thereafter, the impedance code generation circuit 202 normally updates the impedance code, and the resistance value of the ODT circuit 10 is adjusted so that the impedance code is based on the external resistance RQ.

  In the semiconductor device 8 of FIG. 15 described above, when the internal clock signal CLK is fixed to a low level or a high level due to an abnormality in the impedance of the ODT circuit, a deadlock state occurs. could not. However, according to the semiconductor device 1 according to the present embodiment, even if the internal clock signal CLK is fixed at a low level or a high level due to an abnormality in the impedance of the ODT circuit, Since the impedance code is reset, it is possible to escape from the abnormal state of the impedance of the ODT circuit. Thereby, a more stable ODT circuit can be realized.

<< Embodiment 2 >>
FIG. 7 illustrates a block diagram of a semiconductor device to which the ODT circuit with variable impedance according to the second embodiment is applied. In the figure, the same components as those of the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, a predetermined time during which the internal clock signal intCLK is fixed at a high level or a low level for determining that the internal clock signal intCLK is abnormal is configured to be selectable. Specifically, the semiconductor device 2 includes a clock signal abnormality detection circuit 214 instead of the clock signal abnormality detection circuit 204.

  FIG. 8 shows an example of the circuit configuration of the clock signal abnormality detection circuit 214. The clock signal abnormality detection circuit 214 shown in the figure has two detection units. One detection unit in the clock signal abnormality detection circuit 214 is a low level detection unit 2140, which detects that the internal clock signal intCLK has been at a low level for a period longer than the expected low level period. Specifically, the low-bell detection circuit 2142 includes a plurality of delay circuits 101_A to 101_C and a selector 102. The circuit configuration of the delay circuits 101_A to 101_C is similar to that of the delay circuit 101 described above. A plurality of delay circuits 101_A to 101_C are connected in series, and the output of each delay circuit 101 is input to the selector 102. Specifically, the delay circuit 101_A receives the internal clock signal intCLK, the delay circuit 101_B receives the output signal SEL01L of the delay circuit 101_A, and the delay circuit 101_C receives the output signal SEL00L of the delay circuit 101_B. As a result, three types of signals whose signal level is switched after a lapse of a certain time after the internal clock signal intCLK is switched to the low level can be generated. The selector 102 selects and outputs the output signal of the corresponding delay circuit 101_A to 101_C based on the selection signal SEL [1: 0] indicating one of the three types of signals. For example, when the selection signal SEL [1: 0] = 2′b00, the output of the delay circuit 101_B is selected, and the pulse width of the output signal LFIX is tLow−2td. In this case, when the low-level period of the internal clock signal intCLK is 2 td or more, the detection signal stopc becomes high level. When the selection signal SEL [1: 0] = 2′b01, the output of the delay circuit 101_A is selected, and when the low level period of the internal clock signal intCLK is equal to or greater than td, the detection signal stopc becomes high level. Become. Further, in the case of the selection signal SEL [1: 0] = 2′b10, when the output of the delay circuit 101_C is selected and the low-level period of the internal clock signal intCLK becomes 3td or more, the detection signal stopc is set to the high level. Become. Note that the selection signal SEL may be input from the outside, or a value of a register or the like provided inside the semiconductor device 2 may be input. Further, if the selection signal SEL can be changed by a fuse (FUSE) or a bonding option, adjustment according to the system to be used can be performed.

  FIG. 9 illustrates a timing chart representing the operation state of the low level detection unit 2140. In the figure, when the internal clock signal intCLK becomes low level at time t90, the voltage of the node N1 in the delay circuit 101_A increases. After that, when the voltage at the node N1 reaches the threshold voltage of the inverter at time t91, the signal level of the output signal SEL01L of the delay circuit 101_A is switched from the high level to the low level. Accordingly, the voltage increase at the node N1 in the delay circuit 101_B is started. When the voltage of the node N1 reaches the threshold voltage of the inverter at time t92, the signal level of the output signal SEL00L of the delay circuit 101_B is switched from the high level to the low level. Accordingly, the voltage increase at the node N1 in the delay circuit 101_C is started. When the voltage of the node N1 reaches the threshold voltage of the inverter at time t93, the signal level of the output signal SEL10L of the delay circuit 101_C is switched from the high level to the low level. As described above, the selector 102 selects one of the output signals of the delay circuits 101_A to 101_C based on the selection signal SEL. In FIG. 9, for example, the selection signal SEL [1: 0] = 2′b00 is selected, and the output signal SEL00L of the delay circuit 101_B is selected and output as the output signal LFIX of the low level detection unit 2140. . As a result, the detection signal stopc becomes high level at time t92 and becomes low level at time t94 when the clock signal returns to normal.

  Another detection unit in the clock signal abnormality detection circuit 214 is a high level detection unit 2141 that detects that the internal clock signal intCLK has been at a high level for a period longer than the expected high level period. Specifically, as illustrated in FIG. 8, the high level detection circuit 2143 includes an inverter 104, a plurality of delay circuits 101_D to 101_F, and a selector 103. The circuit configuration of the delay circuits 101_D to 101_F is similar to that of the delay circuit 101 described above. The internal clock signal intCLK is input to the inverter 104, and the output of the inverter is input to the delay circuit 101_D. Other connection relationships are the same as those of the low level detection unit 2140.

  As described above, according to the semiconductor device 2 according to the second embodiment, similarly to the semiconductor device 1, a more stable ODT circuit can be realized. In addition, a predetermined time for fixing the internal clock signal intCLK to high level or low level for determining that the internal clock signal intCLK is abnormal can be selected by the selection signal SEL. The predetermined time can be easily adjusted.

<< Embodiment 3 >>
FIG. 10 illustrates a block diagram of a semiconductor device to which the ODT circuit with variable impedance according to the third embodiment is applied. In the figure, the same components as those of the semiconductor devices 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the semiconductor device 1, when the abnormal state of the internal clock signal intCLK is detected, the impedance code is reset to the initial value. However, depending on conditions such as the on-resistance of the external driver circuit 6 that supplies the external clock signal K and the power supply voltage range, the pulse of the external clock signal K can be propagated to the comparator 50 to generate the internal clock signal intCLK. It may be difficult to find an initial value of such an impedance code. Therefore, in the semiconductor device 3, in order to generate the internal clock signal intCLK more reliably in the initial state where impedance matching is not performed, the input terminal K is connected for a certain period after the abnormal state of the clock signal is detected. Put the node in a high impedance state. Specifically, as illustrated in FIG. 10, the semiconductor device 3 includes an impedance code control unit 210 between the impedance code holding register 205 and the ODT circuit 10.

  The impedance code control unit 210 includes a counter 2101 and two AND circuits 2102, 2103. The counter 2101 counts the internal clock signal intCLK, and switches the signal level of the output signal hzodt from low level to high level when the count value reaches a predetermined number of cycles. The count value can be reset by a reset signal rsdot. The predetermined number of cycles is not particularly limited, but is set to 1024 cycles, for example.

  The output signal hzodt is input to the AND circuits 2102 and 2103 together with the code value held in the impedance code holding register 205. The output of the AND circuit 2102 is input to the gates of the PMOS transistors MP0 to MP7 as the P-side impedance pcode, and the output of the AND circuit 2103 is input to the gates of the NMOS transistors MN0 to MN7 as the N-side impedance ncode. Therefore, when the output signal hzodt is at a low level, the P-side impedance code pcode and the N-side impedance code ncode are “8′00000000” regardless of the code value held in the impedance code holding register 205. As a result, the PMOS transistors MP0 to MP7 on the power supply VDDQ side of the ODT circuit 10 are turned off, and the NMOS transistors MP0 to MP7 on the ground GND side of the ODT circuit 10 are turned off, so that the node K is in a high impedance state. If the external clock signal K is supplied to the input terminal K in this state, the external clock signal K is propagated to the comparison circuit 50 with the signal level output from the external driver circuit 6. For example, when the high level of the external clock signal K output from the external driver circuit 6 is VDDQ and the low level is the GND level, the waveform quality is deteriorated, but the high level is a potential similar to the VDDQ potential. A signal having a low level that is approximately the same as the GND potential is input to the comparison circuit 50. Thereby, if the reference voltage VREF is set to 1/2 VDDQ, the magnitude relation of the input of the comparison circuit 50 is alternately switched, so that the internal clock signal intCLK in which the high level and the low level are alternately switched can be generated. .

  On the other hand, when the output signal hzodt is at a high level, the values of the impedance code holding register 205 are supplied to the ODT circuit 10 as the P-side impedance code pcode and the N-side impedance code ncode.

  FIG. 11 is a flowchart illustrating an example of a flow of an impedance adjustment method for the ODT circuit 10 in the semiconductor device 3.

  First, the power supply voltages VDDI and VDDQ are input to the semiconductor device 1 (S201). When the reset signal rst is validated after the power is turned on, the impedance code generation circuit 202 sets an initial value “8′b10000000” in the control signals pre_pcode and pre_ncode (S202). Further, in response to the reset signal rst, the impedance code control unit 210 changes the signal level of the output signal hzodt to a low level, thereby forcibly turning off the MOS transistors MP0 to MP7 and MN0 to MN7 of the ODT circuit 10. K enters a high impedance state (the ODT circuit 10 is forcibly turned off) (S203). Thereafter, when the external clock signal K is input and the internal clock signal intCLK is generated, the impedance code generation circuit 202 starts updating the control signals pre_pcode and pre_ncode (S204).

  Meanwhile, the counter 2101 in the impedance code control unit 210 continues counting until the count value reaches 1024 cycles (S205). When the count value of the counter 2101 reaches “1024”, the impedance code control unit 210 switches the signal level of the output signal hzodt from the low level to the high level, thereby releasing the forced off state of the ODT circuit 10 (S206). . Thereafter, the control signals pre_pcode and pre_pcode are continuously updated by the impedance code generation circuit 202 (S207). Meanwhile, the counter 203 continues to count the internal clock signal intCLK until the count value becomes N (N is an integer of 1 or more) times 256 cycles (S208). When the count value of the counter 203 reaches N (N is an integer of 1 or more) times 256 cycles, the impedance code generation circuit 202 updates the values of the control signals pcode and ncode to the values of pre_pcode and pre_ncode, respectively. (S209). Meanwhile, the clock signal abnormality detection circuit 204 monitors whether or not the internal clock signal intCLK is normally output (S210). When the internal clock signal intCLK is normally output, the process proceeds to step 207, and updating of pre_pcode and pre_ncode is continued. On the other hand, when the abnormality of the internal clock signal intCLK is detected, the clock signal abnormality detection circuit 204 switches the detection signal stopc from the low level to the high level (S211). As a result, the impedance code generation circuit 202 and the like are reset, and the process proceeds to step 202.

  FIG. 12 is a timing chart showing an example of a voltage change at each node in the semiconductor device 3.

  First, when the power supply voltage VDDI is turned on at time t120, the reset signal rstott becomes high level as the reset signal rst from the reset circuit 40 becomes high level, and the impedance code generation circuit 202 and the impedance code control unit 210 Etc. are reset. As a result, the output signal hzodt of the counter 2101 becomes a low level, and the P-side impedance code pcode [7: 0] and the N-side impedance code ncode [7: 0] become “8'00000000”. Further, the impedance code generation circuit 202 sets an initial value “8′10000000” as the control signals pre_pcode and pre_ncode in response to the reset signal rsdot.

  Thereafter, at time t121, the power supply voltage VDDQ is supplied and the reference voltage VREF is supplied. While the power supply voltage VDDQ is rising, ground noise occurs for some reason, and when ground noise is superimposed on a node connected to the input terminal K, as described above, the two input terminals of the comparator 50 The magnitude relationship of the voltages is inverted, and an abnormal internal clock signal intCLK is generated. Since the abnormal internal clock signal intCLK is supplied as an operation clock of the impedance code generation circuit 202, the impedance code generation circuit 202 starts updating the impedance code. However, according to the semiconductor device 3, the code values of the control signals pre_pcode and pre_ncode are updated. However, since the ODT circuit 10 is forcibly turned off by the impedance code control unit 210, the resistance value of the ODT circuit 10 is Not updated, node K remains in a high impedance state.

  Thereafter, when the output of the abnormal internal clock signal intCLK is stopped at time t122, the clock signal abnormality detection circuit 204 starts timing, and at time t123 when td time has elapsed from time t122, the clock signal abnormality detection circuit 204 detects the detection signal. Switch stopc from low level to high level. As a result, the reset signal rssdot becomes high level, the impedance code generation circuit 202 and the like are reset, and the initial value “8′10000000” is reset as the control signals pre_pcode and pre_ncode [7: 0].

  Thereafter, when the external driver circuit 6 is activated and the external clock signal K is supplied, the amplitude of the external clock signal K input to the comparison circuit 50 becomes approximately VDDQ. This is because the node K is in a high impedance state because the ODT circuit 10 is in a forced off state, and the external clock signal K is propagated at the signal level output from the external driver circuit 6. When the reset state is released at time t124, the counter 2101 in the impedance code control unit 210 starts counting, and at time t125 when the count value becomes “1024 cycles”, the output signal hzodt of the counter 2101 is high. Become a level. As a result, the impedance code held in the impedance code holding register 206 is supplied to the ODT circuit 10 as the P-side impedance code pcode and the N-side impedance code ncode.

  As described above, according to the semiconductor device 3 according to the third embodiment, until the internal clock signal intCLK is input a predetermined number of times (1024 cycles in the above example), the ODT circuit 10 is forcibly turned off and the node K is set in a high impedance state. Therefore, the external clock signal K is propagated to the comparator 50 with a sufficient amplitude. Thereby, the comparator 50 can output the internal clock signal intCLK, and the impedance code generation unit 202 using the internal clock signal intCLK as an operation clock can generate a target impedance code. Therefore, as with the semiconductor device 1, a more stable ODT circuit can be realized.

<< Embodiment 4 >>
FIG. 13 illustrates a block diagram of a semiconductor device to which the ODT circuit with variable impedance according to the fourth embodiment is applied. In the semiconductor device 4 shown in the figure, the same components as those of the semiconductor devices 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The semiconductor device 4 is, for example, a QDR (Quad Data Rate) SRAM (Double Data Rate), the data input terminal D and the data output terminal DQ are separated, and data is read from and written to the memory array (MRY_ARR) 613 at the same time. It is possible.

  The semiconductor device 4 has input address terminals SA, read terminals XR, write terminals XW, byte write terminals XBW, data input terminals D, input terminals K, input terminals VREF, and input terminals ZQ as input terminals, and data as output terminals. An output terminal DQ is provided. Although not shown, the semiconductor device 4 is similar to the semiconductor devices 1 to 3 in that the power supply terminal VDDQ to which the power supply voltage VDDQ is supplied, the power supply terminal VDDI to which the power supply voltage VDDI is supplied, and the ground terminal GND to which the ground voltage is supplied. Etc. The input address terminal SA receives an address signal for designating a data write destination and a read destination in the memory array. The lead terminal XR receives a read signal that instructs reading. A write signal for instructing writing is input to the write terminal XW. The byte write terminal XB receives a byte write signal instructing to write a specific byte of the input data to the memory array. Note that the read signal, the write signal, and the byte write signal are active-low signals. Data to be written is input to the data input terminal D. The input terminal K, the input terminal VREF, and the input terminal ZQ are the same as those of the semiconductor devices 1 to 3.

  Like the external clock signal K, the input data input to the data input terminal D is an HSTL level signal and has a relatively small amplitude. Therefore, similarly to the external clock signal K, the comparator 50_2 compares the voltage level of the external clock signal K with the voltage level of the reference voltage VREF, and outputs the comparison result, so that input data with a small amplitude can be obtained. Data can be converted into data having a large amplitude (VDDQ-GND). The comparison result is input to the data register 62. The data register 62 holds the comparison result of the comparator 50_2 in synchronization with the internal clock signal intCLK output from the comparator 50_1. Similarly, the backlight signal XBW, the write signal XW, the read signal XR, and the address signal SA are signals having a small amplitude, and the result of comparison with the reference voltage VREF by the comparators 50_3, 50_4, 50_5, and 50_6 is an internal clock signal. In synchronization with intCLK, they are taken into the control registers 63, 64, 65 and the address register 66, respectively.

  Since the input data input to the data input terminal D is likely to be a signal having a frequency of 500 MHz or higher, like the external clock signal K, the ODT circuit 10_2 is connected to the data input terminal D as a termination circuit. The The circuit configuration of the ODT circuits 10_1 and 10_2 is the same as that of the above-described ODT circuit 10, and the impedance is adjusted by the P-side impedance code pcode and the N-side impedance code ncode from the control unit 20.

  The core logic circuit 61 includes, for example, a memory array 613 for storing data, a memory control unit for controlling writing and reading of data to and from the memory array 613, and a clock signal C_CLK based on the internal clock signal intCLK. And a PLL circuit (PLL) 615 to be generated. The memory control unit includes, for example, an address decoder (ADD_DEC) 610, a read / write control unit (R / W_CNT) 611, a write data bus (W_DATA_BUS) 612, and a read data bus (R_DATA_BUS) 614. The address decoder 610 generates an X address (X_ADD) and a Y address (Y_ADD) based on the address information held in the address register 66 and outputs the X address (X_ADD) to the memory array 613. The read / write control unit 611 issues a read command MR_CNT and a write command MW_CNT based on the information held in the control registers 63 to 65. The write data bus 612 outputs the write data W_DATA stored in the data register 62 to the memory array 613 according to the write command MW_CNT issued from the read / write control unit 611. The read data bus 614 outputs the read data R_DATA read from the memory array 613 to the output buffer 67 in response to the read command MR_CNT issued from the read / write control unit 611. The output buffer 67 outputs read data R_DATA from the data output terminal DQ in synchronization with the clock signal C_CLK output from the PLL circuit 615.

  FIG. 14 illustrates a detailed block diagram around the input terminal K. The connection relationship among the control unit 20, the ODT circuit 10, the reference voltage generation circuit 30, the comparator 50_1, and the reset circuit 40 is the same as that of the semiconductor device 1 of the first embodiment. The difference is that the output signal stopc of the clock signal abnormality detection circuit 204 in the control unit 20 is input as a reset signal of the core logic circuit 61. That is, the core logic circuit 61 including the memory array 613 can be reset not only by the reset signal rst from the reset circuit 40 that performs power supply monitoring but also by the output signal stopc of the clock signal abnormality detection circuit 204. According to this, when the internal clock signal intCLK becomes abnormal, not only the impedance of the ODT circuit 10 but also the core logic circuit 61 can be reset. That is, according to the semiconductor device 4, the core logic circuit 61 can be reset by stopping the external clock signal K (fixing the signal level of the external clock signal K to a high level or a low level). There is no need to turn on the power again to reset the core logic circuit 61 or to provide a reset dedicated terminal and input a reset signal.

  As described above, according to the fourth embodiment, as in the first embodiment, even if the internal clock signal CLK is fixed at a low level or a high level, the impedance code is reset when the state continues for a certain period. Therefore, it is possible to escape from the abnormal state of the impedance of the ODT circuit, and it is possible to realize a more stable ODT circuit. Further, by using the signal stopc related to the abnormality detection of the internal clock signal intCLK as a reset signal of the core logic circuit 61, it is possible to turn on the power again or to provide a reset dedicated terminal and not input the reset signal. The core logic circuit 61 can be reset.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the first embodiment, as an initial value of the control signals pre_pcode, pre_ncode, P-side impedance code pcode, and N-side impedance code ncode, an intermediate value within a range in which the impedance of the ODT circuit 10 can be set as the impedance of the ODT circuit 10 The code value “8′b10000000” is shown as an example, but the present invention is not limited to this. For example, as in the third embodiment, the code value “8′b00000000” at which the node K to which the input terminal K is connected is in a high impedance state may be used. According to this, it is possible to shift from the state in which the internal clock signal intCLK is stopped to the state in which the internal clock signal intCLK is output more reliably.

  Moreover, although the case where the control unit 20 is applied as a circuit for adjusting the impedance of the ODT circuits 10_1 and 10_2 in the semiconductor device 4 in the fourth embodiment is illustrated, it is not limited thereto. For example, the control units 21 and 22 can be applied instead of the control unit 20.

1 to 4 Semiconductor device 6 External driver circuit RQ External resistor ZQ External terminal, node K input terminal, node, external clock signal VREF input terminal, reference voltage ZREF reference voltage, node VDDQ, VDDI power supply voltage GND ground voltage 10 ODT circuit ( ODT)
MP0 to MP7 PMOS transistor MN0 to MN7 NMOS transistor RP0 to RP7 Pull-up resistance of node K RN0 to RN7 Pull-down resistance of node K pcode P-side impedance code ncode N-side impedance code 20 Control unit 201 Impedance detection circuit (REP)
202 Impedance code generation circuit (IMPC_GEN)
203 Counter (CTR)
204 Clock signal abnormality detection circuit 205 Impedance code holding register 2051, 2052 Flip-flop circuit 206 OR circuit p_dn, n_up Comparison result pre_pcode, pre_ncode Control signal strb Output of counter 203 intCLK Internal clock signal rst Reset signal stopc Output of clock signal abnormality detection circuit rstdot reset signal 30 reference voltage generation circuit 40 reset circuit (RESET)
50 Comparator (CMP)
60 Core logic circuit (CIR)
2011, 2012 replica circuit 2013 level conversion circuit with inversion function 2016 level conversion circuit 2014 comparator 2015 comparator ZN node MPR0 to MPR7, MNPR0 to MNPR7 PMOS transistor MNNR0 to MNNR7 NMOS transistor RPR0 to RPR7 pull-up resistor RNPR0 to RNPR7 of node ZQ Pull-up resistance of node ZN RNNR0 to RNNR7 Pull-down resistance of node ZN 2040 Low level detection unit 2041 High level detection unit 100 NAND circuit 101 Delay circuit t60 to t64 Timing (time)
21 control unit 214 clock signal abnormality detection circuit 2140 low level detection unit 2141 high level detection unit 101_A to 101_F delay circuit 102, 103 selector SEL selection signal SEL10L output of delay circuit 101_C SEL00L output of delay circuit 101_B SEL01L output of delay circuit 101_A SEL10H Output of delay circuit 101_F SEL00H Output of delay circuit 101_E SEL01H Output of delay circuit 101_D 22 Control unit 210 Impedance code control unit 2101 Counter 2102, 2103 AND circuit SA input address terminal XR read terminal XW write terminal XBW byte write terminal D Data input terminal K input terminal VREF input terminal ZQ external terminal DQ data output terminal 10_1, 10_2 ODT circuit 50 1～50_6 comparator 62 data register 63-65 Control Register 66 address register 67 output buffer 61 core logic circuit 610 an address decoder (ADD_DEC)
611 Read / write control unit (R / W_CNT)
612 Write data bus (W_DATA_BUS)
614 Read data bus (R_DATA_BUS)
615 PLL circuit (PLL)
C_CLK Clock signal 8 Semiconductor device 80 ODT circuit (ODT)
81 Control unit (CNT)
82 Comparator (CMP)
83 Internal circuit (CIR)
rst_p Power-on reset signal

Claims (9)

An internal impedance is configured to be changeable, and a termination circuit for matching with an impedance of an external transmission line that propagates an input signal;
A clock signal generator for generating a clock signal according to the signal level of the input signal input via the termination circuit;
On the basis of the clock signal, a semiconductor device which have a, and a control unit for adjusting the impedance of the termination circuit,
The control unit performs processing for adjusting the impedance of the termination circuit so as to achieve a target impedance in synchronization with the clock signal, and determines that the clock signal is abnormal. Change the impedance of the
The input signal is an external clock signal,
The clock signal generation unit includes a comparison circuit that compares a signal level of the external clock signal with a signal level of a reference voltage,
The comparison circuit outputs a comparison result as the clock signal,
The predetermined impedance is such that a high level voltage of the external clock signal input to the clock signal generation unit is larger than the reference voltage, and a low level voltage of the external clock signal is smaller than the reference voltage. Semiconductor device with high impedance . The semiconductor device according to claim 1, wherein the control unit determines that the clock signal is abnormal when the clock signal becomes high level or low level for a predetermined period longer than an expected high level period or low level period. apparatus. The semiconductor device according to claim 2, wherein the control unit is configured to change the predetermined period . The initial value of the impedance of the termination circuit is the predetermined impedance,
The control unit includes an impedance adjustment unit that adjusts an impedance of the termination circuit;
A monitoring unit that monitors the clock signal and outputs a reset signal when it is determined that the clock signal is abnormal,
The impedance adjustment unit adjusts the impedance of the termination circuit to be a target impedance in synchronization with the clock signal, and when the reset signal is output, the impedance of the termination circuit is set to the initial value. The semiconductor device according to claim 1, which is reset . The semiconductor device according to claim 1, wherein the predetermined impedance is determined based on an intermediate value in a range that can be set as the impedance of the termination circuit . An internal circuit that operates based on the clock signal;
The semiconductor device according to claim 4, wherein the internal circuit is configured to be initialized by the reset signal . The internal circuit includes a memory unit having a storage area for storing data;
The semiconductor device according to claim 6, further comprising: a memory control unit for writing and reading data to and from the memory unit in synchronization with a signal based on the clock signal . The semiconductor device according to claim 1, wherein the predetermined impedance is determined when the termination circuit enters a high impedance state . The control unit includes an impedance adjustment unit that adjusts an impedance of the termination circuit;
A monitoring unit that monitors the clock signal and outputs a reset signal when it is determined that the clock signal is abnormal,
The impedance adjustment unit, when the reset signal is output, sets the termination circuit to a high impedance state, performs a process of calculating the target impedance value in synchronization with the clock signal, and elapses of a predetermined time. Then, the semiconductor device according to claim 1, wherein the impedance of the termination circuit is updated to the calculated value .

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