JP5732948B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5732948B2 JP5732948B2 JP2011064566A JP2011064566A JP5732948B2 JP 5732948 B2 JP5732948 B2 JP 5732948B2 JP 2011064566 A JP2011064566 A JP 2011064566A JP 2011064566 A JP2011064566 A JP 2011064566A JP 5732948 B2 JP5732948 B2 JP 5732948B2
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- 239000004065 semiconductor Substances 0.000 title claims description 119
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 229920005989 resin Polymers 0.000 claims description 126
- 239000011347 resin Substances 0.000 claims description 126
- 239000004020 conductor Substances 0.000 claims description 117
- 239000000758 substrate Substances 0.000 claims description 74
- 239000002184 metal Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 19
- 238000007789 sealing Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 22
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
付記1:基板上に半導体素子を搭載する工程と、前記基板上に、孔を備える導電体を含む樹脂シートを貼り付けることにより、前記導電体が前記半導体素子を囲むように、前記半導体素子を樹脂を用い封止する工程と、を含むことを特徴とする半導体装置の製造方法。
付記2:前記樹脂および前記基板を切断する工程を含み、前記基板に前記樹脂シートを貼り付ける前において、前記導電体には凹凸が形成されており、前記半導体素子を前記樹脂を用い封止する工程は、前記樹脂および前記基板が切断される領域に前記導電体の凹部が配置されるように、前記樹脂シートを貼り付ける工程を含むことを特徴とする付記1記載の半導体装置の製造方法。
付記3:前記半導体素子を前記樹脂を用い封止する工程は、前記樹脂シートを、前記基板にローラを用い加圧する工程を含むことを特徴とする請求項1または2記載の半導体装置の製造方法。
付記4:前記半導体素子を前記樹脂を用い封止する工程は、前記基板上に形成され接地された接地体に、前記導電体を、電気的に接触させる工程を含むことを特徴とする付記1から3のいずれか一項に記載の半導体装置の製造方法。
付記5:前記導電体は、金属線が網の目状に形成されていることを特徴とする付記1から4のいずれか一項記載の半導体装置の製造方法。
付記6:前記接地体は、前記半導体素子の上面であることを特徴とする付記4記載の半導体装置の製造方法。
付記7:前記接地体は、前記基板上に形成された金属ポストであることを特徴とする付記4記載の半導体装置の製造方法。
付記8:前記基板に前記樹脂シートを貼り付ける前において、前記導電体は、前記樹脂シートに含まれ、かつ平坦であることを特徴とする付記1記載の半導体装置の製造方法。
付記9:前記基板に前記樹脂シートを貼り付ける前において、前記導電体は、前記樹脂シートの前記基板側の表面に設けられていることを特徴とする付記1記載の半導体装置の製造方法。
付記10:基板と、前記基板上に搭載された半導体素子と、前記基板上に設けられ前記半導体素子を封止する樹脂と、前記樹脂に含まれ、前記半導体素子を囲み、前記樹脂の端面での位置が前記半導体素子上の位置より低く、孔を備える導電体と、を具備することを特徴とする半導体装置。
20 半導体素子
29 金属膜
30 受動部品
34 ポスト
40 導電体
41 凸部
43 凹部
50 樹脂シート
55 樹脂
60 ローラ
Claims (5)
- 基板上に半導体素子を搭載する工程と、
前記基板上に、孔を備える導電体と、前記導電体の上に位置する樹脂シートとを、前記導電体が前記半導体素子に対向するように配置する工程と、
前記樹脂シートを加熱して、前記樹脂シートの樹脂が前記基板と前記導電体との間に位置するように前記孔を介して流れ込み、前記樹脂シートを前記基板に貼り付けることにより、前記導電体が前記半導体素子を囲むように、前記半導体素子を前記樹脂を用い封止する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記樹脂および前記基板を切断する工程を含み、
前記基板に前記樹脂シートを貼り付ける前において、前記導電体には凹凸が形成されており、
前記半導体素子を前記樹脂を用い封止する工程は、前記樹脂および前記基板が切断される領域に前記導電体の凹部が配置されるように、前記樹脂シートを貼り付ける工程を含むことを特徴とする請求項1記載の半導体装置の製造方法。 - 前記半導体素子を前記樹脂を用い封止する工程は、前記樹脂シートを、前記基板にローラを用い加圧する工程を含むことを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記半導体素子を前記樹脂を用い封止する工程は、前記基板上に形成され接地された接地体に、前記導電体を、電気的に接触させる工程を含むことを特徴とする請求項1から3のいずれか一項に記載の半導体装置の製造方法。
- 前記導電体は、金属線が網の目状に形成されていることを特徴とする請求項1から4のいずれか一項記載の半導体装置の製造方法。
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JP2011064566A JP5732948B2 (ja) | 2011-03-23 | 2011-03-23 | 半導体装置の製造方法 |
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JP2011064566A JP5732948B2 (ja) | 2011-03-23 | 2011-03-23 | 半導体装置の製造方法 |
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JP2012204368A JP2012204368A (ja) | 2012-10-22 |
JP5732948B2 true JP5732948B2 (ja) | 2015-06-10 |
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JP3190702B2 (ja) * | 1990-10-08 | 2001-07-23 | 株式会社東芝 | 半導体装置の製造方法 |
JP2000223647A (ja) * | 1999-02-03 | 2000-08-11 | Murata Mfg Co Ltd | 高周波モジュールの製造方法 |
JP3912324B2 (ja) * | 2003-05-15 | 2007-05-09 | エプソントヨコム株式会社 | 弾性表面波デバイスの製造方法 |
FR2940588B1 (fr) * | 2008-12-19 | 2011-01-07 | St Microelectronics Grenoble | Ensemble multicomposant blinde a montage en surface |
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