JP5715593B2 - Semiconductor light emitting device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  As a semiconductor light emitting element such as an LED (Light Emitting Diode), for example, there is a structure in which a crystal layer formed on a sapphire substrate is bonded to a conductive substrate and the sapphire substrate is removed. In this structure, in order to improve the light extraction efficiency, the surface of the crystal layer exposed by removing the sapphire substrate is subjected to uneven processing. In addition, there is a structure in which electrodes are not formed on the surface of the crystal layer serving as a light extraction surface, and a p-side electrode and an n-side electrode are formed on the crystal surface opposite to the surface from which the sapphire substrate is removed. In such a semiconductor light emitting device, there is a demand for improving heat dissipation and further improving light extraction efficiency.

A. Laubsch, M. Sabathil, J. Baur, M. Peter, and B. Hahn, IEEE Transactions on electron devices, vol. 57, no. 1, p79-87 (2010)

  Embodiments of the present invention provide a semiconductor light-emitting element that can improve heat extraction performance and improve light extraction efficiency.

The semiconductor light emitting device according to the embodiment includes a laminated structure, a first electrode, a second electrode, a dielectric portion, and a pad electrode. The stacked structure includes a first semiconductor layer including a nitride semiconductor, a second semiconductor layer including a nitride semiconductor, and a nitride semiconductor provided between the first semiconductor layer and the second semiconductor layer. A light emitting layer. The stacked structure has a recess that reaches the first semiconductor layer from the surface on the second semiconductor layer side. The first electrode is a contact portion in contact with the first semiconductor layer in the recess , the contact portion including a first region and a second region, and the second electrode electrically connected to the second region . A via portion extending from the region toward the opposite side of the stacked structure from the first semiconductor layer. The second electrode is in contact with the second semiconductor layer and reflects light. The dielectric portion has a portion embedded in the recess. The dielectric portion electrically insulates between the first electrode and the second electrode and between the first semiconductor layer and the second electrode. The pad electrode is electrically connected to the via portion of the first electrode. The pad electrode is located on the opposite side of the stacked structure from the first semiconductor layer. The second electrode overlaps the first region when viewed in the stacking direction from the first semiconductor layer toward the second semiconductor layer. A part of the dielectric part is provided between the first region and the second electrode, and overlaps the first region when viewed in the stacking direction. Area of the region of the second electrode overlapping with the light emitting layer when viewed in front miracle layer direction is larger than the contact area between the first semiconductor layer of the contact portion.

It is a typical sectional view showing a semiconductor light emitting element. It is a typical top view showing a semiconductor light emitting element. It is the elements on larger scale which show an uneven | corrugated | grooved part. It is a typical sectional view showing a semiconductor light emitting element of a reference example. It is typical sectional drawing which shows the manufacturing method of a semiconductor light-emitting device. It is typical sectional drawing which shows the manufacturing method of a semiconductor light-emitting device. It is typical sectional drawing which shows the manufacturing method of a semiconductor light-emitting device. It is a typical sectional view showing a semiconductor light emitting element. It is a typical top view showing a semiconductor light emitting element. It is a typical top view showing a semiconductor light emitting element. It is typical sectional drawing which shows a semiconductor light-emitting device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment.
FIG. 2 is a schematic plan view illustrating the configuration of the semiconductor light emitting element according to the first embodiment.
Here, FIG. 1 is a schematic cross-sectional view taken along the line AA ′ of FIG.

  As shown in FIG. 1, the semiconductor light emitting device 110 according to the first embodiment includes a multilayer structure 100, a first electrode 50, a second electrode 60, and a first dielectric part 40.

  The stacked structure 100 includes a first semiconductor layer 10 of a first conductivity type, a second semiconductor layer 20 of a second conductivity type facing a part of the first semiconductor layer 10, and a part of the first semiconductor layer 10. And a light emitting layer 30 provided between the second semiconductor layer 20.

  The first conductivity type is, for example, n-type. The second conductivity type is, for example, a p-type. The first conductivity type may be p-type, and the second conductivity type may be n-type. In the present embodiment, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  The laminated structure 100 includes a first main surface 100a on the first semiconductor layer 10 side and a second main surface 100b on the second semiconductor layer 20 side. A part of the first semiconductor layer 10 is exposed to the second main surface 100b side. This part is an exposed portion 10 e of the first semiconductor layer 10.

  The first electrode 50 has a contact portion 51 that contacts the first semiconductor layer 10 at the exposed portion 10e. The second electrode 60 is in contact with the second semiconductor layer 20 at the second major surface 100b.

The second electrode 60 has a first portion 61 in contact with the second semiconductor layer 20 on the second main surface 100b, and is electrically connected to the first portion, and a stacking direction from the first semiconductor layer 10 toward the second semiconductor layer 20 A second portion 62 having a portion overlapping the contact portion 51 when viewed.
Here, in the present embodiment, the direction connecting the first semiconductor layer 10 and the second semiconductor layer 20 is the Z-axis direction, and one of the directions orthogonal to the Z-axis direction is the X-axis direction, the Z-axis direction, and the X-axis. A direction orthogonal to the direction is referred to as a Y-axis direction. The stacking direction is the Z-axis direction.

The first dielectric part 40 is provided between the contact part 51 and the second part 62.
That is, the second electrode 60 is electrically insulated via the first electrode 50 and the first dielectric part 40. In the embodiment, the first dielectric part 40 is provided only around the contact part 51 of the first electrode 50. Therefore, on the second main surface 100b side of the stacked structure 100, the first portion 61 of the second electrode 60 is in contact with the second semiconductor layer 20 with a relatively large area where the first dielectric portion 40 is not provided. Will do. Therefore, the heat generated in the laminated structure 100 is efficiently released from the second electrode 60 to the outside.

  Next, a specific example of the semiconductor light emitting device 110 according to this embodiment will be described.

  In the semiconductor light emitting device 110 according to this embodiment, the first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 included in the multilayer structure 100 are, for example, nitride semiconductors. The first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 are stacked on a growth substrate such as sapphire by using, for example, a metal organic chemical vapor deposition method.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  The laminated structure 100 is provided with a recess 100t that reaches the first semiconductor layer 10 from the second major surface 100b. An exposed portion 10e of the first semiconductor layer 10 is included in the bottom surface of the recess 100t. The contact portion 51 of the first electrode 50 is in contact with the first semiconductor layer 10 at the exposed portion 10 e to obtain conduction with the first semiconductor layer 10.

  For the contact portion 51, a material capable of obtaining a good contact with the first semiconductor layer 10 is used. As the contact portion 51, for example, a laminated film of Al / Ni / Au is used. The laminated film is laminated in the order of Al / Ni / Au from the contact surface 50c side, and is formed with a thickness of, for example, 300 nanometers (nm).

  The first electrode 50 includes a lead portion 53 that is drawn to the outside of the multilayer structure 100. The lead portion 53 is electrically connected to the contact portion 51 and is provided so as to extend from the contact portion 51 to the outside of the laminated structure 100 along the XY plane. The drawer part 53 may be formed integrally with the contact part 51.

  The side surface of the laminated structure 100 is covered with the second dielectric portion 45. A part of the lead portion 53 is exposed from the opening of the second dielectric portion 45 outside the multilayer structure 100. A pad electrode 55 is provided on the exposed portion.

  A wiring member such as a bonding wire (not shown) is connected to the pad electrode 55 so that the outside and the first semiconductor layer 10 can be electrically connected.

  The first portion 61 of the second electrode 60 is provided in contact with the second semiconductor layer 20 along the second major surface 100b. A material capable of efficiently reflecting the emitted light emitted from the light emitting layer 30 is used for the first portion 61. As the first portion 61, for example, a laminated film of Ag / Pt is used. The laminated film is laminated in the order of Ag / Pt from the second main surface 100b side, and is formed with a thickness of, for example, 200 nm.

  The semiconductor light emitting device 110 according to the embodiment includes a support substrate 70 that is electrically connected to the second portion 61 of the second electrode 60. The second portion 61 of the second electrode 60 includes, for example, a bonding metal part. The entire second portion 61 may be a bonding metal portion.

  For the bonding metal part, a material capable of obtaining a good connection with the support substrate 70 described later is used. For example, a Ti / Au laminated film is used as the bonding metal portion. The laminated film is laminated in the order of Ti / Au from the second main surface 100b side, and is formed with a thickness of, for example, 800 nm.

  The support substrate 70 is bonded to the bonding metal portion. The support substrate 70 is made of at least a conductive material. The material of the support substrate 70 is not particularly limited. For example, a semiconductor substrate such as Si or Ge, a metal plate such as CuW or Cu, or a thick film plating layer is used. Further, the entire substrate does not need to have conductivity, and may be a resin having metal wiring.

In the embodiment, Ge is used as an example of the support substrate 70. The support substrate 70 is bonded to the bonding metal portion via, for example, solder (not shown) made of an AuSu alloy.
A back electrode 85 is provided on the support substrate 70. That is, the second semiconductor layer 20 is electrically connected to the second electrode 60, the support substrate 70, and the back electrode 85. As a result, by mounting the semiconductor light emitting element 110 on a mounting substrate (not shown) or the like, electrical connection between the conductive portion provided on the mounting substrate or the like and the second semiconductor layer 20 can be obtained.

  The support substrate 70 has an outer edge 70 a of the stacked structure 100 as viewed in the Z-axis direction. The lead portion 53 of the first electrode 50 is drawn from the contact portion 51 to the edge portion 70a.

  In the semiconductor light emitting device 110, the second electrode 60 is a p-side electrode. Therefore, electrical connection between the p-side electrode (second electrode 60) and the outside is obtained by the support substrate 70 and the back surface electrode 85 that are electrically connected to the second electrode 60.

  In the semiconductor light emitting device 110, the first electrode 50 is an n-side electrode. Therefore, by connecting a wiring member such as a bonding wire to the pad electrode 55, electrical conduction between the n-side electrode (first electrode 50) and the outside is obtained.

  In the semiconductor light emitting device 110, the uneven portion 12 p may be provided on the first main surface 100 a (the surface of the first semiconductor layer 10) of the multilayer structure 100. The concavo-convex portion 12p is configured by a plurality of protrusions provided in the plane of the first main surface 100a.

FIG. 3 is a partially enlarged view showing the uneven portion.
Fig.3 (a) is typical sectional drawing of an uneven | corrugated | grooved part. FIG. 3B is a schematic plan view of one convex portion.
As shown in FIG. 3A, the uneven portion 12p is provided with a plurality of protrusions. The maximum width ΔW along the X-axis direction of the protrusion is longer than the peak wavelength in the first semiconductor layer 10 of the emitted light emitted from the light emitting layer 30.

  Thereby, the reflection of the emitted light at the interface between the first semiconductor layer 10 and the outside can be regarded as Lambertian reflection, and the effect of improving the light extraction efficiency becomes higher. Here, the peak wavelength is the wavelength of light having the highest intensity among the emitted light emitted from the light emitting layer 30. The peak wavelength is a wavelength corresponding to the peak value of the spectrum distribution of the emitted light. In the case of a spectrum having two or more local maximum values that are not noise levels, the wavelength of either peak value may be selected.

  As shown in FIG. 3B, for example, when a nitride semiconductor is used as the first semiconductor layer 10, when the planar shape of the protrusion when viewed in the Z-axis direction is substantially hexagonal, the maximum width ΔW Is the width between the diagonal vertices of the hexagon.

  As an example, when the first semiconductor layer 10 is gallium nitride and the peak wavelength of the emitted light of the light emitting layer 30 is 390 nm, the peak wavelength of the emitted light in the first semiconductor layer 10 is 155 nm. In this case, the effect of improving the light extraction efficiency can be obtained until the maximum width ΔW of the uneven portion 12p exceeds 155 nm and reaches about 3 micrometers (μm). From this, the maximum width ΔW of the concavo-convex portion 12p is preferably at least twice the peak wavelength of the emitted light, and more preferably at least 10 times.

  In such a semiconductor light emitting device 110, more light is emitted from the light emitting layer 30 to the outside from the first main surface 100 a side than the second main surface 100 b side of the multilayer structure 100. That is, the first main surface 100a is a light extraction surface.

  In the semiconductor light emitting device 110, neither the n-side electrode (first electrode 50) nor the p-side electrode (second electrode 60) is disposed on the first main surface 100 a side of the multilayer structure 100. Therefore, the light extraction efficiency on the first main surface 100a side is improved as compared with the case where the electrode is arranged on the first main surface 100a side. Further, the p-side electrode (second electrode 60) immediately below the light emitting layer 30, which is a main heat source, is connected to a metal layer having a high thermal conductivity and the support substrate 70. When, for example, a heat sink is connected to the support substrate 70, the thermal resistance can be lowered and good heat dissipation can be obtained. In addition to this, the second portion 62 of the p-side electrode (second electrode 60) of the semiconductor light emitting device 110 is provided to extend to the second main surface 100 b side of the multilayer structure 100. Thereby, the spread of heat becomes favorable and the thermal resistance of the entire semiconductor light emitting device 110 can be further reduced.

FIG. 4 is a schematic cross-sectional view illustrating the structure of a semiconductor light emitting element according to a reference example.
As shown in FIG. 4, in the semiconductor light emitting device 190 according to the reference example, the first electrode 50 includes a contact portion 51 and a third portion 54. The third portion 54 is electrically connected to the contact portion 51 and is provided along the second main surface 100b. A third dielectric portion 41 is provided between the third portion and the first portion 61 of the second electrode 60 along the Z-axis direction.

  The second electrode 60 includes a first portion 61 and a lead portion 63. The lead portion 63 is electrically connected to the first portion 61 and is drawn from the first portion 61 to the outside of the multilayer structure 100. On the outside of the laminated structure 100, a part of the lead part 63 is exposed from the opening of the second dielectric part 45. A pad electrode 65 is provided on the exposed portion.

  In such a semiconductor light emitting device 190, the third dielectric portion 41 is provided between the first portion 61 of the second electrode 60 and the third portion 54 of the first electrode 50. That is, the third dielectric portion 41 is formed on the second main surface 100 b side of the multilayer structure 100 so as to cover the entire portion other than the contact portion 51 of the first electrode 50. Therefore, the third dielectric portion 41 covers the portion immediately below the light emitting layer 30 that is a main heat source. Since the semiconductor light emitting device 190 is connected to a heat sink or the like via the third dielectric portion 41 having a lower thermal conductivity than metal, the thermal resistance becomes high and sufficient heat dissipation cannot be obtained. Furthermore, the third dielectric portion 41 needs to be formed thick in order to improve the insulation, and the insulation and the heat dissipation are in a trade-off relationship.

  On the other hand, in the semiconductor light emitting device 110 according to this embodiment, no dielectric is provided immediately below the light emitting layer 30. Immediately below the light emitting layer 30 is the second electrode 60, and the heat generated in the light emitting layer 30 spreads from the second electrode 60 to the support substrate 70 side and is easily released to the outside. Therefore, even if the first dielectric portion 40 is formed thick in order to improve insulation, the heat dissipation performance is not impaired. In the semiconductor light emitting device 110, both insulation and heat dissipation can be achieved.

Next, an example of a method for manufacturing the semiconductor light emitting device 110 will be described.
5 to 7 are schematic cross-sectional views for sequentially explaining an example of a method for manufacturing a semiconductor light emitting element.
First, as shown in FIG. 5A, the first semiconductor layer 10, the light emitting layer 30, and the second semiconductor layer 20 are grown in order on a growth substrate 80 such as sapphire. Thereby, the laminated structure 100 is formed on the growth substrate 80.

  The laminated structure 100 is formed using, for example, a metal organic chemical vapor deposition method. In addition, the formation method of the laminated structure 100 can use well-known techniques, such as a molecular beam epitaxial growth method other than a metal-organic vapor phase growth method.

As an example, the laminated structure 100 is formed as follows.
First, a high carbon concentration first AlN buffer layer (for example, a carbon concentration of 3 × 10 ¹⁸ cm ⁻³ or more, 5 × 10 ²⁰ cm ^{− is used} as a buffer layer on the growth substrate 80 whose surface is a sapphire c-plane. ³ or less, for example, a thickness of 3 nm or more and 20 nm or less, and a high-purity second AlN buffer layer (for example, a carbon concentration of 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less and a thickness of 2 μm) and a non-doped GaN buffer layer (for example, 2 μm in thickness) are formed in this order. The first AlN buffer layer and the second AlN buffer layer are single crystal aluminum nitride layers. By using single crystal aluminum nitride layers as the first and second AlN buffer layers, a high-quality semiconductor layer can be formed in the crystal growth described later, and damage to the crystal is greatly reduced.

Next, an Si-doped n-type GaN contact layer (for example, an Si concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less and a thickness of 6 μm), and Si-doped n-type Al _{A 0.10} Ga _0.90 N cladding layer (for example, Si concentration is 1 × 10 ¹⁸ cm ⁻³ and thickness is 0.02 μm) is sequentially formed in this order. The Si-doped n-type GaN contact layer and the Si-doped n-type Al _0.10 Ga _0.90 N cladding layer are the first semiconductor layer 10. For convenience, all or part of the GaN buffer layer may be included in the first semiconductor layer 10.

Here, the buffer layer formed on the growth substrate 80 is not limited to the AlN. For example, a low-temperature grown Al _x Ga _1-x N (0 ≦ x ≦ 1) thin film may be used for the buffer layer.

Next, as the light-emitting layer 30, a Si-doped n-type Al _0.11 Ga _0.89 N barrier layer and a GaInN well layer are alternately stacked in three periods, and further, the final Al of the multiple quantum well is formed. _{A 0.11} Ga _0.89 N barrier layer is further stacked. In the Si-doped n-type Al _0.11 Ga _0.89 N barrier layer, for example, the Si concentration is 1.1 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ¹⁹ cm ⁻³ or less. In the final Al _0.11 Ga _0.89 N barrier layer, for example, the Si concentration is 1.1 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ¹⁹ cm ⁻³ or less, and the thickness is, for example, 0.01 μm. The The thickness of such a multiple quantum well structure is, for example, 0.075 μm. Thereafter, a Si-doped n-type Al _0.11 Ga _0.89 N layer (for example, the Si concentration is 0.8 × 10 ¹⁹ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less, for example, the thickness is 0.01 μm). In addition, the wavelength of the emitted light in the light emitting layer 30 is 370 nm or more and 480 nm or less, or 370 nm or more and 400 nm or less, for example.

Furthermore, as the second semiconductor layer 20, a non-doped Al _0.11 Ga _0.89 N spacer layer (for example, a thickness of 0.02 μm), a Mg-doped p-type Al _0.28 Ga _0.72 N cladding layer (for example, Mg Concentration is 1 × 10 ¹⁹ cm ⁻³ , for example, thickness is 0.02 μm), Mg-doped p-type GaN contact layer (for example, Mg concentration is 1 × 10 ¹⁹ cm ⁻³ , thickness is 0.4 μm) And a high-concentration Mg-doped p-type GaN contact layer (for example, the Mg concentration is 5 × 10 ¹⁹ cm ⁻³ and the thickness is, for example, 0.02 μm) are sequentially formed in this order.
Note that the above composition, composition ratio, impurity type, impurity concentration, and thickness are merely examples, and various modifications are possible.

The ohmic characteristics with the second electrode 60 can be improved by setting the Mg concentration of the high-concentration Mg-doped p-type GaN contact layer to a high value of about 1 × 10 ²⁰ cm ⁻³ . However, in the case of a semiconductor light emitting diode, unlike the semiconductor laser diode, since the distance between the high-concentration Mg-doped p-type GaN contact layer and the light emitting layer 30 is short, there is a concern about deterioration of characteristics due to Mg diffusion. Therefore, by utilizing the fact that the contact area between the second electrode 60 and the high-concentration Mg-doped p-type GaN contact layer is wide and the current density during operation is low, the high-concentration Mg-doped p-type GaN is not greatly impaired. By suppressing the Mg concentration of the contact layer to about 1 × 10 ¹⁹ cm ⁻³ , Mg diffusion can be prevented and light emission characteristics can be improved.

In addition, the first AlN buffer layer having a high carbon concentration serves to alleviate the difference in crystal type from the growth substrate 80, and particularly reduces screw dislocations. Further, the surface of the high purity second AlN buffer layer is planarized at the atomic level. Therefore, crystal defects in the non-doped GaN buffer layer grown on this are reduced. In order to sufficiently reduce crystal defects, it is preferable to make the thickness of the second AlN buffer layer thicker than 1 μm. In order to prevent warping due to distortion, the film thickness is desirably 4 μm or less. The high-purity second AlN buffer layer is not limited to AlN, and may be Al _x Ga _1-x N (0.8 ≦ x ≦ 1), and can compensate for the warp of the growth substrate 80.

The non-doped GaN buffer layer grows in a three-dimensional island shape on the high purity second AlN buffer layer. Thereby, the non-doped GaN buffer layer plays a role of reducing crystal defects. In order to planarize the growth surface, it is desirable that the average film thickness of the non-doped GaN buffer layer be 2 μm or more. From the viewpoint of reproducibility and warpage reduction, the total film thickness of the non-doped GaN buffer layer is preferably 2 μm or more and 10 μm or less.
By employing these buffer layers, crystal defects can be reduced to about 1/10 compared to the case of employing a low-temperature grown AlN buffer layer. With this technique, a highly efficient semiconductor light emitting device is manufactured while being highly concentrated Si doping to the n-type GaN contact layer and emitting light in the ultraviolet band. Further, by reducing crystal defects in the non-doped GaN buffer layer, light absorption in the non-doped GaN buffer layer is also suppressed.

The emission wavelength of the quantum well layer is not particularly limited. For example, when a GaInN gallium nitride compound semiconductor is used, light emission of 375 nm to 700 nm can be obtained.
The buffer layer on the sapphire substrate is not particularly limited, and an Al _x Ga _1-x N (0 ≦ x ≦ 1) thin film grown at a low temperature may be used.

  Next, as illustrated in FIG. 5B, a recess 100 t is formed in a part of the laminated structure 100. The recess 100 t reaches the first semiconductor layer 10 from the second major surface 100 b of the multilayer structure 100. As a result, the first semiconductor layer 10 is exposed at the bottom of the recess 100t (exposed portion 10e).

  In order to form the recess 100t, a mask (not shown) is formed on the second main surface 100b of the laminated structure 100, and, for example, dry etching is performed. That is, the mask is provided with an opening in a portion where the recess 100t is formed, and the stacked structure 100 is removed from the second main surface 100b to the first semiconductor layer 10 by etching. Thereby, the recessed part 100t is formed. The angle of the inner surface of the recess 100t is not particularly limited, but the angle at which the emitted light from the light emitting layer 30 reflects 30 degrees of light having the maximum intensity in the direction opposite to the traveling direction is 60 degrees or more. Is preferred. The depth of the recess 100t is not particularly limited, but the deeper the light extraction efficiency is, the easier it is to change the traveling direction of the emitted light propagating in the lateral direction in the laminated structure 100. On the other hand, when the depth is too deep, it is difficult to fill the recess 100t with solder when the support substrate 70 is joined in a later step. If the recess 100t is deepened until it reaches the non-doped GaN buffer layer, the first electrode 50 cannot be formed on the Si-doped n-type GaN contact layer. Therefore, the depth of the recess 100t is, for example, 0.6 μm or more and 6.6 μm or less, preferably 1.0 μm or more and 3.0 μm or less.

  Next, as illustrated in FIG. 5B, the first electrode 50 in contact with the first semiconductor layer 10 is formed. As the first electrode 50, first, a Ti / Al / Ni / Au laminated film to be an ohmic electrode is formed with a film thickness of, for example, 300 nm on the exposed surface 100e of the first semiconductor layer 10 exposed from the recess 100t. Sintering is performed at 600 ° C. for 5 minutes in a nitrogen atmosphere.

  Next, on the ohmic electrode, for example, a laminated film of Ti / Au / Ti is used as a bonding metal for the current diffusion and the lead portion 53 to the pad electrode 55 and as an adhesive metal to the insulating layer. It is formed with a film thickness of 1200 nm.

  The material of the first electrode 50 is not limited to the above. For example, by using Al as the first layer, an n-type contact layer and good ohmic characteristics and low contact characteristics can be obtained, and the electrode can also be a reflective electrode. Therefore, the light extraction efficiency and the design freedom of the first electrode 50 are improved. improves. Since Al has low environmental resistance, reliability and adhesion can be improved by employing, for example, an Al alloy slightly containing Si.

Next, the first dielectric portion 40 is formed so as to cover the first electrode 50 and the recess 100t. As the first dielectric part 40, for example, SiO ₂ is formed with a film thickness of 800 nm.
Here, when the first dielectric portion 40 is formed, film formation by high-temperature growth can be applied. That is, since the first electrode 50 formed previously is sintered at about 600 ° C., the first electrode 50 has heat resistance up to the same heat treatment condition. Therefore, the film formation of the first dielectric part 40 can be performed at a sufficiently high temperature. For this reason, the 1st dielectric material part 40 turns into a high quality film | membrane excellent in insulation, coverage, reliability, etc.

  Next, as illustrated in FIG. 5C, the first dielectric portion 40 on the second semiconductor layer 20 is removed in order to form the second electrode 60 having ohmic characteristics. Then, an Ag / Pt laminated film serving as an ohmic electrode is formed to a thickness of, for example, 200 nm on the surface of the second semiconductor layer 20 exposed by removing the first dielectric portion 40. Then, sintering is performed in an oxygen atmosphere at about 400 ° C. for 1 minute to form the first portion 61 of the second electrode 60.

  The second electrode 60 contains at least silver or an alloy thereof. The reflection efficiency of a normal metal single layer film in the visible light band tends to decrease as the wavelength becomes shorter in the ultraviolet region of 400 nm or less, but silver has a high reflection efficiency even for light in the ultraviolet region of 370 nm to 400 nm. Has characteristics. Therefore, when the semiconductor light emitting device emits ultraviolet light and the second electrode 60 is a silver alloy, it is desirable that the second electrode 60 on the semiconductor interface side has a larger silver component ratio. The film thickness of the second electrode 60 is preferably 100 nm or more in order to ensure the light reflection efficiency.

  Next, as shown in FIG. 6A, the second portion 62 serving as a bonding metal is formed on the entire surface where the first portion 61 and the first dielectric portion 40 are exposed, for example, Ti / Pt / Au. The laminated film is formed with a film thickness of, for example, 800 nm.

  Next, a support substrate 70 made of, for example, Ge is prepared. On the main surface of the support substrate 70, for example, solder (not shown) made of AuSn alloy having a film thickness of 3 μm is provided. Then, the second portion 62 and the solder are opposed to each other and heated to a temperature equal to or higher than the eutectic point of the solder, for example, 300 ° C. Accordingly, the support substrate 70 is bonded to the second main surface 100b side of the multilayer structure 100.

Then, as shown in FIG. 6B, for example, the third harmonic (355 nm) or the fourth harmonic (266 nm) of a solid laser of YVO ₄ from the growth substrate 80 side with respect to the stacked structure 100. The laser beam LSR is irradiated. The laser light LSR has a wavelength shorter than the forbidden bandwidth wavelength based on the forbidden bandwidth of GaN of the GaN buffer layer (for example, the above-described non-doped GaN buffer layer). That is, the laser light LSR has energy higher than the forbidden band width of GaN.

  This laser light LSR is efficiently absorbed in a region of the GaN buffer layer (non-doped GaN buffer layer) on the side of the single crystal AlN buffer layer (in this example, the second AlN buffer layer). As a result, the GaN on the single crystal AlN buffer layer side of the GaN buffer layer is decomposed by heat generation.

Here, when the crystal layer on the sapphire substrate which is the growth substrate 80 is bonded to the support substrate 70 or when the sapphire substrate which is the growth substrate 80 is peeled off by decomposing GaN with the laser light LSR, Crystal defects and damage are likely to occur in the crystal due to a difference in thermal expansion coefficient between the substrate 70 and sapphire or GaN, heat due to local heating, a product generated by decomposition of GaN, and the like. When a crystal defect or damage enters, Ag of the second electrode 60 diffuses from there, leading to an increase in leakage inside the crystal and an increase in crystal defects.
According to this embodiment, since a high-quality semiconductor layer can be formed by using a single crystal AlN buffer layer, damage to the crystal is greatly reduced. In addition, when GaN is decomposed with the laser light LSR, heat is diffused to the AlN buffer layer having high thermal conductivity characteristics in the immediate vicinity of GaN, so that it is less susceptible to thermal damage due to local heating.

  Then, the decomposed GaN is removed by hydrochloric acid treatment or the like, and the growth substrate 80 is peeled off from the laminated structure 100. Thereby, the growth substrate 80 and the laminated structure 100 are separated.

Next, the unevenness and the pad electrode 55 are formed on the exposed first main surface 100 a of the laminated structure 100.
First, as shown in FIG. 7A, a part of the laminated structure 100 is removed by dry etching, and a part of the first electrode 50 (extracting part 53) is exposed. Next, the second dielectric portion 45 is formed on the entire surface of the first main surface 100a of the multilayer structure 100, and an opening is provided in a part thereof. As the second dielectric portion 45, for example, SiO ₂ is used. The film thickness of the second dielectric part 45 is, for example, 800 nm. For example, the surface of the non-doped GaN buffer layer is exposed from the opening of the second dielectric portion 45.

  Next, as shown in FIG. 7B, the surface of the non-doped GaN buffer layer is processed by, for example, alkaline etching with a KOH solution using the second dielectric part 45 provided with the opening as a mask, so that the uneven part is formed. 12p is formed. As an etching condition, for example, a 1 mol (mol) / liter (L) KOH solution is heated to 80 ° C., and etching is performed for 20 minutes.

  The uneven portion 12p may be formed in the n-type contact layer. However, since the n-type contact layer forms a low-resistance ohmic contact with the n-side electrode (first electrode 50), the carrier concentration (for example, impurity concentration) is set high. When unevenness or a flat part is formed on the n-type contact layer, surface roughness or impurity precipitation occurs, and as a result, the light extraction efficiency may be reduced. On the other hand, since the impurity concentration of the GaN buffer layer is lower than that of the n-type contact layer, it is advantageous in that surface roughness and impurity precipitation are less likely to occur.

  Here, the method of forming the uneven portion 12p may be wet etching as described above or dry etching. In alkaline etching using a KOH solution or the like, anisotropic etching is performed along the plane orientation (mainly {10-1-1}) of the GaN crystal, and as a result, a hexagonal pyramid structure is formed. Etching rate, size of hexagonal pyramid, etc., depending on etching temperature, etching time, hydrogen ion index (pH) adjusted by adding another substance, concentration, ultraviolet (UV) light and UV laser irradiation And the density changes greatly.

  In general, the larger the etching amount (the depth from the surface before etching to the deepest portion of the uneven portion 12p formed after etching), the larger the uneven portion 12p is formed densely. In the case of processing GaN by dry etching, the N plane is different from the Ga plane and is easily affected by crystal orientation and transition, and is easily etched anisotropically. The surface of GaN grown on the c-plane sapphire substrate is usually a Ga plane, and the surface of GaN exposed by removing the sapphire substrate as in this embodiment is an N plane. Accordingly, it is easy to form the uneven portion 12p by anisotropic etching by dry etching. Further, the uneven portion 12p may be formed by dry etching using a mask. Thereby, since the uneven | corrugated | grooved part 12p as designed can be formed, it is easy to improve light extraction efficiency.

  The concavo-convex portion 12p is provided, for example, to effectively extract incident emitted light or to change the incident angle. For this reason, it is preferable that the magnitude | size is more than the wavelength of the emitted light in a crystal layer. When the uneven portion 12p is smaller than the wavelength of the emitted light, the emitted light incident on the uneven portion 12p exhibits a behavior explained by wave optics such as scattering and diffraction at the interface of the uneven portion 12p. Thereby, part of the emitted light that was originally transmitted is not extracted. Further, when the uneven portion 12p is sufficiently smaller than the wavelength of the emitted light, the uneven portion 12p is regarded as a layer whose refractive index continuously changes. For this reason, it becomes the same as a flat surface without unevenness, and the light extraction efficiency is not improved.

  The experimental results using the semiconductor light emitting device with a wavelength of 390 nm of the emitted light produced in the present embodiment (the emission wavelength in the crystal layer is about 155 nm) show a tendency that the light output increases as the size of the uneven portion 12p increases. It was. This increasing tendency continued gradually until the size of the uneven portion 12p reached about 3 μm. From this, it was found that the size of the concavo-convex portion 12p is preferably at least twice the emission wavelength in the crystal layer, more preferably at least 10 times.

  Next, a part of the second dielectric part 45 covering the lead part 53 is removed, and a pad electrode 55 is formed on a part of the exposed lead part 53. As the pad electrode 55, for example, a laminated film of Ti / Pt / Au is used. The film thickness of the pad electrode 55 is, for example, 800 nm. A bonding wire is connected to the pad electrode 55.

Then, the support substrate 70 is ground to a thickness of about 100 μm by grinding or the like, and a Ti / Pt / Au laminated film, for example, with a film thickness of 800 nm, for example, is formed as the back electrode 85 on the ground surface. The back electrode 85 is connected to a heat sink or a package.
Thereafter, the support substrate 70 is cut by cleavage or a diamond blade as necessary. Thereby, the semiconductor light emitting device 110 is completed.

  In the above manufacturing method, an example in which a sapphire substrate is used as the growth substrate 80 has been shown. However, a Si substrate may be used as the growth substrate 80. Further, when the Si substrate is used as the growth substrate 80, the process for removing the growth substrate 80 is not irradiation with the laser light LSR, but after grinding to a certain thickness and then removing the remaining Si substrate by etching. Good.

(Second Embodiment)
FIG. 8 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the second embodiment.
FIG. 9 is a schematic plan view of the surface side illustrating the configuration of the semiconductor light emitting element according to the second embodiment.
FIG. 10 is a schematic plan view on the back surface side illustrating the configuration of the semiconductor light emitting device according to the second embodiment.
Here, FIG. 8 is a schematic cross-sectional view taken along the line BB ′ of FIG.

  As illustrated in FIG. 8, the semiconductor light emitting device 120 according to the second embodiment includes the multilayer structure 100, the first electrode 50, the second electrode 60, and the first dielectric part 40. In addition, the semiconductor light emitting device 120 includes a pad electrode 57 that is electrically connected to the first electrode 50. The pad electrode 57 is juxtaposed with the second portion 62 of the second electrode 60.

A via portion 56 is provided between the pad electrode 57 and the contact portion 51 of the first electrode 50. The via part 56 extends along the Z-axis direction. For example, the via portion 56 is provided inside the hole H that penetrates the second portion 62 of the second electrode 60 in the Z-axis direction. In the hole H, the via part 56 is provided via the buried insulator part 43. For the buried insulator 43, for example, a dielectric (SiO ₂ or the like) is used. A resin may be used for the embedded insulator portion 43. The pad electrode 57 is electrically connected to the contact portion 51 by the via portion 56. The via part 56 may be included in the first electrode 50.

In the semiconductor light emitting device 120, the second portion 62 of the second electrode 60 is formed of, for example, plated metal. That is, the second portion 62 is formed by plating. For example, Cu is used as the plating metal. The second portion 62 is formed to a thickness of, for example, about 200 μm by plating. As a result, the second portion 62 can be used as the support substrate 70 (see FIG. 1) with sufficient strength.
In the second electrode 60, the first portion 61 and the second portion 62 may be formed by plating.

  As described above, in the semiconductor light emitting device 120, the pad electrode 57 is juxtaposed with the second portion 62 of the second electrode 60. That is, in the semiconductor light emitting device 120, both the first electrode 50 and the second electrode 60 are arranged on the side (second main surface 100b side) opposite to the light extraction surface (first main surface 100a) of the multilayer structure 100. Has been. The first electrode 50 and the second electrode 60 are not disposed on the light extraction surface (see FIGS. 8 and 9). Therefore, the area of the light extraction surface can be expanded as compared with the light emitting element in which the electrode is disposed on the light extraction surface side. Thereby, the effective current density is lowered and the light emission efficiency is improved.

  Further, since the pad electrode 57 is electrically connected to the contact portion 51 through the via portion 56, the pad electrode 57 can be freely laid out on the back surface side (second main surface 100b side) of the semiconductor light emitting element 120. it can. As shown in FIG. 10, the pad electrode 57 may be provided at a plurality of locations in the surface on the back surface side. Further, the pad electrode 57 may be provided at a corner (at least one corner) on the back surface side. Further, the pad electrode 57 may be provided in the central portion on the back surface side. In the semiconductor light emitting device 120, the layout of the pad electrode 57 can be easily set in consideration of the current flow between the first electrode 50 and the second electrode 60.

FIG. 11 is a schematic cross-sectional view illustrating the configuration of a semiconductor light emitting device using the semiconductor light emitting element according to the embodiment.
In this specific example, the semiconductor light emitting device 110 according to the first embodiment is used, but the semiconductor light emitting device 120 according to another embodiment can also be used in the semiconductor light emitting device.
The semiconductor light emitting device 500 is a white LED that combines the semiconductor light emitting element 110 and a phosphor. That is, the semiconductor light emitting device 500 according to the present embodiment includes the semiconductor light emitting element 110 and a phosphor that absorbs light emitted from the semiconductor light emitting element 110 and emits light having a wavelength different from that of the light.

  As shown in FIG. 11, in the semiconductor light emitting device 500 according to this embodiment, a reflective film 73 is provided on the inner surface of a container 72 made of ceramic or the like. The reflective film 73 is provided separately on the inner side surface and the bottom surface of the container 72. The reflective film 73 is made of aluminum, for example. Among these, on the reflective film 73 provided on the bottom of the container 72, the semiconductor light emitting device 110 is installed via a submount 74.

  The semiconductor light emitting device 110 has the first main surface 100a facing upward, and the back surface of the support substrate 70 is fixed to the submount 74 using, for example, low-temperature solder. For fixing the semiconductor light emitting element 110, the submount 74, and the reflective film 73, it is also possible to use adhesion by an adhesive.

  An electrode 75 is provided on the surface of the submount 74 on the semiconductor light emitting element 110 side. The support substrate 70 of the semiconductor light emitting device 110 is mounted on the electrode 75 via the back electrode 85. As a result, the electrode 75 is electrically connected to the second electrode 60 via the back electrode 85 and the support substrate 70. The pad electrode 55 is connected to an electrode (not shown) provided on the container 72 side by a bonding wire 76. These connections are made at a portion between the reflective film 73 on the inner surface and the reflective film 73 on the bottom surface.

  A first phosphor layer 81 including a red phosphor is provided so as to cover the semiconductor light emitting device 110 and the bonding wire 76. On the first phosphor layer 81, a second phosphor layer 82 containing a blue, green or yellow phosphor is formed. A lid 77 made of silicone resin or the like is provided on the phosphor layer.

The first phosphor layer 81 includes a resin and a red phosphor dispersed in the resin.
As the red phosphor, for example, Y ₂ O ₃ , YVO ₄ , Y ₂ (P, V) O ₄ can be used as a base material, and trivalent Eu (Eu ³⁺ ) is included as an activator in this. . That is, Y ₂ O ₃ : Eu ³⁺ , YVO ₄ : Eu ^{3+ and the} like can be used as the red phosphor. The concentration of Eu ³⁺ can be 1% to 10% in terms of molar concentration.

As a base material of the red phosphor, LaOS, Y ₂ (P, V) O ₄ or the like can be used in addition to Y ₂ O ₃ and YVO ₄ . In addition to Eu ³⁺ , Mn ⁴⁺ or the like can be used. In particular, by adding a small amount of Bi together with trivalent Eu to the YVO ₄ matrix, the absorption at 390 nm increases, so that the luminous efficiency can be further increased. Moreover, as resin, a silicone resin can be used, for example.

  The second phosphor layer 82 includes a resin and at least one of blue, green, and yellow phosphors dispersed in the resin. For example, a phosphor combining a blue phosphor and a green phosphor may be used, or a phosphor combining a blue phosphor and a yellow phosphor may be used, and a blue phosphor, a green phosphor and a yellow phosphor may be used. You may use the fluorescent substance which combined the fluorescent substance.

As the blue phosphor, for example, (Sr, Ca) ₁₀ (PO ₄ ) ₆ Cl ₂ : Eu ²⁺ and BaMg ₂ Al ₁₆ O ₂₇ : Eu ²⁺ can be used.
As the green phosphor, for example, Y ₂ SiO ₅ : Ce ³⁺ , Tb ³⁺ having trivalent Tb as the emission center can be used. In this case, energy is transferred from Ce ions to Tb ions, so that the excitation efficiency is improved. For example, Sr ₄ Al ₁₄ O ₂₅ : Eu ²⁺ can be used as the green phosphor.

For example, Y ₃ Al ₅ : Ce ³⁺ can be used as the yellow phosphor.
As the resin, for example, a silicone resin can be used. In particular, trivalent Tb exhibits sharp light emission near 550 nm where the visibility is maximized. Therefore, when combined with sharp red light emission of trivalent Eu, the light emission efficiency is significantly improved.

  According to the semiconductor light emitting device 500 according to the present embodiment, for example, ultraviolet light having a wavelength of 390 nm generated from the semiconductor light emitting element 110 is emitted above and to the side of the semiconductor light emitting element 110. Further, the phosphors included in each phosphor layer are efficiently excited by the ultraviolet light reflected by the reflecting film 73. For example, the phosphor having the emission center of trivalent Eu contained in the first phosphor layer 81 is converted into light having a narrow wavelength distribution around 620 nm. Thereby, it is possible to obtain red visible light efficiently.

In addition, blue, green, and yellow phosphors included in the second phosphor layer 82 are excited, so that blue, green, and yellow visible light can be efficiently obtained. Furthermore, as these mixed colors, white light and various other colors of light can be obtained with high efficiency and good color rendering.
According to the semiconductor light emitting device 500, desired color light can be obtained with high efficiency.

  As described above, according to the semiconductor light emitting element according to the embodiment, it is possible to improve heat extraction efficiency by improving heat dissipation.

  In addition, although this Embodiment and its modification were demonstrated above, this invention is not limited to these examples. For example, for each of the above-described embodiments or modifications thereof, those in which those skilled in the art appropriately added, deleted, and changed the design of the embodiments, and those that appropriately combined the features of each embodiment, As long as the gist of the present invention is provided, it is included in the scope of the present invention.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 12p ... Uneven part, 20 ... 2nd semiconductor layer, 30 ... Light emitting layer, 40 ... 1st dielectric part, 43 ... Embedded insulator part, 45 ... 2nd dielectric part, 50 ... 1st DESCRIPTION OF SYMBOLS 1 electrode, 51 ... Contact part, 53 ... Lead part, 55 ... Pad electrode, 60 ... 2nd electrode, 61 ... 1st part, 62 ... 2nd part, 63 ... Lead part, 65 ... Pad electrode, 70 ... Support substrate , 70a ... edge, 80 ... substrate for growth, 85 ... back electrode, 100 ... laminated structure, 100a ... first main surface, 100b ... second main surface, 100t ... concave, 110, 120, 190 ... semiconductor light emitting device

Claims (5)

A first semiconductor layer including a nitride semiconductor;
A second semiconductor layer comprising a nitride semiconductor;
A light-emitting layer including a nitride semiconductor provided between the first semiconductor layer and the second semiconductor layer;
A laminated structure having a recess that reaches the first semiconductor layer from the surface on the second semiconductor layer side, and
A contact portion in contact with the first semiconductor layer in the recess, and a contact portion comprising a first region and a second region, said laminated structure wherein the second region is electrically connected from said second region A first electrode having a via portion extending toward the opposite side of the first semiconductor layer;
A second electrode in contact with the second semiconductor layer and reflecting light;
A dielectric portion having a portion embedded in the recess, and electrically insulating between the first electrode and the second electrode and between the first semiconductor layer and the second electrode; ,
A pad electrode electrically connected to the via portion of the first electrode and located on the opposite side of the stacked structure from the first semiconductor layer;
With
The second electrode overlaps the first region when viewed in the stacking direction from the first semiconductor layer to the second semiconductor layer,
A part of the dielectric part is provided between the first region and the second electrode, and overlaps the first region when viewed in the stacking direction,
The area of the region of the second electrode, the semiconductor light emitting element being greater than the contact area between the first semiconductor layer of the contact portion overlapping with the previous miracle layer the light emitting layer when viewed in the direction. The emitted light emitted from the light emitting layer is emitted more in the direction from the second semiconductor layer to the first semiconductor layer than in the direction from the first semiconductor layer to the second semiconductor layer. The semiconductor light emitting device according to claim 1. The first semiconductor layer includes a concavo-convex portion provided on the first main surface of the first semiconductor layer opposite to the second semiconductor layer ,
3. The semiconductor light emitting element according to claim 1, wherein the concavo-convex portion has concavo-convex portions having a pitch longer than a peak wavelength of emitted light emitted from the light emitting layer.   The semiconductor light emitting element according to claim 1, wherein the second electrode includes a plated metal. The semiconductor light emitting element according to any one of claims 1 to 4, wherein a peak wavelength of emitted light emitted from the light emitting layer is 370 nanometers or more and 400 nanometers or less.

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