JP5715461B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device .

Conventionally, a semiconductor device having a super junction structure is known (see, for example, Patent Document 1).
FIG. 13 is a cross-sectional view showing a main part of a conventional semiconductor device 800. In FIG. 13, reference numeral 832 denotes a peripheral insulating film, and reference numeral 850 denotes a cathode electrode layer.

Conventional semiconductor device 800 is a Schottky barrier diode, as shown in FIG. 13, and the upper ^{n +} -type semiconductor substrate 812, n located on ^{n +} -type semiconductor substrate 812 ^- -type drift layer 814 A plurality of first trenches 816 and a plurality of second trenches 828 formed inside the n ⁻ type drift layer 814, and a p-type semiconductor material formed by epitaxial growth inside the first trench 816 and the second trench 828. The plurality of columnar embedded layers 818 and the plurality of second columnar embedded layers 830, and the n ⁻ type drift layer 814, the plurality of columnar embedded layers 818, and the shots formed on the plurality of second columnar embedded layers 830 A key barrier metal layer 846. In the columnar buried layer 818, the total amount of n-type and p-type impurities is approximately equal between the n ⁻ type drift layer 814 and the p-type columnar buried layer 818 in the region sandwiched between the columnar buried layers 818. It contains a p-type impurity at such a concentration that the state of charge balance can be achieved, and is disposed in the active region R1. The second columnar embedded layer 830 has a function as a guard ring, and is disposed over several tens of the peripheral region R3 surrounding the active region R1 (see, for example, Patent Document 1).

  Since the conventional semiconductor device 800 has a super junction structure, it becomes a Schottky barrier diode having high reverse breakdown voltage characteristics.

Further, according to the conventional semiconductor device 800, the peripheral region R3 is provided with several tens of second columnar buried layers (guard rings) 830 made of the second conductivity type semiconductor material. The second columnar buried layer 830 and the n ⁻ type drift layer 814 inside the outermost second columnar buried layer are depleted, and the breakdown voltage at the periphery of the element can be increased.

  However, in the conventional semiconductor device 800, since several tens of second columnar embedded layers 830 are provided in the peripheral region R3 in order to increase the breakdown voltage at the periphery of the element, the area of the peripheral region increases. As a result, there is a problem that the semiconductor device becomes large.

  Accordingly, the inventors of the present invention have conceived a semiconductor device capable of reducing the area of the peripheral region while increasing the breakdown voltage at the periphery of the element, and is referred to as Japanese Patent Application No. 2010-201299 (hereinafter referred to as a prior application). ) Has already been filed.

FIG. 14 is a cross-sectional view showing a main part of a semiconductor device 900 according to the prior application. In FIG. 14, reference numeral 912 indicates a semiconductor substrate, reference numeral 914 indicates an n ⁻ type drift layer, reference numeral 916 indicates a buried layer trench, reference numeral 946 indicates a Schottky barrier metal layer, and reference numeral 950 indicates a cathode electrode layer. Indicates.

The semiconductor device 900 according to the prior application is a Schottky barrier diode having a super junction structure as in the case of the conventional semiconductor device 800. As shown in FIG. 14, the active region R1 includes a columnar buried layer. A plurality of columnar buried layers 918 made of a p-type semiconductor material having a concentration capable of achieving a charge balance with the n ⁻ type drift layer 914 surrounded by the active region R1 and the peripheral region R3 In the peripheral withstand voltage region R2 between the ring-shaped second trench 922, the insulating film 924 formed on the inner surface of the second trench 922, and the conductivity formed inside the second trench 922 via the insulating film 924. A peripheral breakdown voltage structure 920 having a material layer 926 is provided.

For this reason, according to the semiconductor device 900 according to the prior application, since the peripheral breakdown voltage structure 920 described above is disposed in the peripheral breakdown voltage region R2, the gap between the n ⁻ type drift layer 914 and the columnar buried layer 918 is determined. When a reverse bias is applied to the pn junction, the insulating film 924 of the peripheral breakdown voltage structure 920 takes up most of the required breakdown voltage. The withstand voltage can be increased.

  In addition, according to the semiconductor device 900 according to the prior application, it is not necessary to provide several tens of second columnar buried layers in the peripheral region R3, so that the area of the peripheral region R3 is smaller than that of the conventional semiconductor device 800. It becomes possible to do.

JP 2004-6595 A

  However, according to the research of the inventors of the present invention, in the semiconductor device 900 according to the prior application, the breakdown voltage at the peripheral portion of the element is reduced due to the excessive removal of the first insulating film 932 during the manufacturing process. It turns out that there is a problem that it may end up. FIG. 15 is a view for explaining the main part of the manufacturing process for manufacturing the semiconductor device 800 according to the prior application. FIG. 15A is a cross-sectional view immediately before the CMP (Chemical Mechanical Polishing) process, and FIG. 15B is a cross-sectional view immediately after the CMP process. In FIG. 15, reference numeral 917 denotes a main body portion of the columnar buried layer. That is, when manufacturing the semiconductor device 900 according to the prior application, as shown in FIGS. 15A and 15B, the cap is formed when the columnar buried layer 918 is formed by the epitaxial growth method. The step of removing the portion 919 by the CMP method is required. However, in the semiconductor device 900 according to the prior application, the active region R1 and the peripheral region R3 have greatly different surface structures. The breakdown voltage at the periphery of the element may decrease due to the fact that the first insulating film 932 is excessively cut in the vicinity of R3. Such a problem is not a problem that exists only in a semiconductor device having a super junction structure, but a problem that exists in all semiconductor devices having a columnar buried layer in an active region.

  Therefore, the present invention has been made to solve such a problem, and it is possible to manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the withstand voltage at the periphery of the element. In addition, an object of the present invention is to provide a semiconductor device in which the withstand voltage at the periphery of the element does not decrease due to the above-described CMP process. It is another object of the present invention to provide a method for manufacturing a semiconductor device capable of manufacturing such a semiconductor device.

[1] A semiconductor device according to the present invention includes a plurality of columnar shapes including a first conductivity type semiconductor layer and a second conductivity type semiconductor material formed by epitaxial growth inside a first trench formed in an active region of the semiconductor layer. A buried layer, a ring-shaped second trench formed in a peripheral pressure-resistant region surrounding the active region, an insulating film formed on the inner surface of the second trench, and an insulating film formed inside the second trench via the insulating film A peripheral breakdown voltage structure that has a conductive material layer and depletes the semiconductor layer in a portion sandwiched between the conductive material layer and the columnar buried layer at the time of reverse bias, and is formed in a peripheral region surrounding the peripheral breakdown voltage region And one or more second columnar buried layers made of a second conductivity type semiconductor material formed by epitaxial growth inside the third trench.

[2] In the semiconductor device of the present invention, the semiconductor layer, the plurality of columnar buried layers, and the one or more second columnar buried layers are preferably made of single crystal silicon.

[3] In the semiconductor device of the present invention, the plurality of columnar buried layers are formed in parallel at a first interval, and the columnar buried layer closest to the peripheral breakdown voltage structure among the plurality of columnar buried layers. It is preferable that an interval between the layer and the peripheral breakdown voltage structure is narrower than the first interval.

[4] In the semiconductor device of the present invention, an interval between the second columnar embedded layer closest to the peripheral breakdown voltage structure and the peripheral breakdown voltage structure among the one or more second columnar embedded layers is the first column. Narrower than one interval is preferred.

[5] In the semiconductor device of the present invention, it is preferable that the second columnar embedded layer includes two or more second columnar embedded layers formed in parallel at intervals equal to or less than the first interval.

[6] In the semiconductor device of the present invention, it is preferable that the depth position of the bottom portion of the columnar buried layer is equal to the depth position of the bottom portion of the conductive material layer.

[7] In the semiconductor device of the present invention, it is preferable that the depth position of the bottom portion of the second columnar embedded layer is equal to the depth position of the bottom portion of the conductive material layer.

[8] The semiconductor device of the present invention may be a Schottky barrier diode.

[9] The semiconductor device of the present invention may be a planar gate type MOSFET.

[10] The semiconductor device of the present invention may be a trench gate type MOSFET.

[11] The semiconductor device of the present invention may be a planar gate type IGBT.

[12] The semiconductor device of the present invention may be a trench gate type IGBT.

[13] The semiconductor device of the present invention may be a semiconductor device having a super junction structure.

[14] A manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention, the semiconductor layer preparing step of preparing the first conductivity type semiconductor layer, A peripheral breakdown voltage structure forming step for forming the peripheral breakdown voltage structure in the peripheral breakdown voltage region, and the first trench and the peripheral region using the first insulating film having a predetermined pattern formed on the surface of the semiconductor layer as a mask. Forming the third trench, and epitaxially growing a second conductivity type semiconductor material to a height position exceeding the height position of the surface of the first insulating film inside the first trench and the third trench, Forming a columnar buried layer in the active region and forming a second columnar buried layer in the peripheral region; and forming the columnar buried layer and the second columnar buried layer in the peripheral region, 1, characterized in that it comprises a CMP process for removing by polishing by CMP to a height position of the surface of the insulating film.

  According to the semiconductor device of the present invention, a reverse bias is applied to the pn junction between the first conductive type semiconductor layer and the second conductive type columnar buried layer because the peripheral breakdown voltage region has the peripheral breakdown voltage structure described above. In this case, since the insulating film having the peripheral withstand voltage structure takes up most of the required withstand voltage, the breakdown voltage at the peripheral portion of the element may be increased as in the case of the semiconductor device 900 according to the prior application. it can.

  Further, according to the semiconductor device of the present invention, since the so-called dummy columnar buried layer (second columnar buried layer) is disposed in the peripheral region, the surface structure is greatly different between the active region and the peripheral region. Therefore, the first insulating film is not excessively etched in the vicinity of the peripheral breakdown voltage region during the CMP process, and as a result, the breakdown voltage in the peripheral portion of the element is reduced due to the CMP process. It wo n’t happen.

  Furthermore, according to the semiconductor device of the present invention, since the breakdown voltage is maintained not in the peripheral region but in the peripheral breakdown voltage region, about 2 to 5 second columnar buried layers are sufficient. It is not necessary to provide several tens of second columnar buried layers as in the case of the breakdown voltage semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  For this reason, the semiconductor device of the present invention can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the periphery of the element, and is attributable to the above-described CMP process. Thus, a semiconductor device in which the withstand voltage at the periphery of the element does not decrease is obtained.

  According to the semiconductor device manufacturing method of the present invention, the semiconductor device of the present invention can be manufactured.

1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a diagram for explaining a semiconductor device 200 according to a second embodiment. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device 200 according to the second embodiment. FIG. 6 is a diagram for explaining a semiconductor device 300 according to a third embodiment. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device 300 according to the third embodiment. FIG. 6 is a view for explaining a semiconductor device 400 according to a fourth embodiment. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device 400 according to the fourth embodiment. FIG. 10 is a diagram for explaining a semiconductor device 500 according to a fifth embodiment. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device 500 according to the fifth embodiment. It is a figure shown in order to demonstrate the conventional semiconductor device 800. It is a figure shown in order to demonstrate the semiconductor device 900 concerning a prior application. It is a figure shown in order to demonstrate the principal part of the manufacturing process which manufactures the semiconductor device 900 based on a prior application.

  Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device of the present invention will be described based on the embodiments shown in the drawings.

[Embodiment 1]
1. Configuration of Semiconductor Device 100 According to First Embodiment First, the configuration of the semiconductor device 100 according to the first embodiment will be described.
FIG. 1 is a diagram for explaining the semiconductor device 100 according to the first embodiment. 1A is a plan view of the semiconductor device 100 according to the first embodiment, FIG. 1B is a cross-sectional view taken along the line XX ′ of FIG. 1A, and FIG. It is YY 'sectional drawing of a). In FIG. 1A, only the columnar buried layer 118, the conductive material layer 126, and the second columnar buried layer 130 are shown for easy understanding.

  The semiconductor device 100 according to the first embodiment is a Schottky barrier diode having a super junction structure, and as shown in FIG. 1A, an active region R1, a peripheral withstand voltage region R2 surrounding the active region R1, and a peripheral withstand voltage. It is divided into a peripheral region R3 surrounding the region R2.

As shown in FIG. 1B, the semiconductor device 100 according to the first embodiment includes an n ⁻ type drift layer 114, a columnar embedded layer 118, a peripheral breakdown voltage structure 120, a second columnar embedded layer 130, A peripheral insulating film 132, a Schottky barrier metal layer 146, and a cathode electrode layer 150 are provided.

n ^- -type drift layer 114, which has been formed by epitaxial growth on top of the ^{n +} -type semiconductor substrate 112, ^{n +} -type semiconductor substrate 112 and the n ^- constituting the semiconductor substrate 110 by the type drift layer 114 . The thickness of the n ⁻ type drift layer 114 is, for example, 10 μm, and the impurity concentration of the n ⁻ type drift layer is, for example, 1.5 × 10 ¹⁶ cm ⁻³ .

The columnar buried layer 118 is made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside the first trench 116 formed in the active region R1 in the n ⁻ type drift layer 114. The number of the columnar buried layers 118 can be appropriately changed according to the purpose of use and the structure. The impurity concentration of the p-type semiconductor material is, for example, 4.5 × 10 ¹⁶ cm ⁻³ .

  The depth positions of the bottom portions of the columnar buried layers 118 are all the same and are equal to the depth positions of the bottom portions of the conductive material layer 126 described later. The depth of the columnar buried layer 118 is, for example, 5.5 μm, and the width is, for example, 0.5 μm. The columnar buried layers 118 are formed in parallel at the first interval d1. The first distance d1 is, for example, 1.5 μm.

  The peripheral withstand voltage structure 120 includes the second trench 122, the insulating film 124, and the conductive material layer 126, and depletes a portion sandwiched between the conductive material layer 126 and the columnar buried layer 118 at the time of reverse bias. The distance between the columnar buried layer 118 closest to the peripheral voltage withstanding structure 120 in the columnar buried layer 118 and the peripheral voltage withstanding structure 120 is a second distance d2 that is narrower than the first distance d1. The second interval d2 is, for example, 1.0 μm.

  The second trench 122 is a ring-shaped groove formed in the peripheral breakdown voltage region R2, and has a width of, for example, 2.5 μm and a depth of 6.5 μm. In the first embodiment, the shape of the second trench is a square, but may be another quadrangle such as a rectangle, another polygon, a polygon with rounded corners, and a circle.

The insulating film 124 is a thermal oxide film formed on the inner surface of the second trench 122 and has a thickness of, for example, 1.0 μm.
The conductive material layer 126 is formed inside the second trench 122 via the insulating film 124, and is made of, for example, polysilicon containing a high concentration of impurities.

The second columnar embedded layer 130 is two columnar embedded layers formed in the peripheral region R3 and made of a p-type semiconductor material. The number of the second columnar embedded layers 130 can be appropriately changed according to the purpose of use and the structure. The impurity concentration of the p-type semiconductor material is, for example, 4.5 × 10 ¹⁶ cm ⁻³ .

  The second columnar embedded layers 130 are formed in parallel at a fourth interval d4 that is equal to or less than the first interval d1. The second interval d4 can be set to 1.0 μm, for example. In the first embodiment, the second columnar embedded layers 130 are formed at equal intervals of the fourth interval d4. However, the second columnar embedded layers 130 may have different intervals as long as they are equal to or less than the first interval d1, for example, the peripheral breakdown voltage structure 120. You may form so that it may become short as it leaves | separates.

  In addition, the interval between the second columnar embedded layer closest to the peripheral breakdown voltage structure 120 in the second columnar embedded layer 130 and the peripheral breakdown voltage structure 120 is a third interval d3 that is narrower than the first interval d1. Further, the depth positions of the bottom portions of the second columnar embedded layers 130 are all the same depth and are formed to be equal to the depth positions of the bottom portions of the conductive material layer 126. The third distance d3 is, for example, 1.0 μm. Further, the depth of the bottom of the second columnar embedded layer 130 is, for example, 5.5 μm.

The peripheral insulating film 132 is made of an oxide film. The Schottky barrier metal layer 146 forms a Schottky junction with the n ⁻ type drift layer 114, and forms an ohmic junction with the columnar buried layer 118 and the conductive material layer 126. The material of the Schottky barrier metal layer 146 is, for example, platinum, and the thickness of the Schottky barrier metal layer 146 is, for example, 200 nm. The cathode electrode layer 150 is formed by depositing a metal (for example, nickel) as an electrode material on the back surface of the semiconductor substrate 110. The thickness of the cathode electrode layer 150 is, for example, 200 nm.

  As shown in FIG. 1C, the semiconductor device 100 according to the first embodiment also includes the columnar buried layer 118 inside the peripheral withstand voltage structure 120 in the direction along YY ′ in FIG. A second columnar buried layer 130 is formed outside the peripheral voltage withstanding structure 120.

2. Manufacturing Method of Semiconductor Device 100 According to Embodiment 1 Next, a manufacturing method of the semiconductor device 100 according to Embodiment 1 will be described along the following steps.
2 to 4 are views for explaining the method of manufacturing the semiconductor device according to the first embodiment. 2A to FIG. 2D, FIG. 3A to FIG. 3D, and FIG. 4A to FIG. 4D are process diagrams.

1. Semiconductor layer preparation step First, the ^{n +} -type semiconductor substrate 112, n was formed by epitaxial growth direction on the surface side of the ^{n +} -type semiconductor substrate 112 ^- preparing a semiconductor substrate 110 having a type drift layer 114 (FIGS. 2 (a) reference.). As the n ⁺ type semiconductor substrate 112, for example, a silicon substrate can be used, but a substrate made of silicon carbide SiC or gallium nitride GaN may be used.

2. Peripheral breakdown voltage structure forming step Next, the peripheral breakdown voltage structure 120 is formed. The peripheral breakdown voltage structure forming process includes a second trench forming process, an insulating film forming process, and a conductive material layer forming process.

2-1. Second Trench Formation Step In the peripheral breakdown voltage structure formation step, first, a ring-shaped second trench 122 is formed from the surface side of the n ⁻ type drift layer 114. Specifically, after forming a first insulating film 132 ′, which is a first insulating film, on the surface of the n ⁻ -type drift layer 114 by a thermal oxidation method or a CVD method, a resist film (thickness: 0.8 μm, for example) is not shown. .) And the photographic process is performed to provide an opening in the second trench formation portion, and the first insulating film 132 ′ in the opening is removed by dry etching. Next, the resist oxide film is removed, and then the n ⁻ -type drift layer 114 is dry-etched using the first insulating film 132 ′ as a mask, thereby forming the ring-shaped second trench 122 on the surface of the n ⁻ -type drift layer 114. It is formed (see FIG. 2B).

2-2. Insulating film forming step In the peripheral breakdown voltage structure forming step, the semiconductor substrate 110 is thermally oxidized after performing rounding while removing the damaged layer on the bottom and side surfaces of the second trench 122 by chemical dry etching or sacrificial oxidation. An insulating film 124 is formed inside the second trench 122 (see FIG. 2C). Note that although the insulating film 124 is formed by thermal oxidation here, it may be formed by a CVD method.

2-3. Conductive Material Layer Forming Step In the peripheral breakdown voltage structure forming step, next, a conductive material layer 126 is formed inside the second trench 122 via an insulating film 124. Specifically, the conductive material 126 ′ is deposited from the surface side of the n ⁻ -type drift layer 114 (see FIG. 2D). Thereafter, the conductive material layer 126 is formed by removing the conductive material located above the height position of the surface of the n ⁻ type drift layer 114 (see FIG. 3A). ).
The peripheral withstand voltage structure 120 is formed by the above-described peripheral withstand voltage structure forming process.

3. Embedded Layer Formation Step Next, the columnar embedded layer 118 is formed in the active region R1, and the second columnar embedded layer 130 is formed in the peripheral region R3. The buried layer forming step includes a first trench and a third trench forming step, and a columnar buried layer and a second columnar buried layer forming step.

3-1. First trench and third trench formation step In the first trench and third trench formation step, first, an oxide film serving as a trench mask is formed on the conductive material layer 126 by thermally oxidizing the conductive material ( (Refer FIG.3 (b)). The oxide film forms part of the first insulating film 132 ′. Subsequently, an unillustrated resist film (thickness: 0.8 μm, for example) is formed, and a photographic process is performed to provide openings at the formation positions of the columnar embedded layer and the second columnar embedded layer. The first insulating film 132 ′ in the opening is removed by dry etching. Next, the resist film is removed, and then the n ⁻ type drift layer 114 is dry-etched using the first insulating film 132 ′ as a mask, whereby the first trench 116 and the second trench 128 are formed on the surface of the n ⁻ type drift layer 114. (See FIG. 3C).

3-2. Columnar embedded layer and second columnar embedded layer forming step In the embedded layer forming step, the first trench is formed on the inner surfaces of the first trench 116 and the second trench 128 by chemical dry etching, sacrificial oxidation, hydrogen annealing, or the like. After removing the damaged layer by dry etching in the process, p-type single crystal silicon is epitaxially grown to a height position exceeding the height position of the surface of the first insulating film 132 ′ while introducing a dopant gas containing a p-type impurity. .
As a result, the active region R1 is filled with a columnar embedding comprising a main body portion 117 up to the height position of the surface of the first insulating film 132 ′ and a cap portion 119 which is a portion exceeding the height position of the surface of the first insulating film 132 ′. In addition to forming the buried layer 118 ′, the body portion 129 up to the height position of the surface of the first insulating film 132 ′ in the peripheral region R 3 and the cap portion 131 that is a portion beyond the height position of the surface of the first insulating film 132 ′. A second columnar buried layer 130 ′ is formed (see FIG. 3D).

4. CMP Step Next, the cap portions 119 and 131 formed in the buried layer forming step are polished and removed to the height position of the surface of the first insulating film 132 ′ by the CMP method (see FIG. 4A). .)

5. Peripheral Insulating Film Step Next, the main body portions 117 and 129 are removed to the height position of the surface of the n ⁻ type drift layer 114 by dry etching. Thereby, the columnar embedded layer 118 and the second columnar embedded layer 130 are formed (see FIG. 4B).
After that, the surfaces of the columnar buried layer 118 and the second columnar buried layer 130 exposed between the first insulating films 132 ′ are thermally oxidized to later form the peripheral insulating film 132 and the surface of the second columnar buried layer 130. An oxide film to be formed is formed. The oxide film forms part of the first insulating film 132 ′.
Thereafter, a resist film M is formed and a photographic process is performed to provide openings in predetermined portions of the entire active region R1 and the peripheral breakdown voltage region R2, and the first insulating film 132 ′ in the openings is dry-etched. Remove. At this time, the first insulating film 132 ′ remaining in the peripheral region R3 becomes the peripheral insulating film 132 (see FIG. 4C). Thereafter, the resist film M is removed.

6. Electrode formation process Next, a Schottky junction is formed with the n ⁻ type drift layer 114 and an ohmic junction is formed between the columnar buried layer 118 and the conductive material layer 126 in the opening provided in the peripheral insulating film process. The Schottky barrier metal layer 146 to be formed is formed, and the cathode electrode layer 150 is formed on the back surface side of the n ⁺ type semiconductor substrate 112 located on the back surface side of the semiconductor substrate 110 (see FIG. 4D).

  By sequentially performing the above steps, the semiconductor device 100 according to the first embodiment can be manufactured.

3. Effects of Semiconductor Device 100 According to First Embodiment According to the semiconductor device 100 according to the first embodiment, since the peripheral withstand voltage region 120 is provided in the peripheral withstand voltage region R2, the n ⁻ type drift layer 114 and the p-type columnar embedding are provided. In the case of the semiconductor device 900 according to the prior application, when the reverse bias is applied to the pn junction with the layer 118, the insulating film 124 of the peripheral withstand voltage structure 120 assumes most of the necessary withstand voltage. Similarly to the above, the breakdown voltage at the periphery of the element can be increased.

  Further, according to the semiconductor device 100 according to the first embodiment, since the so-called dummy columnar embedded layer (second columnar embedded layer) is disposed in the peripheral region R3, the active region R1 and the peripheral region R3 Therefore, the first insulating film 132 is not excessively etched in the vicinity of the peripheral withstand voltage region 120 during the CMP process (FIGS. 3D and 4A). As a result, the breakdown voltage at the periphery of the element is not reduced due to the CMP process.

  Furthermore, according to the semiconductor device 100 of the present invention, since the breakdown voltage is maintained not in the peripheral region R3 but in the peripheral breakdown voltage region R2, about 2-5 second columnar buried layers are sufficient. It is not necessary to provide several tens of second columnar buried layers as in the case of the conventional semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  For this reason, the semiconductor device 100 of the present invention can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the peripheral portion of the element. This results in a semiconductor device in which the breakdown voltage at the periphery of the element does not decrease.

  Further, according to the semiconductor device 100 according to the first embodiment, since the plurality of columnar embedded layers 118 are formed in parallel at the first interval d1, it is possible to prevent the electric field from concentrating on a specific portion. Thus, the depletion layer can be spread over a wide range. For this reason, it is possible to increase the breakdown voltage in the active region R1.

  In the semiconductor device 100 according to the first embodiment, the interval between the columnar embedded layer 118 closest to the peripheral breakdown voltage structure 120 and the peripheral breakdown voltage structure 120 among the plurality of columnar embedded layers 118 is greater than the first interval d1. Since the second interval d2 is narrow, the region sandwiched between the active region R1 and the peripheral breakdown voltage structure R2 can be reliably depleted during reverse bias.

  In the semiconductor device 100 according to the first embodiment, the interval between the second columnar embedded layer 130 closest to the peripheral breakdown voltage structure 120 and the peripheral breakdown voltage structure 120 is the third interval d3 that is narrower than the first interval d1. Therefore, it is possible to reliably deplete the region sandwiched between the peripheral withstand voltage region R2 and the peripheral region R3 during reverse bias.

  In addition, according to the semiconductor device 100 according to the first embodiment, as the second columnar embedded layer 130, two or more second columnar embedded layers 130 that are formed in parallel at a distance d4 that is equal to or less than the first distance d1. Therefore, the depletion layer can be extended to the outermost second columnar buried layer 130 among the plurality of second columnar buried layers 130 at the time of reverse bias, and the breakdown voltage around the element can be further increased. It becomes.

  Further, according to the semiconductor device 100 according to the first embodiment, since the depth position of the bottom portion of the columnar embedded layer 118 is equal to the depth position of the bottom portion of the conductive material layer 126, the plurality of columnar embedded layers 118 The bottom of the depletion layer extending downward can be smoothed, and the electric field does not concentrate on the bottom of the columnar buried layer and the bottom of the peripheral breakdown voltage structure during reverse bias. For this reason, the breakdown voltage from the active region R1 to the peripheral breakdown voltage region R2 can be increased.

  Further, according to the semiconductor device 100 according to the first embodiment, since the depth position of the bottom of the second columnar embedded layer 130 is equal to the depth position of the bottom of the conductive material layer 126, the peripheral withstand voltage structure 120 and the second The bottom of the depletion layer extending downward from the two-columnar buried layer 130 can be smoothed, and the electric field is not concentrated on the bottom of the second columnar buried layer and the bottom of the peripheral breakdown voltage structure during reverse bias. For this reason, the breakdown voltage from the peripheral breakdown voltage region R2 to the peripheral region R3 can be increased.

In addition, since the semiconductor device 100 according to the first embodiment is a high-breakdown-voltage semiconductor device having a super junction structure, it is possible to suppress an electric field from being concentrated on a specific portion of the semiconductor substrate 110, and a depletion layer is formed. It can be extended to an n ⁻ type drift layer and a columnar buried layer. Therefore, the breakdown voltage in the active region can be increased.

  Further, according to the semiconductor device 100 according to the first embodiment, the direction along YY ′ in FIG. 1A is the same as the direction along XX ′ in FIG. Since the second columnar buried layer 130 is formed outside the peripheral breakdown voltage structure 120, in the CMP process in which the cap portion formed in the process of forming the columnar buried layer is removed by the CMP method, Since the cap portion is also formed, as shown in FIG. 15B, the first insulating film 132 ′ is not excessively etched in the peripheral region R3. The withstand voltage is not reduced (see FIGS. 3D and 4A).

[Embodiment 2]
FIG. 5 is a diagram for explaining the semiconductor device 200 according to the second embodiment. FIG. 5A is a plan view of the semiconductor device 200 according to the second embodiment, FIG. 5B is a diagram illustrating a cross-sectional view taken along the line XX ′ in FIG. 5A, and FIG. It is a figure which shows the YY 'sectional drawing in Fig.5 (a). In FIG. 5A, as in the case of FIG. 1A, only the columnar embedded layer 218, the conductive material layer 226, and the second columnar embedded layer 230 are included for easy understanding. Show. In FIG. 5A, symbol GP indicates a gate pad.

  FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6A to FIG. 6D are process diagrams. Note that the steps shown in FIGS. 6A to 6B are the same as the steps shown in FIGS. 2A to 3D, so FIGS. 2B to 3C are used. The illustration of the steps shown is omitted. Also, the steps shown in FIGS. 6C to 6D are the same as those in the case of a general planar gate type MOSFET manufacturing method, and therefore between FIGS. 6C and 6D. Some processes are not shown.

  The semiconductor device 200 according to the second embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment. However, as shown in FIG. 5B, the semiconductor device is a planar gate type MOSFET. However, this is different from the case of the semiconductor device 100 according to the first embodiment. That is, as shown in FIG. 5B, the semiconductor device 200 according to the second embodiment includes a body region 234, a source region 236, a gate electrode structure 238 including a gate insulating film 240 and a gate electrode layer 242, and a source. This is a planar gate MOSFET having an electrode layer 246 and a drain electrode layer 250.

  As described above, the semiconductor device 200 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in that the semiconductor device is a planar gate type MOSFET, but is the same as the semiconductor device 100 according to the first embodiment. Therefore, the semiconductor device 100 has the same effect as the semiconductor device 100 according to the first embodiment.

That is, according to the semiconductor device 200 according to the second embodiment, as shown in FIG. 5B, since the peripheral breakdown voltage region R2 includes the peripheral breakdown voltage structure 220 described above, the n ⁻ type drift layer 214 and the p-type columnar shape are provided. When a reverse bias is applied to the pn junction with the buried layer 218, the insulating film 224 of the peripheral withstand voltage structure 220 assumes most of the required withstand voltage, and thus the semiconductor device 900 according to the prior application. As in the case of, the breakdown voltage at the periphery of the element can be increased.

  Further, according to the semiconductor device 200 according to the second embodiment, as shown in FIG. 5B, a so-called dummy columnar embedded layer (second columnar embedded layer 230) is disposed in the peripheral region R3. As a result, the active region R1 and the peripheral region R3 are not greatly different in surface structure, so that the first insulating film 232 is not excessively etched in the vicinity of the peripheral withstand voltage region 220 during the CMP process ( (See FIG. 6B and FIG. 6C.) As a result, the breakdown voltage at the periphery of the element is not reduced due to the CMP process.

  Furthermore, in the semiconductor device 200 according to the second embodiment, since the breakdown voltage is maintained in the peripheral breakdown voltage region R2 instead of the peripheral region R3, about 2 to 5 second columnar embedded layers are sufficient. There is no need to provide several tens of second columnar buried layers as in the case of the conventional semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  Therefore, the semiconductor device 200 according to the second embodiment can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the element peripheral portion, and the above-described CMP. A semiconductor device in which the breakdown voltage at the periphery of the element does not decrease due to the process is obtained.

  The semiconductor device 200 according to the second embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except that the semiconductor device is a planar gate type MOSFET, and thus the semiconductor according to the first embodiment. It has the same effect among the effects which the apparatus 100 has.

[Embodiment 3]
FIG. 7 is a diagram for explaining the semiconductor device 300 according to the third embodiment. FIG. 7A is a plan view of the semiconductor device 300 according to the third embodiment, FIG. 7B is a diagram showing a cross-sectional view taken along the line XX ′ in FIG. 7A, and FIG. It is a figure which shows YY 'sectional drawing in Fig.7 (a). In FIG. 7A, as in the case of FIG. 5A, only the columnar embedded layer 318, the conductive material layer 326, and the second columnar embedded layer 330 are included for easy understanding. Show. In FIG. 7A, symbol GP indicates a gate pad.

  FIG. 8 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment. 8A to 8D are process diagrams. Note that the steps shown in FIGS. 8A to 8B are the same as the steps shown in FIGS. 2A to 3D, and therefore, the steps shown in FIGS. 2B to 3C are performed. The corresponding steps are not shown. Further, the steps shown in FIGS. 8C to 8D are the same as those in the case of a general method for manufacturing a trench gate type MOSFET, and therefore, between FIGS. 8C and 8D. Some processes are not shown.

  The semiconductor device 300 according to the third embodiment basically has the same configuration as that of the semiconductor device 200 according to the second embodiment, but the semiconductor device is a trench gate type MOSFET as shown in FIG. 7B. This is different from the semiconductor device 200 according to the second embodiment. That is, as shown in FIG. 7B, the semiconductor device 300 according to the third embodiment includes a body region 334, a source region 336, a gate electrode structure 338 including a gate insulating film 340 and a gate electrode layer 342, and a source. This is a trench gate type MOSFET including an electrode layer 346 and a drain electrode layer 350.

  As described above, the semiconductor device 300 according to the third embodiment is different from the semiconductor device 200 according to the second embodiment in that the semiconductor device is a trench gate type MOSFET, but is the same as the semiconductor device 200 according to the second embodiment. Therefore, the semiconductor device 200 has the same effects as those of the semiconductor device 200 according to the second embodiment.

That is, according to the semiconductor device 300 according to the third embodiment, as shown in FIG. 7B, since the peripheral breakdown voltage region 320 is provided in the peripheral breakdown voltage region R2, the n ⁻ type drift layer 314 and the p-type columnar shape are provided. When a reverse bias is applied to the pn junction with the buried layer 318, the insulating film 324 of the peripheral withstand voltage structure 320 takes up most of the required withstand voltage, and thus the semiconductor device 900 according to the prior application. As in the case of, the breakdown voltage at the periphery of the element can be increased.

  Further, according to the semiconductor device 300 according to the third embodiment, as shown in FIG. 7B, a so-called dummy columnar embedded layer (second columnar embedded layer 330) is disposed in the peripheral region R3. As a result, the active region R1 and the peripheral region R3 are not greatly different in surface structure, so that the first insulating film 332 is not excessively etched in the vicinity of the peripheral withstand voltage region 320 during the CMP process. (Refer FIG.8 (b) and FIG.8 (c).). As a result, the breakdown voltage at the periphery of the element is not reduced due to the CMP process.

  Furthermore, in the semiconductor device 300 according to the third embodiment, since the breakdown voltage is maintained not in the peripheral region R3 but in the peripheral breakdown voltage region R2, about 2 to 5 second columnar embedded layers are sufficient. There is no need to provide several tens of second columnar buried layers as in the case of the conventional semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  For this reason, the semiconductor device 300 according to the third embodiment can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the peripheral portion of the element, and the above-described CMP. A semiconductor device in which the breakdown voltage at the periphery of the element does not decrease due to the process is obtained.

  Since the semiconductor device 300 according to the third embodiment has the same configuration as that of the semiconductor device 200 according to the second embodiment except that the semiconductor device is a trench gate type MOSFET, the semiconductor according to the second embodiment. It has the same effect among the effects which the apparatus 200 has.

[Embodiment 4]
FIG. 9 is a view for explaining the semiconductor device 400 according to the fourth embodiment. FIG. 9A is a plan view of the semiconductor device 400 according to the fourth embodiment, FIG. 9B is a diagram showing a cross-sectional view taken along the line XX ′ in FIG. 9A, and FIG. It is a figure which shows the YY 'sectional drawing in Fig.9 (a). In FIG. 9A, as in the case of FIG. 5A, only the columnar embedded layer 418, the conductive material layer 426, and the second columnar embedded layer 430 are provided for easy understanding. Show. In FIG. 9A, symbol GP indicates a gate pad.

  FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment. 10A to 10D are process diagrams. Note that the steps shown in FIGS. 10A to 10B are the same as the steps shown in FIGS. 2A to 3D, so FIGS. 2B to 3C are used. The corresponding steps are not shown. Also, the steps shown in FIGS. 10C to 10D are the same as those in the case of a general planar gate type IGBT manufacturing method, and therefore between FIGS. 10C to 10D. Some processes are not shown.

The semiconductor device 400 according to the fourth embodiment basically has the same configuration as that of the semiconductor device 200 according to the second embodiment. However, as shown in FIG. 9B, the semiconductor device is a planar gate type IGBT. This is different from the semiconductor device 200 according to the second embodiment. That is, as shown in FIG. 9B, the semiconductor device 400 according to the fourth embodiment includes a body region 434, an emitter region 436, a gate electrode structure 438 including a gate insulating film 440 and a gate electrode layer 442, and an emitter. The planar gate IGBT includes an electrode layer 446 and a collector electrode layer 450 and includes a p ⁺ type semiconductor layer 412 instead of the n ⁺ type semiconductor substrate 212 of the second embodiment.

  As described above, the semiconductor device 400 according to the fourth embodiment differs from the semiconductor device 200 according to the second embodiment in that the semiconductor device is a planar gate IGBT, but is the same as the semiconductor device 200 according to the second embodiment. Therefore, the semiconductor device 200 has the same effects as those of the semiconductor device 200 according to the second embodiment.

That is, according to the semiconductor device 400 according to the fourth embodiment, as shown in FIG. 9B, the peripheral breakdown voltage region R2 includes the peripheral breakdown voltage structure 420 described above, and therefore, the n ⁻ type drift layer 414 and the p-type columnar shape are provided. When a reverse bias is applied to the pn junction with the buried layer 418, the insulating film 424 of the peripheral withstand voltage structure 420 assumes most of the required withstand voltage. As in the case of, the breakdown voltage at the periphery of the element can be increased.

  Further, according to the semiconductor device 400 according to the fourth embodiment, as shown in FIG. 9B, a so-called dummy columnar embedded layer (second columnar embedded layer 430) is disposed in the peripheral region R3. Therefore, since the surface structure is not greatly different between the active region R1 and the peripheral region R3, the first insulating film 432 is not excessively etched in the vicinity of the peripheral withstand voltage region 420 during the CMP process ( (See FIG. 10B and FIG. 10C.) As a result, the breakdown voltage at the periphery of the element is not reduced due to the CMP process.

  Furthermore, in the semiconductor device 400 according to the fourth embodiment, since the breakdown voltage is maintained not in the peripheral region R3 but in the peripheral breakdown voltage region R2, about 2 to 5 second columnar embedded layers are sufficient. There is no need to provide several tens of second columnar buried layers as in the case of the conventional semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  Therefore, the semiconductor device 400 according to the fourth embodiment can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the element peripheral portion, and the above-described CMP. A semiconductor device in which the breakdown voltage at the periphery of the element does not decrease due to the process is obtained.

  The semiconductor device 400 according to the fourth embodiment has the same configuration as that of the semiconductor device 200 according to the second embodiment except that the semiconductor device is a planar gate type IGBT. It has the same effect among the effects which the apparatus 200 has.

[Embodiment 5]
FIG. 11 is a diagram for explaining the semiconductor device 500 according to the fifth embodiment. FIG. 11A is a plan view of the semiconductor device 500 according to the fifth embodiment, FIG. 11B is a diagram illustrating a cross-sectional view taken along the line XX ′ in FIG. 11A, and FIG. It is a figure which shows the YY 'sectional drawing in Fig.11 (a). In FIG. 11A, as in the case of FIG. 9A, only the columnar embedded layer 518, the conductive material layer 526, and the second columnar embedded layer 530 are provided for easy understanding. Show. In FIG. 11A, symbol GP indicates a gate pad.

  FIG. 12 is a view for explaining the method for manufacturing the semiconductor device according to the fifth embodiment. 12A to 12D are process diagrams. Note that the steps shown in FIGS. 12A to 12B are the same as the steps shown in FIGS. 2A to 3D, so FIGS. 2B to 3C are used. The corresponding steps are not shown. Further, the steps shown in FIGS. 12C to 12D are the same as those in the case of a general trench gate type IGBT manufacturing method, and therefore between FIGS. 12C to 12D. Some processes are not shown.

  The semiconductor device 500 according to the fifth embodiment basically has the same configuration as the semiconductor device 400 according to the fourth embodiment, but the semiconductor device is a trench gate type IGBT as shown in FIG. 11B. This is different from the semiconductor device 400 according to the fourth embodiment. That is, as shown in FIG. 11B, the semiconductor device 500 according to the fifth embodiment includes a body region 534, an emitter region 536, a gate electrode structure 538 including a gate insulating film 540 and a gate electrode layer 542, and an emitter. A trench gate type IGBT is provided with an electrode layer 546 and a collector electrode layer 550.

  As described above, the semiconductor device 500 according to the fifth embodiment is different from the semiconductor device 400 according to the fourth embodiment in that the semiconductor device is a trench gate type IGBT, but is the same as the semiconductor device 400 according to the fourth embodiment. Therefore, the semiconductor device 400 has the same effect as the semiconductor device 400 according to the fourth embodiment.

That is, according to the semiconductor device 500 according to the fifth embodiment, as shown in FIG. 11B, the peripheral breakdown voltage region R2 includes the peripheral breakdown voltage structure 520 described above, and therefore, the n ⁻ type drift layer 514 and the p-type columnar shape. When a reverse bias is applied to the pn junction with the buried layer 518, the insulating film 524 of the peripheral withstand voltage structure 520 assumes most of the required withstand voltage, and thus the semiconductor device 900 according to the prior application. As in the case of, the breakdown voltage at the periphery of the element can be increased.

  Further, according to the semiconductor device 500 of the fifth embodiment, as shown in FIG. 11B, a so-called dummy columnar embedded layer (second columnar embedded layer 530) is disposed in the peripheral region R3. Therefore, the active region R1 and the peripheral region R3 are not greatly different in surface structure, so that the first insulating film 532 is not excessively etched in the vicinity of the peripheral withstand voltage region 520 during the CMP process ( (See FIG. 12B and FIG. 12C.) As a result, the breakdown voltage at the periphery of the element is not reduced due to the CMP process.

  Furthermore, in the semiconductor device 500 according to the fifth embodiment, since the breakdown voltage is maintained not in the peripheral region R3 but in the peripheral breakdown voltage region R2, about 2 to 5 second columnar embedded layers are sufficient. There is no need to provide several tens of second columnar buried layers as in the case of the conventional semiconductor device 800, and the peripheral region can be reduced while increasing the breakdown voltage at the periphery of the element.

  Therefore, the semiconductor device 500 according to the fifth embodiment can manufacture a semiconductor device having a structure capable of reducing the area of the peripheral region while increasing the breakdown voltage at the element peripheral portion, and the above-described CMP. A semiconductor device in which the breakdown voltage at the periphery of the element does not decrease due to the process is obtained.

  The semiconductor device 500 according to the fifth embodiment has the same configuration as that of the semiconductor device 400 according to the fourth embodiment except that the semiconductor device is a trench gate type IGBT. It has the same effect among the effects which the apparatus 400 has.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) In each of the above embodiments, the high voltage semiconductor device of the present invention has been described by taking Schottky barrier diodes, MOSFETs and IGBTs as examples. However, the present invention is not limited to this. The present invention can be applied to any semiconductor device capable of forming a peripheral breakdown voltage structure in the peripheral breakdown voltage region.

(2) In each of the above embodiments, the present invention has been described by taking the case where the first conductivity type is n-type and the second conductivity type is p-type as an example, but the present invention is not limited to this. . For example, the present invention can be applied to the case where the first conductivity type is p-type and the second conductivity type is n-type.

(3) In each of the above embodiments, the invention of the present invention may be applied to a high breakdown voltage semiconductor device in which a p ⁺ type semiconductor region is further formed on the columnar buried layer. With such a configuration, it is possible to achieve good ohmic connection between the columnar buried layer and the anode electrode layer, source electrode layer, or emitter electrode layer.

100, 200, 300, 400, 500, 800, 900 ... Semiconductor layer device, 110, 210, 310, 410, 510, 810, 910 ... Semiconductor substrate, 112, 212, 312 ... n ⁺ type semiconductor substrate, 114, 214 , 314, 414, 514 ... n ^- type drift layer, 116, 216, 316, 416, 516 ... first trench, 117, 129, 217, 229, 317, 329, 417, 429, 517, 529 ... main body, 118, 118 ', 218, 218', 318, 318 ', 418, 418', 518, 518 ', 818, 918, 918' ... columnar buried layer, 119, 131, 219, 231, 319, 331, 419 , 431, 519, 531... Cap portion, 120, 220, 320, 420, 520, 920. , 522, 922 ... second trench, 124, 224, 324, 424, 524, 924 ... insulating film, 126, 226, 326, 426, 526, 926 ... conductive material layer, 128, 228, 328, 428, 528 ... Third trench, 130, 130 ', 230, 230', 330, 330 ', 430, 430', 530, 530 '... Second columnar buried layer, 132, 232, 332, 432, 532, 832, 932 ... peripheral insulating film, 132 ', 232', 332 ', 432', 532 ', 932' ... first oxide film, 146, 846, 946 ... Schottky barrier metal layer, 150, 850, 950 ... cathode electrode layer, 234, 334, 434, 534 ... body region, 236, 336 ... source region, 238, 338, 438, 538 ... gate electrode structure, 240, 340, 4 40, 540 ... gate insulating film, 242, 342, 442, 542 ... gate electrode layer, 244, 344, 444, 544 ... interlayer insulating film, 246, 346 ... source electrode layer, 250, 350 ... drain electrode layer, 316a, 516a ... 4th trench, 412, 512 ... p ⁺ type semiconductor layer, 436, 536 ... emitter region, 446, 546 ... emitter electrode layer, 450, 550 ... collector electrode layer, R1 ... active region, R2 ... peripheral breakdown voltage region, R3 ... Peripheral area

Claims (13)

A first conductivity type semiconductor layer;
A plurality of columnar buried layers made of a second conductivity type semiconductor material formed by epitaxial growth inside a first trench formed in an active region of the semiconductor layer;
A ring-shaped second trench formed in a peripheral pressure-resistant region surrounding the active region, an insulating film formed on an inner surface of the second trench, and a conductive material layer formed in the second trench via the insulating film. A peripheral withstand voltage structure that depletes the semiconductor layer in a portion sandwiched between the conductive material layer and the columnar buried layer at the time of reverse bias;
To manufacture a semiconductor device including one or more second columnar buried layers made of a second conductivity type semiconductor material formed by epitaxial growth inside a third trench formed in a peripheral region surrounding the peripheral breakdown voltage region. A method of manufacturing a semiconductor device, comprising:
A semiconductor layer preparation step of preparing a semiconductor layer of the first conductivity type,
A peripheral breakdown voltage structure forming step of forming the peripheral breakdown voltage structure in the peripheral breakdown voltage region;
The first trench and the third trench are formed in the active region and the peripheral region, respectively, using a first insulating film having a predetermined pattern formed on the surface of the semiconductor layer as a mask, and the first trench and the third trench are formed. by epitaxially growing a second conductivity type semiconductor material to a height greater than the height position of the surface of the first insulating film therein, the said peripheral region so as to form the columnar buried layer in the active region first A buried layer forming step of forming a two-columnar buried layer;
A semiconductor device which comprises a CMP process for removing by polishing by CMP to a height position of the surface of the first insulating film using the columnar buried layer and said second columnar buried layer in this order Production method. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device , wherein the semiconductor layer, the plurality of columnar embedded layers, and the one or more second columnar embedded layers are made of single crystal silicon. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The plurality of columnar embedded layers are each formed in parallel at a first interval,
A method of manufacturing a semiconductor device, wherein an interval between a columnar embedded layer closest to the peripheral breakdown voltage structure and the peripheral breakdown voltage structure among the plurality of columnar embedded layers is narrower than the first interval. In the manufacturing method of the semiconductor device according to claim 3,
A distance between the second columnar embedded layer closest to the peripheral breakdown voltage structure and the peripheral breakdown voltage structure among the one or more second columnar embedded layers is narrower than the first interval. Manufacturing method . In the manufacturing method of the semiconductor device according to claim 4,
A method of manufacturing a semiconductor device , comprising: two or more second columnar buried layers formed in parallel at intervals equal to or less than the first interval as the second columnar buried layers. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein a depth position of a bottom portion of the columnar embedded layer is equal to a depth position of a bottom portion of the conductive material layer. In the manufacturing method of the semiconductor device in any one of Claims 1-6,
A method of manufacturing a semiconductor device, wherein a depth position of a bottom portion of the second columnar embedded layer is equal to a depth position of a bottom portion of the conductive material layer. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a Schottky barrier diode. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a planar gate type MOSFET. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is characterized in that it is a trench gate type MOSFET. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a planar gate type IGBT. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a trench gate type IGBT. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a super junction structure.

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