JP5708508B2 - Semiconductor device simulation method - Google Patents

Description

  The present invention relates to a simulation method for a semiconductor device including a main element composed of a lateral element such as an LDMOS and a sense element arranged adjacent to the main element.

  Conventionally, in a temperature detection circuit and a current mirror circuit in which an LDMOS having a mesh structure in which drains and sources are arranged in a mesh shape (lattice shape) is used as a main element, the planar layout of the LDMOS is generally rectangular. (For example, see Patent Documents 1 and 2). A temperature detection element or a current detection sense element, which is a sense element, is arranged at a predetermined distance from the LDMOS whose planar layout is rectangular. Thus, by arranging the sense element adjacent to the LDMOS, the influence of variations in element characteristics is reduced.

JP 2001-308195 A JP-A-10-256541

  Since the LDMOS with a mesh structure is proportional to the number of drains, the modeling is performed based on the number of drains. However, in actuality, the characteristics depend on the state of adjacent source cells, that is, how many drains are in contact with each other. There is a difference. For this reason, if a simulation is performed with all the drains having the same characteristics, a simulation error occurs. In particular, in a small-sized LDMOS, a simulation error becomes remarkable, which hinders design.

  The characteristics of the main element are the center of gravity of the main element (meaning the position of the center of gravity of the top surface of the main element, and the center of the center of the element is the center of gravity if it is rectangular) based on the device pairability. It changes as the center. For this reason, if the layout is such that the sense element is arranged adjacent to the rectangular main element, the distance from the center of gravity of the main element to the center of gravity of the sense element is increased, resulting in variations in element characteristics. In addition, a temperature gradient is also generated. Therefore, there is a problem that an error occurs in the characteristics of the sense element, for example, an error in temperature detection or current detection, and a characteristic error (simulation error) with a design value such as a temperature detection circuit or a current mirror circuit becomes obvious.

  In view of the above points, it is a first object of the present invention to suppress a simulation error and perform a highly accurate simulation in a semiconductor device having a mesh structure. A second object is to make it difficult for errors to occur in the characteristics of the sense element.

  In order to achieve the above object, according to the first aspect of the present invention, the type of each second semiconductor region (5) arranged in a mesh shape is the second semiconductor region (5) adjacent to the second semiconductor region (5). Each of the first semiconductor regions (3) interspersed with one semiconductor region (3) is identified as one cell, and the type of the first semiconductor region (3) of each cell is defined as one cell. According to the type of the second semiconductor region (5) adjacent to the first semiconductor region (3), the cells have the same characteristics for each type of layered, The simulation is performed by setting a simulation model in which horizontal elements having different characteristics for each type of stratification are connected in parallel.

  Thus, in the setting of the simulation model, the scattered first semiconductor regions (3) are stratified according to the types of the second semiconductor regions (5) adjacent to the first semiconductor regions (3), and the characteristics differ by the number of stratified types. The horizontal element is treated as existing. For this reason, it is possible to perform a simulation in which a characteristic difference is taken into account, and a simulation error can be suppressed and a highly accurate simulation can be performed.

  In this case, as described in claim 2, the cell size for each type can be defined by setting the simulation model with the cell size for each type classified into layers as the number of cells for each type.

In the third aspect of the present invention, the main element (T1) has an O shape with a square central portion removed, and a top surface layout in which the sense elements (T2, S1) are arranged in the center of the O shape. It is a feature. According to a fourth aspect of the present invention, the main element (T1) has a U shape in which a concave portion is formed on one side of a square shape, and a top surface layout in which the sense elements (T2, S1) are arranged in the concave portion. It is a feature. Similarly, in the invention according to claim 5, the main element (T1) and a square-shaped corner portion and Losing was L-shaped, and layout plan of arranging the sensing element (T2, S1) with one corner section the It is characterized by that.

  By using these top surface layouts, variations in element characteristics can be suppressed, and temperature gradients can also be suppressed. Therefore, it is possible to suppress an error in the characteristics of the sense elements (T2, S1), that is, an error in current detection or temperature detection, and to suppress a characteristic error (simulation error) from a design value of the current mirror circuit, the temperature detection circuit, or the like. It becomes possible.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a top layout view of a semiconductor device according to a first embodiment of the present invention. It is A-A 'sectional drawing of FIG. FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1. It is a top surface layout view of a conventional semiconductor device. It is the figure which showed the example of the upper surface layout of LDMOS in which a simulation model is set. FIG. 6 is a schematic diagram illustrating a simulation model setting method in the upper surface layout example of FIG. 5. It is explanatory drawing which showed the setting method of the simulation model. It is the figure which showed the example of modeling. It is a top surface layout diagram of a semiconductor device concerning a 2nd embodiment of the present invention. It is a top surface layout view of a conventional semiconductor device. It is a top surface layout view of a semiconductor device explained in other embodiments.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
FIG. 1 is a top layout view of the semiconductor device according to the present embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is a circuit diagram of the semiconductor device shown in FIG.

  The semiconductor device shown in FIGS. 1 to 3 includes an LDMOS having the same structure as the main element T1 and the current detecting sense element T2.

As shown in FIG. 1, the LDMOS constituting the main element T1 and the current detecting sense element T2 are formed in the same chip. As shown in FIG. 2, in this embodiment, the n-type made of a semiconductor such as silicon is used. It is formed on the semiconductor substrate 1. The n-type semiconductor substrate 1 forms a drift layer and is configured with a predetermined impurity concentration. An insulating film 2 made of a LOCOS oxide film is formed on the surface of the n-type semiconductor substrate 1. An n ⁺ -type drain region 3 having a higher concentration than that of the n-type semiconductor substrate 1 is formed on the surface layer portion of the n-type semiconductor substrate 1 so as to be in contact with the insulating film 2.

A p-type base region 4 is formed in the surface layer portion of the n-type semiconductor substrate 1. The p-type base region 4 terminates in the vicinity of the end of the insulating film 2, and a deep base is configured by being partially deepened. On the surface layer portion of the p-type base region 4, an n ⁺ -type source region 5 is formed so as to be separated from the insulating film 2, and a p ⁺ -type contact region 6 is formed. The p ⁺ -type contact region 6 is arranged on the opposite side of the n ⁺ -type drain region 3 with the n ⁺ -type source region 5 interposed therebetween.

A gate insulating film 7 is disposed on the surface of the p-type base region 4 sandwiched between the n ⁺ -type source region 5 and the n ⁺ -type drain region 3, and doped Poly-Si is formed on the gate insulating film 7. The gate electrode 8 comprised by the above is provided. With such a configuration, the surface layer portion of the p ⁺ type base region 4 located below the gate electrode 8 is used as a channel region, and the MOS operation is performed using the n type semiconductor substrate 1 as a drift layer.

An interlayer insulating film 9 is disposed so as to cover the gate electrode 8, and the source electrode 10 and the drain electrode 11 are patterned on the interlayer insulating film 9. The source electrode 10 is connected to the n ⁺ -type source region 5 and the p ⁺ -type contact region 6 and the drain electrode 11 is connected to the n ⁺ -type drain region 3 through contact holes formed in the interlayer insulating film 9. ing. Although not shown, the LDMOS is configured by covering the surface of the SOI substrate with a protective film or the like so as to cover the source electrode 10 and the drain electrode 11 and the like. The LDMOS has the same cross-sectional structure in both the main element T1 and the current detecting sense element T2. As shown in FIG. 3, the gate electrodes 8 are electrically connected and the n ⁺ -type drains are mutually connected. The region 3 is electrically connected to constitute a current mirror circuit. Then, a current obtained by reducing the drain current flowing through the main element T1 at a predetermined ratio is caused to flow as the drain current of the current detecting sense element T2, and the drain current of the current detecting sense element T2 is detected. The circuit configuration can detect the drain current.

As shown in FIG. 1, the LDMOS configured as described above has a mesh structure in which n ⁺ -type drain regions 3 and n ⁺ -type source regions 5 are arranged in a mesh shape (lattice shape). In this embodiment, the LDMOS constituting the main element T1 is formed in an O shape (frame shape) from which the central portion of the square shape is removed, and the LDMOS constituting the current detecting sense element T2 is disposed in the central portion. The upper surface layout, that is, the current detection sense element T2 is surrounded by the main element T1. With such a structure, a semiconductor device including LDMOS as the main element T1 and the current detection sense element T2 is configured. By adopting such a top surface layout, the center of gravity of the main element T1 can be compared with the case where the current detecting sense element T2 is arranged adjacent to the conventional rectangular main element T1 as shown in FIG. It is possible to shorten the distance from the center of gravity of the current detection sense element T2. For this reason, variation in element characteristics can be suppressed, and a temperature gradient can also be suppressed. Therefore, an error in characteristics of the current detecting sense element T2, in the case of this embodiment, an error in current detection can be suppressed, and a characteristic error (simulation error) with a design value of the current mirror circuit or the like can be suppressed. .

In FIG. 1, the n ⁺ type drain region 3 is represented by “D”, and the n ⁺ type source region 5 is represented by “S”. As shown in FIG. 2, the n ⁺ -type drain region 3 and the n ⁺ -type source region 5 are arranged apart from each other. However, as a simulation model, each part (each lattice having a mesh shape as shown in FIG. 1) is used. ) In which one of the n ⁺ -type drain region 3 and the n ⁺ -type source region 5 is arranged.

  A simulation method in the semiconductor device including the LDMOS configured as described above will be described. However, the simulation method itself of the characteristics of the semiconductor device provided with the main element T1 and the current detection sense element T2 has been conventionally performed using an electric circuit simulator such as SPICE. In this embodiment, Since there is a feature in the setting method of the simulation model used for the simulation, the setting method of the simulation model will be described.

FIG. 5 is a diagram showing an upper surface layout example (Examples 1 to 3) of an LDMOS in which a simulation model is set. FIG. 6 is a diagram showing a state when the n ⁺ -type drain region 3 is stratified by the simulation model setting method of the present embodiment in the top surface layout example of FIG.

As shown in Examples 1 to 3 in FIG. 5, n ⁺ type source regions 5 are arranged around the scattered n ⁺ type drain regions 3, and the n ⁺ type drain regions 3 serve as n ⁺ type source regions. 5 is surrounded.

Conventionally, the n ⁺ -type drain regions 3 scattered in the mesh-like layout are all handled as having the same function. Specifically, each n ⁺ -type drain region 3 is regarded as one cell, the cell size is expressed by the number of cells (number of n ⁺ -type drain regions 3), and the characteristics of each cell are assumed to be the same. And modeling. Therefore, in Example 1 of FIG. 5, there are four n ⁺ -type drain regions 3, so the cell size is four. In Example 2, since there are six n ⁺ -type drain regions 3, the cell size is six, Since there are nine n ⁺ -type drain regions 3, the cell size is nine. Such modeling is performed in each of the main element T1 and the current detection sense element T2, and both the main element T1 and the current detection sense element T2 are regarded as LDMOS having a plurality of identical cells. Therefore, in the case of the circuit diagram, a current mirror circuit in which two LDMOSs are connected in parallel as shown in FIG. 3 is formed, which is a conventional simulation model.

On the other hand, in the present embodiment, each n ⁺ type drain region 3 is regarded as one cell and the cell size is set as in the conventional case, but the n ⁺ type drain region 3 is adjacent to it. The n ⁺ -type source region 5 is divided into layers according to the type. Then, the cells of the n ⁺ -type drain region 3 are distinguished for each type classified by layer. By such layering, as shown in FIG. 6, the n ⁺ -type drain region 3 is divided into different types of cells (cell “1”, cell “2”...).

  FIG. 7 is an explanatory diagram of the simulation model setting method described above. A specific simulation model setting method will be described with reference to FIG.

As shown in this figure, the type of the n ⁺ type source region 5 adjacent to the n ⁺ type drain region 3 is identified. That is, as shown in FIG. 7A, each n ⁺ type source region 5 is divided according to the number of n ⁺ type drain regions 3 adjacent to the n ⁺ type source region 5. Here, among the n ⁺ -type source regions 5, the number of adjacent n ⁺ -type drain regions 3 is 0 for “A”, 1 for “B”, and 2 for “C”. Three are classified as “D” and four are classified as “E”. Then, the breakdown of each n ⁺ type drain region 3 when the n ⁺ type source region 5 adjacent to the n ⁺ type drain region 3 is divided is examined, and each n ⁺ type drain region 3 is stratified based on the breakdown.

In the n ⁺ -type source region 5, the current from each n ⁺ -type drain region 3 is shared in accordance with the number of adjacent n ⁺ -type drain regions 3. ^It becomes easier for the current to flow than when the number of the ⁺ type drain regions 3 is small. For this reason, the n ⁺ -type source region 5 is assumed from the side number of adjacent and n ⁺ -type drain region 3 is less excellent in characteristics in order, the n ⁺ -type drain region 3, adjacent and n ^{The +} type source region 5 is ordered in descending order of the most excellent characteristics.

For example, as shown in the chart of FIG. 7B, among the n ⁺ type drain regions 3, the adjacent n ⁺ type source regions 5 are divided into three “B”, “C”, “ D "Two things are stratified into cell" 1 ". Further, among the n ⁺ -type drain regions 3, the adjacent n ⁺ -type source regions 5 are divided into three cells “B”, “C”, and “E” divided into cells “2”. To do. Among the n ⁺ -type drain regions 3, the adjacent n ⁺ -type source regions 5 are divided into two cells “B”, “C”, “D”, and “E”. Stratified into 3 ″. Similarly, the remaining n ⁺ -type drain region 3 is also divided into cells “4” to “6”. As a result, the n ⁺ -type drain region 3 can be classified by type based on the type of the adjacent n ⁺ -type source region 5.

When layering is performed by such a method, as shown in FIG. 7A, all of the n ⁺ -type drain regions 3 can be layered in Example 3. Similarly, when stratification is performed also in Example 1 and Example 2, each cell can be stratified in the form as shown in FIG.

When the n ⁺ -type drain region 3 is stratified in this way, each cell has the same characteristics for each type of stratification, but the n ⁺ -type drain region 3 has different characteristics for each type. Are handled and modeled. Accordingly, in the case of Example 1, since there are two n ⁺ type drain regions 3 of the cell “1”, the cell size is two, and two n ⁺ type drain regions 3 of the cell “2” are also two. Therefore, the cell size is two. In the case of Example 2, since all the n ⁺ type drain regions 3 of the cells “1” to “3” are two, the cell size is two. In the case of Example 3, since there is one n ⁺ type drain region 3 of the cell “1”, the cell size is one. Since there are two n ⁺ -type drain regions 3 of the cells “2” to “4”, the cell size is two. Further, since there are two n ⁺ -type drain regions 3 of the cells “5” and “6”, the cell size is two.

  FIGS. 8A and 8B are diagrams illustrating modeling examples. FIG. 8A is an upper surface layout diagram of an LDMOS to be modeled (corresponding to Example 3 in FIG. 5), and FIG. 8B is an upper surface layout of FIG. FIG. 6 is a circuit diagram after modeling of the LDMOS. Here, the case where it uses as a SPICE simulation model is demonstrated.

  In SPICE, various parameters of an LDMOS model are registered in advance, and when the model is designated, the parameters registered in advance of the model are read out and applied as LDMOS parameters for simulation. For example, as shown in Table 1, nm1, nm2, nm3, nm4, nm5, nm6... Are registered as models of Nch type MOS transistors, and various parameters (impurities) of transistors corresponding to each model are registered. A parameter list (level = 1...) That lists density, depth, etc.) is registered. Therefore, by designating a corresponding model from models registered in advance, the parameters of the designated model are read from the parameter list and used for simulation.

一方、上記したように図５の例３のような上面レイアウトにおいては、セル“１”〜セル“６”に区分けされたｎ⁺型ドレイン領域３がある。これらセル“１”〜セル“６”はそれぞれ別の特性を有したＬＤＭＯＳであると想定されるため、図７（ｂ）に示すような回路構成、つまりセル“１”〜セル“６”のＬＤＭＯＳ（これら各ＬＤＭＯＳをＭ１〜Ｍ６と表記する）が並列接続された構成となる。そして、このような回路構成において、図７（ｂ）中に示したように、Ｍ１についてはセルサイズＭ＝１、Ｍ２〜Ｍ４についてはセルサイズＭ＝２、Ｍ５およびＭ６についてはセルサイズＭ＝４として表す。これをＳＰＩＣＥでのシミュレーションモデルとして用いる。

On the other hand, as described above, in the top layout as in Example 3 of FIG. 5, there is an n ⁺ -type drain region 3 divided into cells “1” to “6”. Since these cells “1” to “6” are assumed to be LDMOS having different characteristics, the circuit configuration as shown in FIG. 7B, that is, the cells “1” to “6”. LDMOS (each of these LDMOSs is denoted as M1 to M6) is connected in parallel. In such a circuit configuration, as shown in FIG. 7B, the cell size M = 1 for M1, the cell size M = 2 for M2 to M4, and the cell size M = for M5 and M6. This is expressed as 4. This is used as a simulation model in SPICE.

For example, in SPICE, the LDMOS drain D, gate G, source V, and base B states are set, and the LDMOS model name is designated. For example, the drain voltage V _D , the gate voltage V _G , the source voltage V _S , the base voltage V _B corresponding to the substrate potential are set, and the LDMOS model name is designated as nm2. The channel length L, channel width W, drain capacitance (drain-base capacitance) AD, source capacitance (source-base capacitance) AS are set for each model, and the cell size is input. As a result, the input is made as shown in Table 2.

これにより、図７（ｂ）に示す回路構成についてＳＰＩＣＥによるシミュレーションが実行され、ＬＤＭＯＳのＤＣ特性、具体的にはドレイン電流Ｉ_Dとドレイン電圧Ｖ_Dとの特性であるＩ_D−Ｖ_D特性やドレイン電流Ｉ_Dとゲート電圧との特性であるＩ_D−Ｖ_G特性が導出される。同様に、シミュレーションにより、ＬＤＭＯＳの容量特性、具体的にはゲート−ソース間容量Ｃ_GSとゲートソース間電圧Ｖ_GSとの特性であるＣ_GS−Ｖ_GS特性やドレイン−ソース間容量Ｃ_DSとソース−ドレイン間電圧Ｖ_DSとの特性であるＣ_DS−Ｖ_DS特性、および、ゲート−ドレイン間容量Ｃ_GDとゲート−ドレイン間電圧Ｖ_GDとの特性であるＣ_GD−Ｖ_GD特性が導出される。

As a result, the SPICE simulation is performed on the circuit configuration shown in FIG. 7B, and the DC characteristics of the LDMOS, specifically, the I _D -V _D characteristics, which are the characteristics of the drain current I _D and the drain voltage V _D , I _D -V _G characteristics is a characteristic of the drain current I _D and the gate voltage is derived. Similarly, by simulation, the capacitance characteristics of the LDMOS, specifically, the C _GS -V _GS characteristic, which is a characteristic of the gate-source capacitance C _GS and the gate-source voltage V _GS , and the drain-source capacitance C _DS and the source -C _DS -V _DS characteristics that are characteristics with respect to the drain-drain voltage V _DS and C _GD -V _GD characteristics that are characteristics between the gate-drain capacitance C _GD and the gate-drain voltage V _GD are derived. .

In this way, the scattered n ⁺ -type drain regions 3 are classified according to the types of the n ⁺ -type source regions 5 adjacent thereto, and the number of layered n ⁺ -type drain regions 3 is set as the cell size. ing. Then, a simulation model is set that is handled as if there are LDMOSs having different characteristics by the number of stratified types. As a result, it is possible to set a simulation model that is close to actuality considering characteristics of the same LDMOS having different characteristics. For this reason, it is possible to perform a simulation in which a characteristic difference is taken into account, and a simulation error can be suppressed and a highly accurate simulation can be performed.

As described above, in the setting of the simulation model, the scattered n ⁺ type drain regions 3 are classified according to the types of the n ⁺ type source regions 5 adjacent thereto, and the layered n ⁺ type drain regions 3 are separated. Set the number of cells to the cell size. Then, it is assumed that there are LDMOSs having different characteristics by the number of types classified into layers. For this reason, it is possible to perform a simulation in which a characteristic difference is taken into account, and a simulation error can be suppressed and a highly accurate simulation can be performed.

  Further, the LDMOS that constitutes the main element T1 is configured in an O shape (frame shape), and the top surface layout in which the LDMOS that constitutes the current detection sense element T2 is arranged at the center, that is, the periphery of the current detection sense element T2 The structure is surrounded by the main element T1. By adopting such a top layout, variations in element characteristics can be suppressed, and temperature gradients can also be suppressed. Therefore, an error in characteristics of the current detecting sense element T2, in the case of this embodiment, an error in current detection can be suppressed, and a characteristic error (simulation error) with a design value of the current mirror circuit or the like can be suppressed. .

(Second Embodiment)
A second embodiment of the present invention will be described. This embodiment includes a temperature detection element S1 instead of the current detection sense element T2 as a sense element with respect to the first embodiment, and is otherwise the same as the first embodiment. Only portions different from the embodiment will be described.

  FIG. 9 is a diagram showing a top layout of the semiconductor device according to the present embodiment. As shown in this figure, in this embodiment, a temperature detection element S1 is provided as a sense element. The temperature detection element S1 is constituted by, for example, a diode connected in series, and detects the temperature of the LDMOS constituting the main element T1 based on the temperature of the diode Vf, in particular. Also in the present embodiment, the main element T1 is configured in an O shape (frame shape), and the top surface layout in which the temperature detection element S1 is arranged at the center, that is, the temperature detection element S1 is surrounded by the main element T1. With such a structure, a semiconductor device including the LDMOS that constitutes the main element T1 and the temperature detection element S1 is configured.

  By adopting such a top surface layout, the center of gravity of the main element T1 and the temperature detection are compared with the case where the temperature detection element S1 is arranged adjacent to the conventional rectangular main element T1 as shown in FIG. It is possible to shorten the distance from the center of gravity of the element S1. For this reason, variation in element characteristics can be suppressed, and a temperature gradient can also be suppressed. Therefore, the characteristic error of the temperature detection element S1, in the case of this embodiment, the temperature detection error can be suppressed, and the characteristic error (simulation error) with the design value of the temperature detection circuit and the like can be suppressed.

  Even in such a circuit configuration, the setting of the simulation model of the LDMOS constituting the main element T1 is performed by the same method as in the first embodiment. As a result, it is possible to set a simulation model that is close to actuality considering characteristics of the same LDMOS having different characteristics. For this reason, it is possible to perform a simulation in which a characteristic difference is taken into account, and a simulation error can be suppressed and a highly accurate simulation can be performed.

(Other embodiments)
In the first and second embodiments, the semiconductor device having the top surface layout in which the main element T1 is O-shaped has been described. However, other top surface layouts may be used. For example, as shown in FIGS. 11 (a) and 11 (b), the main element T1 has an L shape, that is, a shape in which one of four corners of a quadrangle is lost, and current detection is performed at the corner. A structure including the sense element T2 and the temperature detection element S1 can be employed. Further, as shown in FIGS. 11C and 11D, the main element T1 has a U shape, that is, a shape in which a recess is provided on one of the four sides of the quadrangle, and a current detection sense is provided in the recess. It is good also as a structure provided with element T2 and temperature detection element S1.

  In each of the above embodiments, the Nch type LDMOS has been described as an example. However, the same configuration as that of each of the above embodiments can be adopted for the Pch type LDMOS in which each conductivity type is inverted. Also in this case, by applying a simulation method using the same simulation model as in each of the above embodiments, it is possible to achieve the same effect as in each of the above embodiments. In each of the above embodiments, an example of the configuration of the LDMOS is shown, but it can be changed as appropriate. For example, the n-type semiconductor substrate 1 is used so that the n-type semiconductor substrate 1 functions as a drift layer. However, while using the p-type semiconductor substrate, the n-type semiconductor substrate 1 is ion-implanted by ion implantation or the like. It is also possible to form an LDMOS inside the drift layer. Furthermore, the present invention can be applied to a general lateral MOSFET that is not an LDMOS.

In addition, although the description has been given here taking the LDMOS as an example of the lateral element, the same applies to the simulation of the IGBT or the like in which the n ⁺ type drain region 3 in the LDMOS having the cross-sectional structure shown in FIG. 2 is changed to the p ⁺ type. I can say that. In the case of LDMOS, the n ⁺ type drain region 3 corresponds to the first semiconductor region, the n ⁺ type source region 5 corresponds to the second semiconductor region, the drain electrode 11 corresponds to the first electrode, and the source electrode 10 corresponds to the second electrode. In this case, the p ⁺ type collector region corresponds to the first semiconductor region, the n ⁺ type emitter region corresponds to the second semiconductor region, the collector electrode corresponds to the first electrode, and the emitter electrode corresponds to the second electrode. Of course, the IGBT is not limited to the Nch type but can be a Pch type element.

T1 main element T2 current detecting sense element S1 temperature detecting element 1 n-type semiconductor substrate 3 n ⁺ type drain region 4 p type base region 5 n ⁺ type source region 6 p ⁺ type contact region 7 gate insulating film 8 gate electrode 10 source Electrode 11 Drain electrode

Claims (5)

A semiconductor substrate (1) having a drift layer of a first conductivity type;
A second conductivity type base region (4) formed in the drift layer;
A first semiconductor region (3) of a first conductivity type or a second conductivity type formed in the drift layer so as to be separated from the base region (4);
A second semiconductor region (5) of the first conductivity type formed in the base region (4);
A first electrode (11) connected to the first semiconductor region (3);
A second electrode (10) connected to the second semiconductor region ( 5 );
A gate electrode (8) provided on the surface of the base region (4) via a gate insulating film (7);
The first semiconductor region (3) and the second semiconductor region (5) have a mesh structure in which the first semiconductor region (3) and the first semiconductor region (3) are interspersed. 3) is a top surface layout in which the second semiconductor region (5) is arranged around the periphery, and the gate insulating film (7) in the base region (4) is applied to the gate electrode (8) based on voltage application. A main element (T1) formed of a lateral element configured to form a channel region in a contact portion and to pass a current between the first electrode (11) and the second electrode (10);
A simulation method of a semiconductor device having sense elements (T2, S1) formed on the same chip as the lateral element,
The type of each of the second semiconductor regions (5) arranged in a mesh shape is identified according to the number of the first semiconductor regions (3) adjacent to the second semiconductor region (5). Each of the scattered first semiconductor regions (3) is defined as one cell, and the type of the first semiconductor region (3) of each cell is adjacent to the first semiconductor region (3). Layered according to the type of the second semiconductor region (5), and each cell has the same characteristics for each layered type. A simulation method for a semiconductor device, wherein simulation is performed by setting a simulation model in which horizontal elements having different characteristics are connected in parallel.   2. The simulation method for a semiconductor device according to claim 1, wherein the simulation model is set with the cell size of each stratified type as the number of cells of each type.   The main element (T1) has an O shape from which a square central portion is removed, and has a top layout in which the sense elements (T2, S1) are arranged in the center of the O shape. 3. A method for simulating a semiconductor device according to 2.   The main element (T1) has a U-shape in which a concave portion is formed on one side of a square shape, and has a top layout in which the sense element (T2, S1) is disposed in the concave portion. The simulation method of the semiconductor device as described. The main element (T1) and a square-shaped corner portion and Losing was L-shaped, according to claim 1 or 2, characterized in that said sensing element (T2, S1) layout plan which was placed on one corner the A method for simulating a semiconductor device according to claim 1.

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