JP5705593B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a metal silicide layer and a method for manufacturing the semiconductor device.

  In recent years, semiconductor devices have been rapidly miniaturized with higher integration. However, when the element is miniaturized, the diffusion layer resistance increases due to the shallow junction, and the contact resistance increases due to the reduction of the junction with the miniaturized element wiring. An increase in the diffusion layer resistance and contact resistance becomes an obstacle to high-speed operation.

  Therefore, there is a need for a technology that enables reduction of contact resistance and diffusion layer resistance corresponding to element miniaturization. A salicide process has been proposed as one of the techniques that can reduce the contact resistance and diffusion layer resistance.

  In the above salicide process, elements are separated by an insulating film such as a thermal oxide film, and then the diffusion layer of the semiconductor substrate and the surface of each electrode are exposed, and then, by sputtering or the like, titanium (Ti), molybdenum ( After depositing a metal such as Mo) or tungsten (W), a heat treatment is performed to form a metal silicide layer by siliciding the substrate diffusion layer portion and the surface portion of the electrode in each element by an alloying reaction. Is the method.

  A typical structure of a MOSFET formed by using the salicide process will be described with reference to the cross-sectional view of FIG. 7 by taking an N-channel MOSFET using a P-type substrate as an example. A P-type well 3 is formed along one main surface of the P-type semiconductor substrate 2 on which the element isolation region 1 is selectively formed. Source / drain regions 4 are formed in the P-type well 3 by diffusing low-concentration N-type impurities. Further, a high concentration source region 5 and a high concentration drain region 6 are formed in the source / drain region 4 by diffusing a high concentration N-type impurity. A gate electrode 8 is formed on the surface of the substrate via a gate oxide film 7. An insulating film 9 called a side wall is formed on the side wall of the gate electrode 8. A metal silicide layer 10 is formed on the surface of the high-concentration source region 5, the high-concentration drain region 6, and the gate electrode 8 to constitute a MOSFET. Here, since the structure after the electrode wiring (the formation process of the metal wiring and the protective film) after the formation of the metal silicide layer 10 is the same as that of a general semiconductor device, the detailed description is omitted.

  By adopting such a structure, the diffusion layer resistance and the contact resistance can be reduced. However, when the salicide process is used to form a metal silicide on the entire surface of the diffusion layer and each electrode, stress such as stress is generated in the metal silicide forming portion due to the following (a) and (b).

  (A) Inconsistency between the underlying silicon and the metal silicide formed on the silicon.

  (B) Volume change due to difference in lattice constant before and after alloying reaction.

  When stress such as stress increases on the diffusion layer and each element electrode, there is a problem that the characteristics of the element change and the PN junction is destroyed.

  In response to this problem, by using metal halide gas as a metal raw material by CVD, it is possible to form metal silicide at low temperature, and by not performing alloying reaction by high-temperature heat treatment, lattice before and after alloying reaction A technique for relieving stress resulting from a difference in constant is disclosed (for example, see Patent Document 1).

JP-A-7-94446

  However, in the manufacturing method described in Patent Document 1, stress due to the cause described in (b) above is relieved, but stress relaxation due to poor alignment between silicon and metal silicide described in (a) is not caused. However, reliability degradation due to stress such as stress is also a problem.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that prevent deterioration of reliability such as element characteristic variation and PN junction breakdown due to stress such as stress on a metal silicide formation surface. is there.

  In order to solve the above problems, the present invention uses the following means.

  First, a semiconductor device having a salicide structure is characterized in that the metal silicide formed on the high-concentration source / drain regions and the surface of the gate electrode is composed of a plurality of island-like metal silicides.

  The island-shaped metal silicide is a semiconductor device having a space without metal silicide between adjacent island-shaped metal silicides.

  The island-shaped metal silicide is a semiconductor device that is circular or polygonal in plan view.

Further, the island-like metal silicide, titanium (Ti), molybdenum (Mo), tungsten (W), nickel (Ni), cobalt (Co), chromium (Cr), platinum (Pt), palladium (Pd), tantalum A semiconductor device made of any one of (Ta) and silicon (Si) was used.

  Then, in the manufacture of the semiconductor device, a step of forming a high concentration source / drain region and a gate electrode having a sidewall on the side wall on the semiconductor substrate, and a surface of the high concentration source / drain region and the gate electrode surface are formed. A method of manufacturing a semiconductor device, comprising: forming a partially opened silicon oxide; and forming a plurality of island-like metal silicides on the surface of the high concentration source / drain regions and the surface of the gate electrode using the silicon oxide as a mask. It was.

  According to the present invention, by forming the island-like metal silicide layer only in the contact region, the stress on the surface where the metal silicide is formed is relieved, and the device characteristics change due to stress such as stress and the reliability such as PN junction breakdown It becomes possible to prevent deterioration.

It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention. FIG. 2 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the invention following FIG. 1; FIG. 3 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the invention following FIG. 2; FIG. 4 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the invention following FIG. 3; It is the typical sectional view and the top view showing the shape of the metal silicide layer in the semiconductor device concerning the present invention. It is typical sectional drawing and the top view which show the shape of the metal silicide layer in the conventional semiconductor device. It is sectional drawing which shows the structure of MOSFET formed by the conventional salicide process.

  Hereinafter, embodiments of the present invention will be described in detail.

  FIG. 1A to FIG. 4B are process cross-sectional views for explaining a method for manufacturing a semiconductor device of the present embodiment. In this embodiment, for simplicity of explanation, an N-channel LDDMOSFET using a P-type substrate will be described as an example. However, the essence of the present invention relates to the conductivity type, impurity type, and conductivity type of the substrate. Therefore, the same explanation can be made even when the conductivity type, impurity type, and conductivity type of the substrate are different. In the present embodiment, an LDD (Lightly Doped Drain) MOSFET will be described as an example. However, the present invention may be applied to other types of MOSFETs, capacitance elements, diffusion layers in resistance elements, and electrodes. A similar effect can be obtained.

  The structure and manufacturing method of the semiconductor device of this embodiment will be described below with reference to the process cross-sectional views shown in FIGS. 1 (a) to 4 (b).

  First, as shown in FIG. 1A, an element isolation region 12 is formed on a P-type semiconductor substrate 11 by a LOCOS method using an existing element isolation technique.

Next, as shown in FIG. 1B, the P-type well region 13 is passed through a sacrificial oxide film (not shown) of about 500 mm along one main surface on the P-type semiconductor substrate 11. It is formed by introducing a P-type impurity having a dose of 5 × 10 ¹² to 1 × 10 ¹³ atoms / cm ² and heat treatment.

Next, as shown in FIG. 1C, a gate oxide film 14 of about 400 mm is formed on the surface of the P-type well region 13 by thermal oxidation, and then a polysilicon film (about 2800 mm) is formed on the gate oxide film. (Not shown) is deposited on the entire surface of the substrate by CVD, ion-implanted with N-type impurities of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms / cm ² , heat-treated, and further etched to form a gate electrode 15 is formed.

Next, as shown in FIG. 2A, using the gate electrode 15 as a mask, a low-concentration source / drain region 16 is interposed in the P well region 13 through a sacrificial oxide film (not shown) of about 500 mm. It is formed by introducing an N-type impurity having a dose of 2 × 10 ^{12 to} 6 × 10 ¹² atoms / cm ² and heat treatment.

  Next, as shown in FIG. 2B, a silicon oxide film (not shown) of about 2200 mm is deposited on the side surface of the gate electrode 15 by CVD, and etched to form the insulating film 17 on the side wall. Form as.

Next, as shown in FIG. 2C, the gate electrode 15 and the insulating film 17 are used as a mask to form a high concentration source / drain region 18 in a sacrificial oxide film (about 500 mm) in the low concentration source / drain region 16. (Not shown) through introduction of an N-type impurity having a dose of 3 × 10 ^{15 to} 5 × 10 ¹⁵ atoms / cm ² and heat treatment.

  Next, a process for forming a metal silicide will be described. As shown in FIG. 3A, a silicon oxide film 19 of about 500 mm is formed on the semiconductor substrate 11.

  Next, as shown in FIG. 3B, the silicon oxide film 19 is patterned and etched to partially expose the silicon in the region where the metal silicide is to be formed. The silicon oxide located on the surface of the high concentration source / drain region 18 and the gate electrode 15 is partially removed by opening so that the surface of the high concentration source / drain region 18 and the surface of the gate electrode are partially exposed. The planar shape of the exposed region at this time will be described later.

Next, as shown in FIG. 4A, on the semiconductor substrate 11 on which the silicon oxide film 19 is partially etched, for example, titanium (Ti), molybdenum (Mo), tungsten (W) of about 350 mm. by nickel (Ni), cobalt (Co), chromium (Cr), platinum (Pt), palladium (Pd), the metal film 20 of tantalum (Ta) or the like formed by sputtering, heat treatment, alloying A metal silicide layer 21 is formed by reaction. At this time, a metal silicide layer 21 made of the metal and silicon of the semiconductor substrate is formed on the surface of the region where the silicon oxide film 19 has been removed by the previous etching.

  Next, the unreacted metal film 20 that has not become metal silicide by the alloying reaction is removed by wet etching. FIG. 4B shows a cross section when the silicon oxide film 19 used as a silicidation mask is removed after the unreacted metal film is removed.

  Since the structure after the electrode wiring after forming the metal silicide layer 21 (the formation process of the metal wiring and the protective film) and the manufacturing method are the same as those of a general semiconductor device, a detailed description is omitted.

  The above is the semiconductor device and the method for manufacturing the semiconductor device of this embodiment.

  Although the present embodiment has been described with specific examples, various conditions and the like can be changed without departing from the scope of the present invention.

  The greatest feature of this embodiment is that metal silicide is selectively formed using a silicon oxide film as a mask in the formation of metal silicide in the salicide process.

  Next, the shape of the metal silicide will be described with reference to FIGS.

  FIG. 6 is a schematic cross-sectional view and a plan view showing the shape of the metal silicide layer 25 formed on the surface of the high concentration diffusion layer in the conventional semiconductor device. This figure is a diagram in which the source region or drain region of FIG. 7 which is a conventional semiconductor device is extracted, with the bottom being a cross-sectional view and the top being a plan view. A metal silicide 25 is formed on the entire surface of the high-concentration diffusion layer 24 (corresponding to the source region 5 or the drain region 6 in FIG. 7). The same applies to the gate electrode, and the entire upper surface of the gate electrode is covered with metal silicide. However, the side surface of the gate electrode is hindered by the sidewall, and no metal silicide is formed. On the other hand, in the present invention, as shown in FIG. 5, the metal silicide layer 23 formed on the surface of the high concentration diffusion layer 22 (corresponding to the high concentration source / drain region 18 in FIG. It is formed from a circular island. That is, a plurality of island-like metal silicides are formed on the surface of the high concentration diffusion layer 22. Similarly, a plurality of island-like metal silicides are formed on the gate electrode. The shape of the island-like metal silicide is not limited to a circle, but may be a polygon. The number of island-like metal silicides in the source region, drain region, and gate electrode surface can be changed as appropriate. In addition, the space width between the islands can be controlled, and thereby good contact resistance can be obtained.

  In the semiconductor device according to the present invention, since the island-shaped metal silicide is divided, the source region, the drain region, and the gate electrode surface do not warp due to stress. This is because there is a space without metal silicide between the islands.

  By adopting such a structure, in the semiconductor device of the present invention, it is possible to prevent deterioration in reliability such as element characteristic fluctuation and PN junction breakdown due to stress such as stress.

DESCRIPTION OF SYMBOLS 1 Element isolation region 2 P type semiconductor substrate 3 P type well region 4 Low concentration source / drain region 5 High concentration source region 6 High concentration drain region 7 Gate oxide film 8 Gate electrode 9 Insulating film 10 Metal silicide layer 11 P type semiconductor substrate 12 element isolation region 13 P-type well region 14 gate oxide film 15 gate electrode 16 low concentration source / drain region 17 insulating film 18 high concentration source / drain region 19 silicon oxide film 20 metal film 21 metal silicide layer 22 high concentration diffusion layer 23 Metal silicide layer 24 High-concentration diffusion layer 25 Metal silicide layer

Claims (6)

A salicide structure semiconductor device,
A semiconductor substrate;
A gate electrode provided on the semiconductor substrate via a gate oxide film and having sidewalls on sidewalls;
High concentration source / drain regions disposed on both sides of the gate electrode;
Metal silicide formed on the surface of the high concentration source / drain region and the gate electrode;
Have
The metal silicide is a semiconductor device comprising a plurality of island-like metal silicides.   The semiconductor device according to claim 1, wherein the island-shaped metal silicide has a space having no metal silicide between adjacent island-shaped metal silicides.   The semiconductor device according to claim 2, wherein the island-shaped metal silicide is circular or polygonal in plan view. Said island-shaped metal silicide, titanium (Ti), molybdenum (Mo), tungsten (W), nickel (Ni), cobalt (Co), chromium (Cr), platinum (Pt), palladium (Pd), and tantalum 4. The semiconductor device according to claim 1, wherein the semiconductor device comprises one of elements selected from the group consisting of (Ta) and silicon (Si). 5. A method of manufacturing a salicide structure semiconductor device comprising:
Forming a gate electrode having a sidewall on a sidewall on a semiconductor substrate;
Forming high concentration source / drain regions on both sides of the gate electrode;
Forming a silicon oxide film partially opened on the surface of the high concentration source / drain region and the surface of the gate electrode;
Forming a plurality of island-like metal silicides on the surface of the high concentration source / drain region and the surface of the gate electrode using the silicon oxide film as a mask;
A method for manufacturing a semiconductor device comprising: After the step of forming the plurality of island-like metal silicides,
Removing unreacted metal film that has not become metal silicide by wet etching;
Removing the silicon oxide film used as the mask;
A method for manufacturing a semiconductor device according to claim 5, comprising:

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