JP5704012B2 - Processor and control method of processor - Google Patents

Description

  The present invention relates to a processor and a method for controlling the processor.

  The vector processor executes a load / store instruction for reading data from the data memory and an operation processing instruction for the read data in parallel by a plurality of pipelines to perform high-speed vector operations. A method for avoiding access conflict to the same memory in a plurality of load / store instructions has been proposed. For example, Patent Documents 1 to 3 describe the avoidance of contention in memory access. In one example, access to the memory bank is controlled in a bank interleave manner. In the bank interleaving method, a storage area having continuous addresses is divided into a plurality of banks, and access to continuous addresses is performed with a time shift for each bank.

  However, even if the bank interleaving method is adopted, bank conflicts occur in which a plurality of load / store instructions compete for access to the same bank. Therefore, in order to avoid bank conflict, a method for avoiding bank conflict by delaying (stalling) issuance of any of the competing instructions has been proposed.

JP-A-6-162064 JP-A-9-305487 JP 2008-135813 A

  However, frequent stalls are problematic because processing efficiency is reduced.

  Accordingly, an object of the present invention is to provide a processor having a plurality of pipelines, which can avoid bank conflicts without reducing processing efficiency, and a control method therefor.

  In one embodiment for achieving the above object, a processor includes: a first processing unit that accesses a plurality of banks of memory in a first bank access order; and a start of access of the first processing unit. When a second processing unit that starts accessing the plurality of banks in a second bank access order and access to the plurality of banks by the first processing unit and the second processing unit compete with each other, A control unit that rearranges the second bank access order into a third bank access order that does not cause the contention and causes the second processing unit to access the plurality of banks.

  According to the embodiment described below, bank contention can be avoided without reducing processing efficiency in a processor having a plurality of pipelines.

It is a figure for demonstrating the structure of the processor in this embodiment. It is a figure which shows the structure of a data memory typically. It is a figure explaining a vector register. It is a figure for demonstrating the vector pipeline operation | movement which performs a load / store instruction. It is a figure explaining bank competition. FIG. 11 is a configuration diagram of a rearrangement control unit 1144. It is a figure for demonstrating a memory access order etc. FIG. It is a flowchart figure which shows the rearrangement procedure of bank access order. It is a figure which shows the example in which a load / store instruction is executed by four slots. It is a figure explaining rearrangement of a register access order. 6 is a diagram for explaining the operation of an access order control unit 602. FIG. It is a figure which shows the example of the value written in the rearrangement management flag. It is a figure explaining issue timing detection. It is a figure which shows a sequence in case an operation instruction depends on two load / store instructions. It is a flowchart figure which shows the operation | movement procedure of rearrangement of register access order.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a diagram for explaining a configuration of a processor in the present embodiment. As an example of the processor in the present embodiment, the configuration of the vector processor 100 is shown. In the vector processor 100, the vector pipeline 104 reads data stored in the data memory 106 and performs various operations in accordance with the instructions stored in the instruction memory 102.

  The vector processor 100 includes a decoder 108, a vector register 110, a scalar register 112, a bank conflict detection unit 113, and a control unit 114 in addition to the instruction memory 102, the vector pipeline 104, and the data memory 106. The vector processor 100 is, for example, a signal processing LSI (Large Scale Integrated circuit). The data memory 106 may be provided outside the vector processor 100.

  The instruction memory 102 stores various instructions for the vector pipeline 104. The various instructions are a load / store instruction for reading data from the data memory 106 to the vector register 110, an arithmetic instruction for performing an arithmetic operation on the data stored in the vector register 110, and the like. The instruction memory 102 is, for example, an SRAM (Static Random Access Memory).

  The decoder 108 reads and decodes the instruction from the instruction memory 102, inputs the decoded instruction to the vector pipeline 104, and reads the address of the data memory 106 accessed by the load / store instruction from the scalar register 112, 104 is input.

  The data memory 106 is a large capacity memory such as a DRAM (Dynamic Random Access Memory). In the data memory 106, consecutive addresses are assigned to storage areas. The storage area is divided into a plurality of banks each having an input / output port. In the data memory 106, the storage area is accessed by bank interleaving.

  The vector pipeline 104 has slots 1040, 1041, 1042, and 1043 for executing load / store instructions and arithmetic instructions by the pipeline, respectively. The slots 1040 to 1043 include sequencers seq0 to seq3 and arithmetic units prc0 to prc3, respectively. In slots 1040 to 1043, the arithmetic units prc0 to prc3 execute instructions under the control of the sequencers seq0 to seq3, respectively. The instruction executed by each slot and its execution timing are determined by the sequencers seq0 to seq3 according to each instruction. Slots 1040 to 1043 are examples of processing units in the present embodiment.

  In the vector processor 100, for example, the instruction is executed by the stage of instruction fetch “IF”, instruction decode “ID”, instruction execution “EX”, memory access “MEM”, and execution result register write “WB”. Is done. The IF and ID stages are executed in the same cycle. In the ID stage, the decoded instruction is input to the sequencers seq0 to seq3 in the slots 1040 to 1043. In each stage of EX to WB, processing corresponding to the instruction is executed by the slots 1040 to 1043 of the vector pipeline 104. In the EX stage, instructions are transferred from the sequencers seq0 to 3 to the arithmetic units prc0 to prc3, and the arithmetic units prc0 to prc3 execute processing corresponding to each instruction.

  For example, in the case of a load / store instruction, the load / store instruction is read from the instruction memory 102 in the IF stage. At the ID stage, the decoder 108 decodes the load / store instruction and inputs it to the slots 1040 to 1043. Each slot accesses the data memory 106 at the EX stage, reads a data element from the data memory 106 at the MEM stage, and writes the read data element to the vector register 110 at the WB stage. In the case of an arithmetic instruction, an arithmetic instruction is read from the instruction memory 102 at the IF stage, and the arithmetic instruction is decoded and input to the vector pipelines 1040 to 1043 at the ID stage. Each slot reads the data element from the vector register 110 at the EX stage and executes an operation, and writes the operation result to the vector register 110 at the WB stage.

  FIG. 2 schematically shows the configuration of the data memory 106. The data memory 106 has a storage area 1060 in which consecutive addresses are assigned in the row direction and the column direction. Each square of the storage area 1060 indicates a data storage area for every 16 bits. Data every 16 bits is a data element. The numbers in the squares indicate the order of the data elements. Storage area 1060 is divided into four banks BK0 to BK3 each having an input / output port. In the following description, four banks are used as an example, but the number of banks may be other than four. Each bank has a bank width of 128 bits corresponding to 8 data elements. For example, in the row R1, the banks BK0 are “0” to “7”, the banks BK1 are “8” to “15”, the banks BK1 are “16” to “23”, and The “24” th to “31” th data elements are stored in the bank BK2. From the banks BK0 to BK3, eight data elements are read out in one access to which a read address is input.

  FIG. 3 is a diagram for explaining the vector register 110. In the vector register 110, data elements read from the data memory 106 for performing arithmetic processing on the slots 1040 to 1043 are temporarily stored. As shown in FIG. 3A, the storage area 1100 of the vector register 110 has a width of 128 bits and stores eight data elements in one row address. Each square in the storage area 1100 indicates a storage area having a 16-bit length, and the number in each square indicates the number of the data element.

  FIG. 3B shows an example of a logical vector register (VR) number and a physical vector register (VR) number in the vector register 110. The logical vector register number indicates the position of data in the vector register 110 in a load / store instruction or an operation instruction. On the other hand, the physical vector register number indicates the position of physical data in the vector register 110. The logical vector register numbers are represented as vr0, vr1, vr2,. The physical vector register numbers corresponding to the respective logical vector register numbers are represented as vr [0], vr [1], vr [2],. The physical vector register number corresponds to, for example, the data element number in FIG. 3A, and is an example of a plurality of registers in the present embodiment.

  FIG. 4 is a diagram for explaining the operation of the vector pipeline 104 for executing the load / store instruction. FIG. 4A shows an address arrangement in the data memory 106. The addresses increase from left to right and from top to bottom. In the bank BK0, the base address of each row is 0x00, 0x40, 0x80, 0xC0,. The offset values from the base address at the head of the banks BK1 to BK3 are 0x10, 0x20, and 0x30, respectively.

  FIG. 4B shows a load / store instruction processing sequence. Here, an example of a load / store instruction executed by two slots is shown with the horizontal axis as the processing cycles C1, C2, C3,. For example, the load / store instruction LS1 is executed by the slot 1040. This instruction is “vldh sr2, vr0”, and is an instruction for instructing the logical vector register number vr0 to read data sequentially from the logical address “sr2” of the data memory 106 (for example, “0x00” of the bank BK0). The load / store instruction LS2 is executed by the slot 1041. This instruction is “vldh sr3, vr1”, and is an instruction that instructs the logical vector register number vr1 to read data from the logical address “sr3” of the data memory 106 (for example, “0x110” of the bank BK1, for example). 4B shows a bank and an address to be accessed in each processing cycle, and each processing cycle corresponds to the “EX” stage in the pipeline shown in FIG. A processing cycle corresponds to one instruction cycle (the same applies hereinafter).

  The load / store instruction LS1 is executed, for example, from the processing cycle C1. First, the slot 1040 is changed to the address “0x00” of the bank BK0 in the cycle C1, the address “0x10” of the bank BK1 in the cycle C2, the address “0x20” of the bank BK2 in the cycle C3, and the bank BK3 in the cycle C4. Access to address “0x30”. Following this, the slot 1040 further changes to the address “0x40” of the bank BK0 in the cycle C5, the address “0x50” of the bank BK1 in the cycle C6, the address “0x60” of the bank BK2 in the cycle C7, and the cycle. The address “0x70” of the bank BK3 is accessed at C8. Note that the address of the data memory 106 accessed by the slot 1040 is indicated by a hatched “/” in FIG.

  On the other hand, the load / store instruction LS2 is executed from the processing cycle C2. The slot 1041 is changed to the address “0x100” of the bank BK0 in the cycle C2, the address “0x110” of the bank BK1 in the cycle C3, the address “0x120” of the bank BK2 in the cycle C4, and the address “0x120” of the bank BK3 in the cycle C5. 0x130 "is accessed. Following this, the slot 1041 further changes to the address “0x140” of the bank BK0 in the cycle C6, the address “0x150” of the bank BK1 in the cycle C7, the address “0x160” of the bank C8 bank BK2, and the cycle C9. To access the address “0x170” of the bank BK3. It should be noted that the address of the data memory 106 accessed by the slot 1041 is indicated by hatching “\” in FIG.

  In FIG. 4B, slots 1040 and 1041 do not access the same bank in the same cycle. Therefore, in this case, bank conflict does not occur. However, if the slots 1040 and 1041 access the same bank in the same cycle, bank contention occurs. In such a case, the control unit 114 rearranges instructions, thereby avoiding bank conflicts without reducing processing efficiency.

  FIG. 5 shows a case where bank contention occurs. FIG. 5A shows the same address of the data memory 106 as in FIG. 5B to 5D show a load / store processing sequence. The addresses of the memory 106 accessed by the load / store instructions LS1 and LS2 in FIGS. 5B to 5D are indicated by hatched lines “/” and “\” in FIG. 5A, respectively.

  5B, in the load / store instruction LS2 executed by the slot 1041, the access start address in the data memory 106 is different from that in FIG. 4B. For example, the slot 1041 starts access to the address “0x110” of the bank BK1 in the cycle C2, and accesses the address “0x120” of the bank BK2 and the address “0x130” of the bank BK3 for each cycle. BK0 address “0x140”, bank BK1 address “0x150”, bank BK2 address “0x160”, BK3 address “0x170”, and bank BK0 address “0x180” are accessed. That is, access is performed in a so-called wrap (folding) pattern. Then, bank conflict occurs in cycles C2 to C8.

  Here, an attempt to avoid bank conflict by stalling is as shown in FIG. As shown in FIG. 5C, bank contention is avoided by stalling the load / store instruction LS2 for one cycle. However, this delays the end of the load / store instruction LS2 until the cycle C10.

  Therefore, in the present embodiment, the control unit 114 causes the slot 1041 as the second processing unit to execute the second load after the slot 1040 as the first processing unit starts executing the first load / store instruction LS1. When the execution of the store instruction LS2 is started, the bank access order to the plurality of banks BK0 to BK3 in the second instruction is set to the bank access order (hereinafter referred to as conflict) that does not conflict with the access to the banks of the slots 1040 and 1041. The second load / store instruction LS2 is executed in the slot 1041.

  Specifically, as shown in FIG. 5D, the access to the address “0x140” of the bank BK0 corresponding to the cycle C5 in FIG. 5A is executed in the cycle C2 (arrow 51). Access to the address “0x110” of BK1, the address “0x120” of bank BK2, and the address “0x130” of bank BK3 corresponding to C2 to C4 are each delayed by one cycle. Similarly, access to the address “0x180” of the bank BK0 corresponding to the cycle C9 in FIG. 5A is executed in the cycle C6 (arrow 52), and the address of BK2 corresponding to the cycles C6 to C8 is executed. Access to the address “0x150”, the address “0x160” of the bank BK2, and the address “0x170” of the bank BK3 are each delayed by one cycle. By doing so, it is equivalent to stalling the first to third cycles by one cycle among the four cycles and executing the fourth cycle first. Thus, bank contention is avoided. The load / store instruction LS2 is executed in the rearranged contention avoidance bank access order. In this way, as shown in, for example, comparison with FIG. 5B, bank contention can be avoided without stalling the load / store instruction LS2, that is, without reducing processing efficiency.

  Returning to FIG. 1, the control unit 114 that performs the above control will be described with reference to FIG. The control unit 114 includes a dependency relationship detection unit 1142, a rearrangement control unit 1144, and a rearrangement address generation unit 1146. Further, as shown in FIG. 6, the rearrangement control unit 1144 includes an access order control unit 602, a register management unit 604, an issue timing detection unit 606, a rearrangement management flag 608, 610, 612, 614, and a register management flag. 616, 618, 620, 622. Of the configurations shown in FIGS. 1 and 6, the operation of the configuration relating to the rearrangement of the bank access order will be described first.

  The controller 114 receives load / store instructions LS1 and LS2 decoded from the decoder 108. In addition, the bank conflict detection unit 113 receives the address of the data memory 106 accessed by the decoded load / store instructions LS 1 and LS 2 from the scalar register 112. The bank conflict detection unit 113 analyzes the bank access order of the load / store instructions LS1, LS2, and detects bank conflict in the load / store instructions LS1, LS2. Bank conflict is detected when each load / store instruction is executed at a predetermined timing and each load / store instruction includes an instruction that accesses the same bank in the same cycle. When the bank conflict detection unit 113 detects a bank conflict, the bank conflict detection unit 113 notifies the rearrangement control unit 1144 of this. In response to this, the rearrangement control unit 1144 rearranges the bank access order of the load / store instruction LS2 to the conflict avoidance bank access order.

  In the rearrangement control unit 1144, the access order control unit 602 determines the bank access order of the load / store instructions LS1 and LS2. The load / store instructions LS1 and LS2 have an access order for each processing cycle (hereinafter referred to as a memory access order) to the address of the data memory 106 as shown in FIG. 7A, for example. Here, the memory access order is indicated by an offset value from the head base address of each bank. For example, the memory access order MA1 is “0x0” in the bank BK0, “0x10” in the bank BK1, “0x20” in the bank BK2, and “0x30” in the bank BK3. The memory access order MA2 is an order of “0x10”, “0x20”, “0x30”, “0x0”. Further, the memory access order MA3 is an order of “0x20”, “0x30”, “0x0”, “0x10”. The memory access order MA4 is an order of “0x30”, “0x0”, “0x10”, “0x20”. The access order control unit 602 determines the bank access order as shown in FIG. 7B from the memory access orders MA1 to MA4. For example, the bank access order BA1 corresponding to the memory access order MA1 is the order of the banks BK0, BK1, BK2, and BK3. The bank access order BA2 corresponding to the memory access order MA2 is the order of the banks BK1, BK2, BK3, and BK0. Furthermore, the bank access order BA3 corresponding to the memory access order MA3 is the order of the banks BK2, BK3, BK0, BK1. The bank access order BA4 corresponding to the memory access order MA4 is the order of the banks BK3, BK0, BK1, and BK2.

  For example, in the example of FIG. 5B, the bank access order of the load / store instruction LS1 is determined to be BA1. The bank access order of the load / store instruction LS2 is determined to be BA2. Therefore, the access order control unit 602 rearranges the bank access order BA2 of the load / store instruction LS2 into a conflict avoidance access order that does not cause bank conflict with the load / store instruction LS1. The contention avoidance access order is an order in which the last accessed bank is rearranged so as to be accessed first. Here, the conflict avoidance access order is the same bank access order BK1 as that of the load / store instruction LS1. Then, the access order control unit 602 transfers the load / store instruction LS1 and the LS2 in which the bank access order is rearranged to the rearrangement address generation unit 1146. The rearrangement address generation unit 1146 generates an address to be accessed of the data memory 106 based on the load / store instructions LS1 and LS2, and inputs the generated addresses to the slots 1140 and 1141, respectively. Then, the slots 1140 and 1141 sequentially access the banks BK0 to BK3 according to the load / store instructions LS1 and LS2, respectively, as shown in FIG.

  The access order control unit 602 writes the bank access order before and after the rearrangement of each load / store instruction in the rearrangement management flags 608 to 614. For example, in the rearrangement management flags 608 to 614, the bank access order of load / store instructions executed in the slots 1040 to 1043 is written. Therefore, the bank access order BA1 of the load / store instruction LS1 is written in the rearrangement management flag 608. The bank access order BA1 before the rearrangement of the load / store instruction LS2 and the bank access order BA2 after the rearrangement are written in the rearrangement management flag 610.

  Further, the execution state of the load / store instruction is input from the decoder 108 to the register management unit 604. The instruction execution state includes information indicating that the corresponding instruction is decoded for each stage such as “EX”, “MEM”, and “WB”. The register manager 604 records and manages the execution state of instructions in the register management flags 616 to 622. This operation will be described in detail later.

  FIG. 8 is a flowchart showing the bank access order rearrangement procedure. The procedure shown in FIG. 8 is executed each time an instruction for one instruction cycle is fetched, for example. First, the decoder 108 decodes a load / store instruction (S802). Then, the bank conflict detection unit 113 determines whether there is a bank conflict (S804).

  If no bank conflict is detected (No in S804), a load / store instruction is executed in the vector pipeline 104 (S812). For example, the load / store instruction LS1 does not cause a bank conflict with the preceding instruction. Therefore, the load / store instruction LS1 is executed by the slot 1040 for the address generated by the rearrangement address generation unit 1146. Then, the rearrangement control unit 1144 manages the registers of the vector register 110 in which data is written (S814). For example, when the WB stage of the load / store instruction LS1 is completed in the slot 1040, information indicating that is written in the register management flags 616 to 622 in 616. Although details will be described later, since the register of the write destination is specified in the load / store instruction LS1, the completion of processing to the register is managed by grasping the completion of the WB stage.

  On the other hand, when bank conflict is detected (Yes in S804), the reordering control unit 1142 determines the conflict avoidance bank access order (S806). For example, in the case of the load / store instruction LS2, a bank conflict is detected with the load / store instruction LS1. Therefore, the access order control unit 602 determines the contention avoidance bank access order BA1 for the load / store instruction LS2. Then, the reorder address generation unit 1146 generates a reorder address corresponding to the conflict avoidance bank access order (S808). Then, the access order control unit 602 manages the bank access order (S810). For example, the bank access order before and after the rearrangement of the load / store instruction LS2 is written in 610 of the rearrangement management flags 610 to 622. Then, the load / store instruction is executed in the vector pipeline 104 (S812). For example, the load / store instruction LS 2 is executed by the slot 1041. Then, the rearrangement control unit 1144 manages the register in which the data is written (S814).

  According to the above procedure, bank contention can be avoided without reducing processing efficiency due to stall.

  FIG. 9 shows an example in which a load / store instruction is executed by four slots. 9A to 9C show a sequence of load / store processing LS1 to LS4 by slots 1040 to 1043.

  FIG. 9A shows a sequence when bank conflict occurs. The sequence of the load / store instructions LS1 and LS2 by the slots 1040 and 1041 is the same as that in FIG. That is, the slot 1040 that processes the load / store instruction LS1 accesses the data memory 106 in the bank access order BA1 (the order of BK0, BK1, BK2, and BK3) to read data. Further, the slot 1041 for processing the load / store instruction LS2 accesses the data memory 106 in the bank access order BA2 (the order of BK1, BK2, BK3, BK0) and reads the data.

  In addition, the slot 1042 executes a load / store instruction LS3. The load / store instruction LS3 is “vldh sr4, vr2”, and is an instruction for sequentially instructing the logical vector register number vr2 to read data from the logical address “sr4” of the data memory 106 (for example, “0x230” of the bank BK3). It is. Accordingly, the slot 1042 accesses the data memory 106 in the bank access order BA4 (order of BK3, BK0, BK1, and BK2). That is, the slot 1042 is changed to the address “0x230” of the bank BK3 in the cycle C3, the address “0x240” of the bank BK0 in the cycle C4, the address “0x250” of the bank BK1 in the cycle C5, and the bank BK2 in the cycle C6. Access to address “0x260”. Further, the slot 1042 is changed to the address “0x270” of the bank BK3 in the cycle C7, the address “0x280” of the bank BK0 in the cycle C8, the address “0x290” of the bank BK1 in the cycle C9, and the bank BK2 in the cycle C10. Access to address “0x2A0”.

  The slot 1043 executes a load / store instruction LS4. The load / store instruction LS4 is “vldh sr5, vr3”, and is an instruction for instructing the logical vector register number vr3 to read data sequentially from the logical address “sr5” of the data memory 106 (for example, “0x320” of the bank BK2). It is. Accordingly, the slot 1043 accesses the data memory 106 in the bank access order BA3 (BK2, BK3, BK0, BK1 order). For example, the address “0x320” of the bank BK2 in cycle C4, the address “0x330” of the bank BK3 in cycle C5, the address “0x340” of the bank BK0 in cycle C6, and the address “0x350” of the bank BK1 in cycle C7 Then, in cycle C8, the address “0x360” of bank BK2 is changed to address “0x370” of bank BK3 in cycle C9, the address “0x380” of bank BK0 is changed in cycle C10, and the address of bank BK1 is changed in cycle C11. Access the address “0x390”.

  In FIG. 9A, bank conflicts occur in slots 1040 and 1041 in cycles C2 to C8. Here, when the load / store instructions LS2 to LS4 are sequentially stalled until bank conflict with the previous load / store instruction is avoided, the result is as shown in FIG.

  As shown in FIG. 9B, the bank conflict is avoided by stalling the load / store instruction LS2 for one cycle, the load / store instruction LS3 for three instruction cycles, and the load / store instruction LS4 for six instruction cycles. Is done. However, by doing so, the end timing of the load / store instructions LS1 to LS4 is delayed until the cycle C17.

  Therefore, in the present embodiment, as shown in FIG. 9C, when the slot 1041 starts executing the load / store instruction LS2 after the slot 1040 starts executing the load / store instruction LS1, the control unit 114 Then, they are rearranged in the conflict avoidance bank access order so that accesses to the banks of the slots 1040 and 1041 do not conflict (arrows 91 and 92), and the load / store instruction LS2 is executed in the slot 1041. The contention avoidance access order is such that the last accessed bank is accessed first. For example, bank BK0 accessed last in bank access order BA2 is bank access order BA1 accessed first. That is, here, the bank access order is the same as that of the load / store instruction LS1. Here, bank contention in slots 1040, 1041, and 1042 is avoided.

  Further, when the slot 1043 starts executing the load / store instruction LS4 after the slot 1042 starts executing the load / store instruction LS3, the control unit 114 changes the bank access order BA3 in the load / store instruction LS4 to the slot 1042. , 1043 are rearranged in the bank access order that does not conflict with the access to the bank of 1043, that is, the conflict avoidance bank access order (arrows 93 and 94), and the load / store instruction LS4 is executed in the slot 1043. The contention avoidance access order is such that the last accessed bank is accessed first. For example, the bank access order BA2 is such that the bank BK1 accessed last in the bank access order BA4 is accessed first. Here, bank contention in the slots 1040 to 1043 is avoided.

  In FIG. 9C, the load / store instructions LS1 to LS4 end in the cycle C11. In comparison with FIG. 9B, the processing speed can be increased by 6 cycles.

  Thus, according to the present embodiment, bank contention can be avoided in a plurality of slots without reducing processing efficiency.

  By the way, in each load / store instruction, a register of the vector register 110 to which data read from the data memory 106 is written is designated. For example, the load / store instruction LS1 in FIGS. 9A to 9C designates the logical vector register number vr0, and the data element read from the data memory 106 is changed to the physical vector register number corresponding to the logical vector register number vr0. This is an instruction for writing to vr [0] to vr [63]. The load / store instruction LS2 designates the logical vector register number vr1, and writes the data element read from the data memory 106 to the physical vector register numbers vr [64] to vr [127] corresponding to the logical vector register number vr1. It is an instruction for. Further, the load / store instruction LS3 designates the logical vector register number vr2, and writes the data element read from the data memory 106 to the physical vector register numbers vr [128] to vr [191] corresponding to the logical vector register number vr2. It is an instruction for. Then, the load / store instruction LS4 designates the logical vector register number vr3 and writes the data element read from the data memory 106 to the physical vector register numbers vr [192] to vr [255] corresponding to the logical vector register number vr3. It is an instruction for. Then, when the bank access order in the load / store instruction is rearranged as described above, the access order of the data write register in the vector register 110 is changed. This affects the start timing of an operation instruction that performs an operation by reading data from the vector register 110.

  Therefore, the control unit 114 according to the present embodiment accesses a plurality of registers of the vector register 110 in a register access order different from the register access order by the slot 1041, and issues an operation instruction for reading the data written by the slot 1041 to the slot 1042. In this case, the register access order by the slot 1042 is rearranged to the register access order in which the read data is written in the slot 1041 in order, and the slot 1042 executes the arithmetic instruction.

  FIG. 10 is a diagram for explaining the rearrangement of the register access order. FIG. 10A shows a sequence when the slots 1040, 1041, and 1042 execute the load / store instructions LS1, LS2, and the arithmetic instruction AL3. Slots 1040 and 1041 execute load / store instructions LS 1 and LS 2 to write data elements to the vector register 110. The slot 1042 executes an arithmetic instruction AL3 that reads data written to the vector register 110 by the slot 1041. The arithmetic instruction AL3 is “vaddh vr1, vr2, vr3”, and is an instruction for adding the data elements written in the logical vector register numbers vr1 and vr2 and instructing the writing of the addition result to vr3.

  In the sequence of the load / store instructions LS1 and LS2, the bank accessed by the slots 1040 and 1041 and the physical vector register number of the vector register 110 to which the read data element is written are shown. Here, a state in which the load / store instruction LS2 is rearranged in the conflict avoidance bank access order in order to avoid bank conflict in the slots 1040 and 1041 is shown.

  For example, in the slot 1040, data read by accessing the bank BK0 in the cycle C1 is stored in the physical vector register number vr [0]-[7] of the vector register 110, and data read by accessing the bank BK1 in the cycle C2 is stored in the vector. The physical vector register number vr [8]-[15] of the register 110, the data read by accessing the bank BK2 in cycle C3 to the physical vector register number vr [16]-[23] of the vector register 110, and In cycle C4, data read out by accessing the bank BK3 is written into the physical vector register numbers vr [24]-[31] of the vector register 110. On the other hand, in the slot 1041, the data read out by accessing the bank BK0 in the cycle C2 is stored in the physical vector register number vr [88]-[95] of the vector register 110, and the data read out by accessing the bank BK1 in the cycle C3 110, the physical vector register number vr [64]-[71] of 110, the data read by accessing the bank BK2 in cycle C4 to the physical vector register number vr [72]-[79] of the vector register 110, and the cycle C5 The data read by accessing the bank BK3 is written in the physical vector register number vr [80]-[87] of the vector register 110.

  In addition, in the sequence of the arithmetic instruction AL3, the physical vector register number of the vector register 110 that the slot 1042 accesses to read data is indicated. In the arithmetic instruction AL3, the vector register 110 is accessed in ascending order of physical vector register numbers. Therefore, the physical vector register numbers vr [64]-[71], vr [72]-[79], vr [80]-[87] of the vector register 110 to which the data is accessed by the load / store instruction LS2 are written. And vr [88]-[95] are accessed in order. This register access order corresponds to the register access order in the load / store instruction LS2 before the bank access order change.

  Incidentally, the access to the data memory 106 by the load / store instruction LS2 is executed in the “EX” stage shown in FIG. Data reading from the data memory 106 is executed at the “MEM” stage, and writing to the vector register 110 is executed at the “WB” stage. Accordingly, in FIG. 10A, the data writing to the vector register 110 by the load / store instruction LS2 ends after two cycles from the cycle in which the access to the data memory 106 is executed. Therefore, this data can be read from the vector register 110 after three cycles. For example, data can be read from the physical vector register numbers vr [64]-[71] from cycle C6, which is three cycles after cycle C3. Therefore, according to the operation instruction AL3, the slot 1042 is changed from the physical vector register number vr [64]-[71] of the vector register 110 in cycle C6 to the physical vector register number vr [72] − of the vector register 110 in cycle C7. From [79], in cycle C8, the data element is obtained from the physical vector register number vr [80]-[87] of the vector register 110, and in cycle C9 from the physical vector register number vr [88]-[95] of the vector register 110. read out. Therefore, the arithmetic instruction AL3 ends at cycle C9.

  Here, paying attention to reading of data elements from the physical vector register numbers vr [88]-[95] of the vector register 110, the physical vector register numbers are obtained by rearranging the bank access order of the load / store instruction LS2. Writing of the data element to vr [88]-[95] ends in cycle C4. Therefore, the data element can be read from the physical vector register number vr [88]-[95] from cycle C5. Therefore, in this embodiment, as shown in FIG. 10B, the control unit 114 accesses the register access order in the operation instruction AL3 in order from the register in which the read data write / store instruction LS2 has been written. In such a register access order, for example, the physical vector register numbers vr [88]-[95] are rearranged in the order in which access is first made (arrow 1000). In this way, the arithmetic instruction AL3 ends at cycle C8. Therefore, the processing time is shortened.

  FIG. 10C shows an example of rearranging the bank access order in the load / store instruction LS2 as an example of avoiding the processing failure by performing the reading before the writing of the data element to the vector register 110 is completed. In this case, the operation instruction AL3 is stalled without managing. Here, the execution of the arithmetic instruction AL3 is started after the writing of data accessed in the last processing cycle C5 of the load / store instruction LS2 is completed, that is, from the cycle C8. Therefore, the end of the operation instruction AL3 is cycle C11. According to this embodiment, in comparison with FIG. 10C, the end of the three-cycle process is accelerated as shown in FIG. 10B.

  Here, the operation of the control unit 114 that rearranges the register access order will be described with reference to FIGS. 1 and 6 again.

  In the control unit 114, the load / store instruction LS 2 and the operation instruction AL 3 are input from the instruction memory 102 to the dependency relationship detection unit 1142. The dependency relationship detection unit 1142 analyzes the load / store instruction LS2 and the operation instruction AL3, and detects the dependency relationship of the operation instruction AL3 with respect to the load / store instruction LS2. The dependency relationship is detected when the logical vector register number for writing data by the load / store instruction LS2 and the logical vector register number for reading data by the operation instruction AL3 overlap.

  The dependency relationship detection unit 1142 transfers the detection result to the rearrangement control unit 1144. When the dependency relationship is detected, the rearrangement control unit 1144 rearranges the register access order in the arithmetic instruction AL3 in addition to the rearrangement of the bank access order of the load / store instruction LS2. Further, the rearrangement control unit 1144 determines the issue timing of the arithmetic instruction AL3 in which the register access order is rearranged.

  In the rearrangement control unit 1144, the load / store instruction LS 2 and the operation instruction AL 3 are input to the access order control unit 602. Then, the access order control unit 602 rearranges the register access order in the arithmetic instruction AL3 based on the bank access order before the rearrangement of the load / store instruction LS2 and the bank access order after the rearrangement. The bank access order before rearrangement of the load / store instruction LS2 and the bank access order after rearrangement are acquired from the rearrangement management flag 610.

  FIG. 11 is a diagram for explaining the operation of the access order control unit 602. The table in FIG. 11A shows the register access order corresponding to the bank access order before rearrangement and the bank access order after rearrangement. For example, the bank access order before the rearrangement of the load / store instruction LS2 is BA2, and the bank access order after the rearrangement is BA1. Therefore, the register access order corresponding to this is RA4.

  FIG. 11B shows the register access order in the vector register 110. FIG. 11B shows the access order of physical vector register numbers when data is written by eight data elements, taking physical vector register numbers vr [0]-[31] in logical vector register number vr0 as an example. It is. For example, the register access order RA1 is the order of vr [0]-[7], vr [8]-[15], vr [16]-[23], vr [24]-[31]. The register access order RA2 is the order of vr [8]-[15], vr [16]-[23], vr [24]-[31], vr [0]-[7]. Furthermore, the register access order RA3 is the order of vr [16]-[23], vr [24]-[31], vr [0]-[7], vr [8]-[15]. The register access order RA4 is an order of vr [24]-[31], vr [0]-[7], vr [8]-[15], vr [16]-[23]. According to FIG. 11B, for example, the register access order RA4 in which the operation instruction AL3 is rearranged is vr [88]-[95], vr [64] in the physical vector register number vr [64]-[95]. The order is-[71], vr [72]-[79], vr [80]-[87].

  The access order control unit 602 stores information in FIGS. 11A and 11B in advance in an internal ROM (Read Only Memory) or the like as map data or the like. Then, the access order control unit 602 determines the register access order in the arithmetic instruction AL3 from the bank access order before and after the rearrangement of the load / store instruction LS2, using the information in FIGS. 11A and 11B. Sort it.

  Then, the access order control unit 602 transfers the rearranged register access order to the rearrangement address generation unit 1146. The rearrangement address generation unit 1146 generates an address of the vector register 110 corresponding to the register access order, and transfers it to the slot 1142 that executes the operation instruction AL3.

  FIG. 12 shows an example of values written in the rearrangement management flags 608 to 614. FIG. 12A is the sequence diagram shown in FIG. In FIG. 12B, corresponding to the sequence diagram of FIG. 12A, the rearrangement management flag 608 for the slot 1040 for executing the load / store instruction LS1 and the slot 1041 for executing the load / store instruction LS2 are shown. The rearrangement management flag 610 and the rearrangement management flag 612 for the slot 1042 for executing the arithmetic instruction AL3 are shown. Since the load / store instruction LS1 has the bank access order BA1, the bank access order “BA1” is written in the rearrangement management flag 608 in the cycles C1 to C4 in which the load / store instruction LS1 is executed. In the load / store instruction LS2, the bank access order is changed from BA2 to BA1. Accordingly, in cycles C2 to C5 in which the load / store instruction LS2 is executed, the bank access order “BA2” before the change and the conflict avoidance bank access order “BA1” after the change are written in the rearrangement management flag 608.

  At the time of cycle C1, the register access order of the arithmetic instruction AL3 is based on the bank access order “BA1” included in the rearrangement management flag 608 and the conflict avoidance bank access order “BA1” included in the rearrangement management flag 610. It is changed from RA1 to RA4. Therefore, the register access order “RA4” is written in the rearrangement management flag 612. Then, in cycles C5 to C8 in which the arithmetic instruction AL3 is executed, the value of the rearrangement management flag 612 is maintained in the register access order “RA4”.

  Returning to FIG. 1 and FIG.

  The rearrangement control unit 1144 determines the issue timing of the arithmetic instruction AL3 in which the register access order is rearranged. The execution state of the load / store instruction is input from the decoder 108 to the register management unit 604. The execution state indicates which of the “EX” stage, the “MEM” stage, and the “WB” stage has been executed. The register manager 604 writes and records the execution state in the register management flags 616 to 622. For example, the execution state of the slot 1041 that executes the load / store instruction LS2 is written in 618 of the register management flags 616 to 622. The processing register management unit 604 notifies the issue timing detection unit 606 of the values of the register management flags 616 to 622. The issue timing detection unit 606 detects the issue timing of the arithmetic instruction AL3 based on the values of the register management flags 616 to 622.

  FIG. 13 is a diagram illustrating issue timing detection. FIG. 13A is the same sequence diagram as FIG. Here, the bank access order of the load / store instruction LS2 is rearranged according to the bank access order of the load / store instruction LS1, and further, the register access order of the arithmetic instruction AL3 according to the register access order of the load / store instruction LS2 The state where is rearranged is shown.

  FIG. 13B shows an example of the register management flag when the above rearrangement is performed. Here, a register management flag 618 for the slot 1041 for executing the load / store instruction LS2 is shown. The register management flag 618 further includes register management flags 618-1, 618-2, 618-3, and 618-4 in the order of physical vector register numbers of the vector register 110. The register management flag 618-1 is a process for the physical vector register number vr [64]-[71], and the register management flag 618-2 is a process for the physical vector register number vr [72]-[79]. -3 corresponds to the processing for the physical vector register number vr [80]-[87], and the register management flag 618-4 corresponds to the processing for the physical vector register number vr [88]-[95]. The register management flags 618-1 to 618-4 have an initial value “OFF”. Then, “ON” is written in the register management flags 618-1 to 618-4 when the writing of the data element to the corresponding physical vector register number vr is completed.

  As shown in FIG. 13A, in the load / store instruction LS2, bank access for data reading to the physical vector register numbers vr [88]-[95] is executed in cycle C2. Then, the “WB” stage is executed at cycle C 4 after two cycles, and data is written into the vector register 110. Therefore, the register management flag 618-4 is set to “ON” in the cycle C4. Similarly, a bank access for reading data to physical vector register numbers vr [64]-[71] is executed in cycle C3, and data is written to vector register 110 in cycle C5 after two cycles. Therefore, the register management flag 618-1 is turned “ON” in the cycle C5. In cycle C4, bank access for reading data to physical vector register numbers vr [72]-[79] is executed, and data is written into the vector register 110 in cycle C6 after two cycles. Therefore, the register management flag 618-2 is turned “ON” in cycle C6. Then, in cycle C5, bank access for reading data to physical vector register numbers vr [80]-[87] is executed, and data is written into the vector register 110 in cycle C7 after two cycles. Therefore, the register management flag 618-3 is turned “ON” in cycle C7.

  The register management unit 604 transfers the values of the register management flags 616 to 622 to the issue timing detection unit 606. The issue timing detection unit 606 detects the issue timing based on the execution states of the load / store instructions LS1 and LS2 indicated by the values of the register management flags 616 to 622. For example, as shown in FIG. 13B, when the register management flag 618-4 is turned “ON” in the cycle C4, the arithmetic instruction AL3 can be executed from the next cycle. Therefore, the issue timing detection unit 606 detects the issue timing at cycle C4. The issue timing detection unit 606 transmits a control signal instructing the decoder 108 to issue the operation instruction AL3. In response to this, the decoder 108 issues an arithmetic instruction AL3 to the slot 1042 so as to be executed from the cycle C5.

  Next, an example in which an operation instruction depends on a plurality of load / store instructions is shown.

  FIG. 14 shows a sequence when an operation instruction depends on two load / store instructions. In FIG. 14A, the load / store instructions LS1, LS2, and LS3 are executed by the slots 1040, 1041, and 1042, and the operation instruction AL4 is executed on the data written to the vector register 110 by the slots 1041 and 1042. A sequence when the slot 1043 to read is read is shown. Here, a state in which the load / store instructions LS2 and LS3 are stalled in order to avoid bank conflict in the slots 1040 to 1042 for executing the load / store instructions LS1 to LS3 is shown.

  In the load / store instruction LS1, the data memory 106 is accessed in the bank access order BA1, and data is written in the vector register 110 in the register access order RA1. In the load / store instruction LS2, the data memory 106 is accessed in the bank access order BA2, and data is written in the vector register 110 in the register access order RA1. In the load / store instruction LS3, the data memory 106 is accessed in the bank access order BA3, and data is written in the vector register 110 in the register access order RA1. Here, the load / store instruction LS2 is stalled for one cycle. The load / store instruction LS3 is stalled for two cycles.

  The arithmetic instruction AL4 is “vaddh vr0, vr1, vr2,” and is an instruction for adding the data elements written in the logical vector register numbers vr0 and vr1 and instructing writing of the addition result to vr2. In accordance with this, the slot 1043 accesses the vector register 110 in the register access order RA1, reads data, and performs an operation. For example, in the first cycle, the physical vector register numbers vr [0] and [63] are accessed. Access to data written to the physical vector register number vr [0] is performed in cycle C5 in the load / store instruction LS3. Therefore, the writing is completed at C7 after two cycles. On the other hand, access to the data written to the physical vector register number vr [64] is performed in the cycle C3 in the load / store instruction LS2. Therefore, the writing is completed at C5 after two cycles. Therefore, in this case, the arithmetic instruction AL4 starts from C8 next to the later cycle C7.

  Next, a sequence according to the present embodiment is shown in FIG. FIG. 14B shows a state in which the load / store instructions LS2 and LS3 are rearranged in the conflict avoidance bank access order. The conflict avoidance bank access order in the load / store instruction LS2 is such that the bank BK0 accessed last is accessed first in the initial bank access order BA2. Therefore, the bank access order BA1 is obtained. In the conflict avoidance bank access order in the load / store instruction LS3, the bank BK1 that is accessed last is first accessed in the initial bank access order BA3. Then, a bank conflict occurs with the rearranged load / store instruction LS2. Therefore, the same rearrangement is repeated. Finally, the contention avoidance bank access order BA1 is obtained. In this way, the contention avoidance bank access order is obtained by repeating the process of making the bank accessed last be accessed first.

  Next, rearrangement of the register access order will be described. The arithmetic instruction AL4 depends on two load / store instructions. When an operation instruction depends on a plurality of load / store instructions, the operation of the rearrangement control unit 1144 is different from the contents described in FIGS. In this case, the execution state of the dependent load / store instruction is managed by the register management flags 616 to 622. A specific example is shown in FIG.

  In FIG. 14C, register management flags 618-0 to 618-3 for the slot 1041 for executing the load / store instruction LS2 and register management flags 620-0 to for the slot 1042 for executing the load / store instruction LS3. 620-3. Here, the register management flag 618-0 is used for processing for the physical vector register number vr [64]-[71], and the register management flag 618-1 is used for processing for the physical vector register number vr [72]-[79]. The management flag 618-2 corresponds to the processing for the physical vector register number vr [80]-[87], and the register management flag 618-3 corresponds to the processing for the physical vector register number vr [88]-[95]. . The register management flag 620-0 is used for processing for the physical vector register number vr [0]-[7], and the register management flag 620-1 is used for processing for the physical vector register number vr [8]-[15]. The flag 620-2 corresponds to the process for the physical vector register number vr [16]-[23], and the register management flag 620-3 corresponds to the process for the physical vector register number vr [24]-[31]. In the register management flags 618-0 to 618-3 and 620-0 to 620-3, “ON” is written by the register management unit 604 in a cycle in which writing of data elements to the corresponding physical vector register numbers is completed. For example, register management flag 618-3 is "ON" in cycle C4, register management flag 618-0 is in cycle C5, register management flag 618 is in cycle C6, and register management flag 618-2 is in cycle C7. become. The register management flag 620-2 is in cycle C5, the register management flag 620-3 is in cycle C6, the register management flag 620-0 is in cycle C7, and the register management flag 620-1 is in cycle C8. "ON".

  On the other hand, in each cycle of the arithmetic instruction AL4, physical vector register numbers vr [0] and vr [64], vr [8] and vr [72], vr [16] and vr [80], and so on. , The physical vector register numbers separated by “64” intervals are accessed. These physical vector register number pairs include register management flag pairs 618-0 and 620-0, pairs 618-1 and 620-1, pairs 618-2 and 620-2, and pairs 618-3 and 620, respectively. -3. Therefore, the register management unit 604 includes register management flag pairs 618-0 and 620-0, pairs 618-1 and 620-1, pairs 618-2 and 620-2, and pairs 618-3 and 620-3. In either of them, when both are turned "ON", the register access order in the operation instruction AL4 is determined. For example, pair 618-3, 620-3 in cycle C6, pair 618-0, 620-0 and pair 618-2, 620-2 in cycle C7, and pair 618-1, 620-1 in cycle C8. Are both “ON”. Therefore, in the earliest cycle C6, the register management unit 604 rearranges the register access order so as to start access to the physical vector register numbers corresponding to the pairs 618-3 and 620-3. Then, the rearranged operation instruction AL4 is started from the next cycle C7. The state at this time is shown in FIG.

  The register management unit 604 outputs a signal that instructs the rearrangement address generation unit 1146 to generate an address of the vector register 110 corresponding to the rearranged register access order. Then, the rearrangement address generation unit 1146 generates an address to be accessed and sends it to the slot 1043 that executes the operation instruction AL4. In addition, the register management unit 604 transmits a signal instructing the issue of the arithmetic instruction AL4 to the issue timing detection unit 606. Then, the issue timing detection unit 606 transfers this to the decoder 108. Then, the decoder 108 decodes the operation instruction AL4 and sends it to the slot 1043. Accordingly, the slot 1043 executes the arithmetic instruction AL4 at the timing shown in FIG.

  FIG. 15 is a flowchart showing an operation procedure for rearranging the register access order.

  The procedure shown in FIG. 15 is executed each time an instruction for one instruction cycle is fetched, for example. First, the decoder 108 decodes the operation instruction (S1500). Then, the dependency relationship detection unit 1142 detects the dependency relationship with the preceding load / store instruction (S1502).

  When the dependency relationship is not detected (No in S1504), the operation instruction is executed in the vector pipeline 104 (S1520). On the other hand, if a dependency relationship is detected (Yes in S1504) and there is one dependent preceding instruction (Yes in S1506), the access order control unit 602 determines the bank access order of the preceding load / store instruction. Reference is made (S1508), and the register access order of operation instructions is controlled (S1510). For example, the access order control unit 602 rearranges the register access order, and the register management unit 604 writes the execution state in the processing register management flags 616 to 622. Then, an arithmetic instruction is executed (S1520).

  If the dependency relationship is detected (Yes in S1504) and there are two dependent preceding instructions (No in S1506, Yes in S1512), the register management unit 604 uses the processing register management flags 616 to 622. The process completion register is monitored (S1514), and the register access order is determined (S1516). Then, the register management unit 604 manages the register access completion status by writing it in the processing register management flags 616 to 622 (S1518). Then, an arithmetic instruction is executed (S1520).

  In this way, even when the operation instruction depends on one or two load / store instructions, the processing efficiency can be avoided and the processing efficiency can be avoided.

  The above embodiment is summarized as follows.

(Appendix 1)
A first processing unit that accesses a plurality of banks of the memory in a first bank access order;
A second processing unit that starts accessing the plurality of banks in a second bank access order following the start of access of the first processing unit;
When access to the plurality of banks by the first processing unit and the second processing unit competes, the second bank access order is rearranged to a third bank access order that does not cause the conflict. And a control unit that causes the second processing unit to access the plurality of banks.

(Appendix 2)
In Appendix 1,
The control unit determines a start timing of access to the plurality of banks of the second processing unit according to the third bank access order from a start timing of access to the plurality of banks of the first processing unit. A processor which is controlled after one cycle.

(Appendix 3)
In Appendix 1 or 2,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the first register access order,
A third processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The control unit controls the second register access order so that the second register access order is accessed sequentially from a register for which writing in the first register access order has been completed.

(Appendix 4)
In Appendix 3,
The processor is characterized in that the second register access order is rearranged based on the second bank access order and the third bank access order.

(Appendix 5)
In Appendix 1 or 2,
The first processing unit accesses and writes data read by accessing the memory in the first bank access order to a plurality of registers in the first register access order,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the second register access order,
A third processing unit for accessing the plurality of registers in a third register access order and reading data written by the first and second processing units;
The processor is configured to control the third register access order so that the third register access order is accessed sequentially from a register in which writing by the first and second processing units is completed.

(Appendix 6)
In Appendix 5,
The control unit is a processor that records accesses to the plurality of registers of the first and second processing units and determines the third register access order based on the records.

(Appendix 7)
In any one of supplementary notes 1 to 6,
In the third bank access order, the processor that is accessed last in the second bank access order is accessed earlier than the other banks.

(Appendix 8)
A first processing unit that accesses a plurality of registers in a first register access order and writes data;
A second processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The second register access order is rearranged to a third register access order in which the data to be read is sequentially accessed from the register in which the writing of the read data by the first processing unit is completed, among the plurality of registers. And a control unit that causes the processing unit to access the plurality of registers.

(Appendix 9)
A first processing unit that accesses a plurality of registers in a first register access order and writes data;
A second processing unit for writing data by accessing the plurality of registers in a second register access order;
A third processing unit that accesses the plurality of registers in a third register access order and reads data written by the first and second processing units;
And a control unit that controls the third register access order so as to sequentially access the data to be read from the register in which the writing by the first and second processing units of the plurality of registers is completed.

(Appendix 10)
In Appendix 9,
The control unit is a processor that records accesses to the plurality of registers of the first and second processing units and determines the third register access order based on the records.

(Appendix 11)
A first processing unit that accesses a plurality of banks of the memory in a first bank access order, and an access to the plurality of banks in a second bank access order is started following the start of access of the first processing unit. And a second processing unit for controlling a processor,
When access to the plurality of banks by the first processing unit and the second processing unit competes, the second bank access order is rearranged to a third bank access order that does not cause the conflict. Allowing the second processing unit to access the plurality of banks;
Processor control method (Appendix 12)
In Appendix 11,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the first register access order,
The processor further includes a third processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The second register access order is controlled so as to be accessed sequentially from the register in which writing according to the first register access order is completed.
How to control the processor.

(Appendix 13)
In Appendix 11,
The first processing unit accesses and writes the data read by accessing the memory in the first bank access order to a plurality of registers in the first register access order,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the second register access order;
The processor further includes a third processing unit that accesses the plurality of registers in a third register access order and reads data written by the first and second processing units;
The third register access order is controlled so as to be accessed in order from the register in which writing by the first and second processing units is completed.
How to control the processor.

(Appendix 14)
A first processing unit that accesses a plurality of registers in a first register access order and writes data; and a second processing unit that accesses the plurality of registers in a second register access order and reads the written data. A control method of a processor having a processing unit,
The second register access order is rearranged in a third register access order in which the data to be read is sequentially accessed from the register in which writing by the first processing unit is completed, among the plurality of registers, Causing the second processing unit to access the plurality of registers;
How to control the processor.

(Appendix 15)
A first processing unit that accesses a plurality of registers in a first register access order and writes data; a second processing unit that accesses the plurality of registers in a second register access order and writes data; And a third processing unit that accesses a plurality of registers in a third register access order and reads data written by the first and second processing units.
The third register access order is rearranged into a fourth register access order in which the data to be read is sequentially accessed from the register in which the writing of the read data by the first and second processing units is completed among the plurality of registers. And causing the third processing unit to access the plurality of registers,
How to control the processor.

100: Vector processor, 106: Data memory, BK0 to BK3: Bank,
110: Vector register 114: Control unit 1040-1043: Slot
1142: Dependency detection unit, 1144: Rearrangement control unit

Claims (10)

A first processing unit that accesses a plurality of banks of the memory in a first bank access order;
A second processing unit that starts accessing the plurality of banks in a second bank access order following the start of access of the first processing unit;
When access to the plurality of banks by the first processing unit and the second processing unit competes, the second bank access order is rearranged to a third bank access order that does not cause the conflict. And a control unit that causes the second processing unit to access the plurality of banks. In claim 1,
The control unit determines a start timing of access to the plurality of banks of the second processing unit according to the third bank access order from a start timing of access to the plurality of banks of the first processing unit. A processor which is controlled after one cycle. In claim 1 or 2,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the first register access order,
A third processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The control unit controls the second register access order so that the second register access order is accessed sequentially from a register for which writing in the first register access order has been completed. In claim 3,
The processor is characterized in that the second register access order is rearranged based on the second bank access order and the third bank access order. In claim 1 or 2,
The first processing unit accesses and writes data read by accessing the memory in the first bank access order to a plurality of registers in the first register access order,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the second register access order,
A third processing unit for accessing the plurality of registers in a third register access order and reading data written by the first and second processing units;
The processor is configured to control the third register access order so that the third register access order is accessed sequentially from a register in which writing by the first and second processing units is completed. A first processing unit that accesses a plurality of registers in a first register access order and writes data;
A second processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The second register access order is rearranged to a third register access order in which the data to be read is sequentially accessed from the register in which the writing of the read data by the first processing unit is completed, among the plurality of registers. And a control unit that causes the processing unit to access the plurality of registers. A first processing unit that accesses a plurality of registers in a first register access order and writes data;
A second processing unit for writing data by accessing the plurality of registers in a second register access order;
A third processing unit that accesses the plurality of registers in a third register access order and reads data written by the first and second processing units;
And a control unit that controls the third register access order so as to sequentially access the data to be read from the register in which the writing by the first and second processing units of the plurality of registers is completed. A first processing unit that accesses a plurality of banks of the memory in a first bank access order, and an access to the plurality of banks in a second bank access order is started following the start of access of the first processing unit. And a second processing unit for controlling a processor,
When access to the plurality of banks by the first processing unit and the second processing unit competes, the second bank access order is rearranged to a third bank access order that does not cause the conflict. Allowing the second processing unit to access the plurality of banks;
How to control the processor. In claim 8,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the first register access order,
The processor further includes a third processing unit that accesses the plurality of registers in a second register access order and reads the written data;
The second register access order is controlled so as to be accessed sequentially from the register in which writing according to the first register access order is completed.
How to control the processor. In claim 8,
The first processing unit accesses and writes the data read by accessing the memory in the first bank access order to a plurality of registers in the first register access order,
The second processing unit accesses and writes the data read by accessing the memory in the third bank access order to the plurality of registers in the second register access order;
The processor further includes a third processing unit that accesses the plurality of registers in a third register access order and reads data written by the first and second processing units;
The third register access order is controlled so as to be accessed in order from the register in which writing by the first and second processing units is completed.
How to control the processor.

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