JP5701736B2 - 平坦化方法および平坦化装置 - Google Patents
平坦化方法および平坦化装置 Download PDFInfo
- Publication number
- JP5701736B2 JP5701736B2 JP2011278837A JP2011278837A JP5701736B2 JP 5701736 B2 JP5701736 B2 JP 5701736B2 JP 2011278837 A JP2011278837 A JP 2011278837A JP 2011278837 A JP2011278837 A JP 2011278837A JP 5701736 B2 JP5701736 B2 JP 5701736B2
- Authority
- JP
- Japan
- Prior art keywords
- solid plate
- workpiece
- fluorine
- oxide film
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
Description
図1乃至図5を用いて、本実施形態に係る平坦化方法について説明する。本実施形態は、酸性溶液である処理液15中において酸化珪素膜21を含む被加工物12の被加工面をフッ素(F)23が吸着した固体板11の表面に接触させることで、接触した酸化珪素膜の被加工面を化学的に溶解させ、被加工面の平坦化を行う例である。本実施形態では、機械的研磨を必要としないため、被加工面への研磨ダメージを抑制することができる。以下に、本実施形態について詳説する。
まず、図1を用いて、本実施形態に係る酸化珪素膜の平坦化を行う平坦化装置について説明する。図1は、本実施形態に係る酸化珪素膜の平坦化を行う平坦化装置の構成例を示す斜視図である。
次に、図2乃至図5を用いて、本実施形態に係る酸化珪素膜の平坦化方法および原理について説明する。図2乃至図5は、本実施形態に係る酸化珪素膜の平坦化工程および原理を示す断面図である。
すなわち、解離したフッ素イオンと珪素とが結合し、ヘキサフルオロ珪酸イオン(SiF6 2−)30として酸性溶液の処理液15中に溶解する。
上記実施形態によれば、酸性溶液の処理液15中において、被加工物12(酸化珪素膜21)の被加工面をフッ素23が吸着した固体板11の表面に接触させる。これにより、固体板11に接触した酸化珪素膜21の被加工面を化学的に溶解させ、被加工面の平坦化を行う。すなわち、酸化珪素膜21を機械的な研磨なく、化学的な反応のみで平坦化することができる。このため、機械的研磨によって生じる酸化珪素膜21の被加工面への研磨ダメージを抑制することができる。
図6乃至図9を用いて、本実施形態に係る平坦化方法の適用例について説明する。本実施形態に係る平坦化方法は、半導体装置のSTI(Shallow Trench Isolation)形成プロセスに適用され得る。
Claims (10)
- 処理液中において、酸化珪素膜を含む被加工物の被加工面と、イオン交換体を含み、かつフッ素が吸着した固体板の表面とを接触または極接近させることにより、前記被加工物の被加工面を平坦化する平坦化方法であって、
フッ素と前記固体板との結合エネルギーは、フッ素と珪素との結合エネルギーよりも小さいことを特徴とする平坦化方法。 - 前記イオン交換体は、鉄酸化物またはセリウムを含むことを特徴とする請求項1に記載の平坦化方法。
- 前記処理液が酸性溶液であることを特徴とする請求項1または請求項2に記載の平坦化方法。
- 接触または極接近した前記被加工物の被加工面と前記固体板の表面の温度を上昇させることを特徴とする請求項1乃至請求項3のいずれか1項に記載の平坦化方法。
- 前記被加工物の被加工面の平坦化前に、フッ酸溶液に浸されることにより前記固体板の表面にフッ素が吸着されることを特徴とする請求項1乃至請求項4のいずれか1項に記載の平坦化方法。
- イオン交換体を含み、かつ表面にフッ素が吸着した固体板と、
酸化珪素膜を含む被加工物を保持し、前記被加工物の被加工面と、前記固体板の表面とを処理液中で接触または極接近させることにより、前記被加工物の被加工面を平坦化する保持部と、
を具備し、
フッ素と前記固体板との結合エネルギーは、フッ素と珪素との結合エネルギーよりも小さいことを特徴とする平坦化装置。 - 前記イオン交換体は、鉄酸化物またはセリウムを含むことを特徴とする請求項6に記載の平坦化装置。
- 前記処理液が酸性溶液であることを特徴とする請求項6または請求項7に記載の平坦化装置。
- 接触または極接近した前記被加工物の被加工面と前記固体板の表面の温度を上昇させることを特徴とする請求項6乃至請求項8のいずれか1項に記載の平坦化装置。
- 前記被加工物の被加工面の平坦化前に、フッ酸溶液に浸されることにより前記固体板の表面にフッ素が吸着されることを特徴とする請求項6乃至請求項9のいずれか1項に記載の平坦化装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011278837A JP5701736B2 (ja) | 2011-12-20 | 2011-12-20 | 平坦化方法および平坦化装置 |
US13/603,924 US8936729B2 (en) | 2011-12-20 | 2012-09-05 | Planarizing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011278837A JP5701736B2 (ja) | 2011-12-20 | 2011-12-20 | 平坦化方法および平坦化装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013131566A JP2013131566A (ja) | 2013-07-04 |
JP5701736B2 true JP5701736B2 (ja) | 2015-04-15 |
Family
ID=48610535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011278837A Expired - Fee Related JP5701736B2 (ja) | 2011-12-20 | 2011-12-20 | 平坦化方法および平坦化装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8936729B2 (ja) |
JP (1) | JP5701736B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10879087B2 (en) | 2017-03-17 | 2020-12-29 | Toshiba Memory Corporation | Substrate treatment apparatus and manufacturing method of semiconductor device |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6004887A (en) * | 1994-09-01 | 1999-12-21 | Kabushiki Kaisha Toshiba | Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film |
JP3305911B2 (ja) * | 1995-03-15 | 2002-07-24 | 株式会社東芝 | 研磨方法および研磨装置並びにそれに用いる研磨砥石 |
US6103627A (en) * | 1996-02-21 | 2000-08-15 | Micron Technology, Inc. | Treatment of a surface having an exposed silicon/silica interface |
TW405155B (en) * | 1997-07-15 | 2000-09-11 | Toshiba Corp | Semiconductor device and its manufacture |
US6200896B1 (en) * | 1998-01-22 | 2001-03-13 | Cypress Semiconductor Corporation | Employing an acidic liquid and an abrasive surface to polish a semiconductor topography |
WO2001078116A2 (en) | 2000-04-11 | 2001-10-18 | Cabot Microelectronics Corporation | System for the preferential removal of silicon oxide |
JP2003209076A (ja) * | 2002-01-15 | 2003-07-25 | Hitachi Chem Co Ltd | Cmp研磨剤および基板の研磨方法 |
JPWO2004023539A1 (ja) * | 2002-09-06 | 2006-01-05 | 旭硝子株式会社 | 半導体集積回路用絶縁膜研磨剤組成物および半導体集積回路の製造方法 |
JP4248889B2 (ja) | 2002-11-22 | 2009-04-02 | Agcセイミケミカル株式会社 | 研磨材粒子の品質評価方法、研磨方法及びガラス研磨用研磨材 |
JP2004072099A (ja) | 2003-08-01 | 2004-03-04 | Hitachi Ltd | 研磨方法 |
US7566391B2 (en) * | 2004-09-01 | 2009-07-28 | Micron Technology, Inc. | Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media |
JP4041110B2 (ja) * | 2004-09-29 | 2008-01-30 | Hoya株式会社 | 磁気ディスク用ガラス基板の製造方法及び磁気ディスクの製造方法 |
TW200629392A (en) * | 2004-12-22 | 2006-08-16 | Ebara Corp | Flattening method and flattening apparatus |
JP2008081389A (ja) | 2006-08-28 | 2008-04-10 | Osaka Univ | 触媒支援型化学加工方法及び装置 |
JP5007384B2 (ja) | 2006-10-18 | 2012-08-22 | 株式会社荏原製作所 | 触媒支援型化学加工方法及び装置 |
KR100809338B1 (ko) * | 2006-09-21 | 2008-03-05 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
JP2008262956A (ja) * | 2007-04-10 | 2008-10-30 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP4887266B2 (ja) * | 2007-10-15 | 2012-02-29 | 株式会社荏原製作所 | 平坦化方法 |
JP2010206094A (ja) * | 2009-03-05 | 2010-09-16 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8552425B2 (en) * | 2010-06-18 | 2013-10-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP5404673B2 (ja) * | 2011-02-25 | 2014-02-05 | 株式会社東芝 | Cmp装置、研磨パッド及びcmp方法 |
JP2012212752A (ja) * | 2011-03-31 | 2012-11-01 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8703004B2 (en) * | 2011-11-14 | 2014-04-22 | Kabushiki Kaisha Toshiba | Method for chemical planarization and chemical planarization apparatus |
-
2011
- 2011-12-20 JP JP2011278837A patent/JP5701736B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-05 US US13/603,924 patent/US8936729B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20130157464A1 (en) | 2013-06-20 |
US8936729B2 (en) | 2015-01-20 |
JP2013131566A (ja) | 2013-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102775584B1 (ko) | 콜로이드성 실리카 화학적-기계적 연마 조성물 | |
US9556363B2 (en) | Copper barrier chemical-mechanical polishing composition | |
JP5963822B2 (ja) | 研磨粒子、研磨スラリー及びこれを用いた半導体素子の製造方法 | |
JP5820404B2 (ja) | 平坦化方法及び平坦化装置 | |
JP6189571B1 (ja) | 研磨用組成物およびこれを用いた研磨方法、ならびにこれらを用いた研磨済研磨対象物の製造方法 | |
US20160035598A1 (en) | Method for chemical planarization and chemical planarization apparatus | |
CN105585965A (zh) | 研磨组成物 | |
CN101308790A (zh) | 移除基底上的绝缘层的方法和化学机械研磨工艺 | |
JP5701736B2 (ja) | 平坦化方法および平坦化装置 | |
TWI843059B (zh) | 電晶體及其製造方法 | |
JP5882579B2 (ja) | 半導体装置の製造方法 | |
JP5750877B2 (ja) | ウェーハの片面研磨方法、ウェーハの製造方法およびウェーハの片面研磨装置 | |
CN104078346A (zh) | 半导体器件的平坦化方法 | |
US20080261402A1 (en) | Method of removing insulating layer on substrate | |
TW200410789A (en) | Method for manufacturing metal line contact plug of semiconductor device | |
CN111599677B (zh) | 半导体结构及其形成方法 | |
CN114725063A (zh) | 半导体结构及其制造方法 | |
JP2011071303A (ja) | 半導体装置の製造方法 | |
JP5835890B2 (ja) | 素子間分離層の形成方法 | |
JP2010278120A5 (ja) | ||
US20140030891A1 (en) | Method of manufacturing semiconductor device and apparatus for manufacturing semiconductor device | |
TWI680508B (zh) | 於化學機械硏磨處理期間藉由原地蝕刻移除缺陷 | |
US9558961B2 (en) | Manufacturing method of semiconductor device | |
US20110237079A1 (en) | Method for exposing through-base wafer vias for fabrication of stacked devices | |
JP2007311473A (ja) | 半導体絶縁膜用研磨剤及び基板の研磨方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131205 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131212 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131219 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131226 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20140109 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140207 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141016 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141021 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141219 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150120 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150218 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5701736 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |