JP5694212B2 - Management information generation method and memory system - Google Patents

Description

  Embodiments described herein relate generally to a management information generation method and a memory system.

  In recent years, the capacity of a NAND flash memory, which is a nonvolatile semiconductor memory device, has increased, and an SSD (Solid State Drive) equipped with this NAND flash memory has attracted attention.

  Conventionally, an SSD stores a management table in a volatile memory as it is in a NAND flash memory that is a nonvolatile memory. However, when the size of the management table is large, a volatile memory having a large memory size is required. Further, when the size of the management table is large, it takes a long time to read from the NAND flash memory to the volatile memory. For this reason, it is desired to reduce the size of the management table.

JP 2009-211122 A

  The problem to be solved by the present invention is to provide a management information generation method and a memory system capable of managing data in a nonvolatile memory with a management table having a small size.

  According to the embodiment, a first predetermined number of physical block addresses in a non-volatile memory arranged in a semiconductor memory device used as an external storage device of a computer system are extracted in order from a small address value. Create a physical block address group. Furthermore, when the physical block address of the bad block is included in the physical block address group, the physical block address of the first good block after the bad block is changed to the first physical block address of the next physical block address group. The next physical block address group is generated by setting the block address. Then, for each of the physical block address groups, all the physical block addresses after the first bad block are set to the first bad block. Further, a second predetermined number of physical block address groups are extracted from the entire physical block address group in order of increasing number of good blocks to generate a physical block address group group. For each of the generated physical block address groups, the number of consecutive bad blocks in each physical block address group and the number of consecutive good blocks from the top are the least in the physical block address group. A second bad block is set in each physical block address group so as to have the same value as the physical block address group. A logical block address group that is a plurality of continuous logical block addresses set by using a logical block address in the nonvolatile memory corresponding to a logical address specified by a host device, and the physical block address group group. An associated address management table is generated.

FIG. 1 is a block diagram illustrating a configuration example of an SSD according to the first embodiment. FIG. 2 is a diagram for explaining address conversion performed in the SSD. FIG. 3 is a diagram illustrating a configuration example of the BA conversion table and the validity management table according to the first embodiment. FIG. 4 is a flowchart showing a procedure for reading data from the NAND memory. FIG. 5 is a flowchart showing a procedure for constructing a BA conversion table according to the second embodiment. FIG. 6 is a diagram for explaining the pre-construction process of the BA conversion table according to the second embodiment. FIG. 7 is a diagram for explaining the post-construction process of the BA conversion table according to the second embodiment. FIG. 8 is a diagram illustrating a configuration example of the BA conversion table and the validity management table according to the second embodiment. FIG. 9 is a perspective view showing an example of a personal computer equipped with an SSD. FIG. 10 is a diagram illustrating a system configuration example of a personal computer equipped with an SSD.

  Hereinafter, a management information generation method and a memory system according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)

  FIG. 1 is a block diagram illustrating a configuration example of an SSD according to the first embodiment. An SSD (Solid State Drive) 1 as a semiconductor storage device (memory system) is an external storage device used in a computer system, and includes a RAM 2, a NAND memory 4 (nonvolatile memory) that actually stores data, and a controller 3. And.

  The RAM 2 is connected to the host device 10, the controller 3, and the NAND memory 4. The NAND memory 4 is connected to the controller 3 and the RAM 2. The controller 3 is connected to the host device 10, the RAM 2, and the NAND memory 4.

  The RAM 2 is a memory such as SRAM, DRAM, or FERAM. The RAM 2 temporarily stores data sent from the host device 10 and sends the stored data to the NAND memory 4. Further, when the data requested to be read from the host device 10 is read from the NAND memory 4, the RAM 2 temporarily stores the read data. Data read from the NAND memory 4 and temporarily stored in the RAM 2 is sent to the host device 10.

  The RAM 2 stores a host address conversion table 21, a read / write buffer 22, a BA (Block Address) conversion table 23A as a management table, an effectiveness management table 24A, and the like. The host address conversion table 21 is a conversion table that indicates the correspondence between the logical address given from the host device 10 and the logical block address of the NAND memory 4. The logical block of the NAND memory 4 is an erasing unit set in the SSD 1 and is associated with one or more physical blocks.

  The BA conversion table 23A is a conversion table (address management table) indicating a correspondence relationship between the logical block address of the NAND memory 4 and the physical block address (storage position) of the NAND memory 4, and addresses management (read / write) Control). The physical block is a minimum unit that can be independently erased in the NAND memory 4 and is composed of a plurality of physical pages. Hereinafter, the logical block address is referred to as a logical BA, and the physical block address is referred to as a physical BA.

  In the BA conversion table 23A of this embodiment, logical BAs having consecutive address numbers are grouped. In addition, physical BAs having consecutive address numbers are grouped. Then, the grouped logical BA and the grouped physical BA are associated with each other. The validity management table 24A is a table indicating the validity of the logical BA, the number of erasures, etc. for each logical BA.

  The host address conversion table 21, BA conversion table 23A, and validity management table 24A are expanded from the NAND memory 4 to the RAM 2 at a predetermined timing such as when the SSD 1 is activated.

  When the correspondence between the logical address given from the host device 10 and the logical BA of the NAND memory 4 is updated due to data writing or data erasing in the NAND memory 4, the host address developed in the RAM 2 is updated. The conversion table 21 is updated.

  The BA conversion table 23A and the validity management table 24A are constructed, for example, when the SSD 1 is used for the first time. In addition, when the validity of the logical BA, the number of rewrites, and the like are updated, the validity management table 24A expanded in the RAM 2 is updated.

  The read / write buffer 22 is a buffer memory used when data is transferred between the NAND memory 4 and the host device 10. Data read from the NAND memory 4 is buffered by the read / write buffer 22 and sent to the host device 10. The data requested to be written from the host device 10 is buffered by the read / write buffer 22 and written to the NAND memory 4.

  The controller 3 fetches the table group (the host address conversion table 21, the BA conversion table 23A, the validity management table 24A) stored in the NAND memory 4 into the RAM 2 at a predetermined timing (such as at the time of activation), and the RAM 2 The table group is stored in the NAND memory 4 at a predetermined timing. The controller 3 performs data transfer between the host device 10 and the NAND memory 4 via the RAM 2.

  The controller 3 controls the RAM 2 and the NAND memory 4 by using the BA conversion table 23A and the validity management table 24A, thereby performing data read / write control on the NAND memory 4. The controller 3 includes a table construction unit (Generator) 31, a write control unit 32, a read control unit 33, a host address conversion unit 34, and a block address conversion unit 35.

  The table construction unit 31 constructs the BA conversion table 23A and the validity management table 24A using the continuity of the logical BA and physical BA address numbers. The table construction unit 31 may construct the BA conversion table 23A and the validity management table 24A at any timing. The table construction unit 31 may reconstruct the BA conversion table 23A and the validity management table 24A as necessary.

  The write control unit 32 writes data into the NAND memory 4 using the host address conversion table 21, the BA conversion table 23A, and the validity management table 24A in the RAM 2.

  The read control unit 33 reads data from the NAND memory 4 using the host address conversion table 21, the BA conversion table 23A, and the validity management table 24A in the RAM 2.

  The write control unit 32 and the read control unit 33 perform data management in the RAM 2 and the NAND memory 4 based on the table group while updating the table group in the RAM 2 and the NAND memory 4 at the time of data transfer.

  The host address conversion unit 34 converts a logical address into a logical BA using the host address conversion table 21. The host address conversion unit 34 converts the logical address into a logical BA using the host address conversion table 21.

  The block address conversion unit 35 converts the logical BA into a physical BA that is a storage position in the NAND memory 4 using the BA conversion table 23A and the validity management table 24A. The block address conversion unit 35 converts the physical BA into a logical BA using the BA conversion table 23A and the validity management table 24A.

  For example, when data is written in the NAND memory 4, the write control unit 32 refers to the validity management table 24A and selects a valid logical block (a writable logical block) that is not used. Then, the write control unit 32 writes the data designated by the logical address to the selected logical block. Furthermore, the write control unit 32 registers the correspondence between the logical BA and logical address of the selected logical block in the host address conversion table 21.

  When reading data from the NAND memory 4, the read control unit 33 sends a data conversion instruction to the host address conversion unit 34 and the block address conversion unit 35. As a result, the host address conversion unit 34 converts the logical address into a logical BA using the host address conversion table 21.

  The SSD 1 receives a read / write instruction from the host device 10 via an interface (not shown). The interface between the host device 10 and the SSD 1 conforms to, for example, the SATA (Serial ATA) standard, but is not limited thereto.

  The NAND memory 4 is a nonvolatile semiconductor memory such as a NAND flash memory. The NAND memory 4 includes a memory cell array in which a plurality of nonvolatile memory cells are arranged in a matrix and a peripheral circuit for controlling write, read, and erase operations for the memory cell array. The memory cell array is configured by arranging a plurality of blocks which are the minimum unit of data erasure. Each block is configured by arranging a plurality of pages which are the minimum unit of data writing and reading. Each memory cell may be configured to store 1 bit, or may be configured to store 2 bits or more. In the NAND memory 4, rewriting to the same page in the block is permitted only after the entire block including the page is once erased.

  Data written from the host device 10 to the SSD 1 is stored in the NAND memory 4 in a predetermined management unit. Using consecutive addresses on the logical BA space as units of logical-physical conversion (conversion between logical BA and physical BA), the continuous addresses are collectively allocated to a physical area on the NAND memory 4. Within a management unit, a plurality of sectors with consecutive logical BAs are arranged in order. Although the size of the management unit is arbitrary, it can be matched with, for example, the page size or block size of the NAND memory 4 or the cluster size of the file system adopted by the host device 10. Note that the cluster size is not less than the sector size and not more than the block size.

  When the update data written from the host device 10 is not aligned with the management unit, the data already stored in the area of the management unit size on the NAND memory 4 and the size of the management unit are not reached. The newly written update data is merged on the RAM 2 to create management unit data, which is then written into the empty area of the NAND memory 4 (read-modify-write). The logical BA on the NAND memory 4 to which the data written from the host device 10 is written changes dynamically, and the corresponding relationship is managed by the host address conversion table 21. As the logical address, for example, an LBA (Logical Block Address) in which a serial number from 0 to the sector is assigned to the logical capacity is employed.

  Here, a correspondence relationship between the LBA aligned in the management unit and the data area allocated to the management unit on the NAND memory 4 will be described. The logical address specified by the host device 10 in the write request is in units of sectors, but in the SSD 1, the logical addresses are aligned in the size of the management unit (for example, cluster size). Then, sectors corresponding to consecutive LBAs in the management unit are collectively stored in the management unit area of the NAND memory 4. For example, when the size of the management unit is equal to the cluster size, a plurality of sectors corresponding to the LBAs aligned with the cluster size are written into the area of the cluster size of the NAND memory 4.

  FIG. 2 is a diagram for explaining address conversion performed in the SSD. A table indicating in which logical BA the data designated by the logical address is written is the host address conversion table 21. A table indicating which physical BA in the NAND memory 4 is written with data indicated by the logical BA is the BA conversion table 23A.

  For example, when writing data into the NAND memory 4, the logical address 41 is designated from the host device 10. The write control unit 32 refers to the validity management table 24A and selects a valid logical block that is not used. Then, the write control unit 32 writes the data designated by the logical address to the selected logical block. Furthermore, the write control unit 32 registers the correspondence between the logical BA and logical address of the selected logical block in the host address conversion table 21. Further, the block address conversion unit 35 converts the logical BA 42 into the physical BA 43 using the BA conversion table 23A. Then, the write control unit 32 sends a write command including the physical BA 43 to the NAND memory 4. As a result, data is written to the physical BA 43 corresponding to the logical address 41.

  Similarly, when data is read from the NAND memory 4, the logical address 41 is designated from the host device 10. The host address conversion unit 34 converts the logical address 41 into the logical BA 42 using the host address conversion table 21. Further, the block address conversion unit 35 converts the logical BA 42 into the physical BA 43 using the BA conversion table 23A. Then, the read control unit 33 sends a read command including the physical BA 43 to the NAND memory 4. As a result, data is read from the physical BA 43 corresponding to the logical address 41.

  Thus, in the computer system having the SSD 1, when accessing the data in the NAND memory 4, the logical BA is converted into the physical BA using the BA conversion table 23A.

  Next, the BA conversion table 23A, which is one of the features of this embodiment, will be described. FIG. 3 is a diagram illustrating a configuration example of the BA conversion table and the validity management table according to the first embodiment. 3A shows the BA conversion table 23A, and FIG. 3B shows the validity management table 24A.

  In the BA conversion table 23A, logical BAs having consecutive addresses are associated with physical BAs having consecutive addresses. Specifically, in the BA conversion table 23A, a continuous 16-block logical BA and a continuous 16-block physical BA are associated with each other.

  For example, the table construction unit 31 sets 16 blocks of logical BAs “00” to “15” in one logical BA group. In other words, a plurality of logical BAs are set in one entry in the BA conversion table 23A. In the BA conversion table 23A of FIG. 3, the group of logical BAs “00” to “15” is indicated by “logical BA 00/15”.

  In addition, the table construction unit 31 associates a set of physical BAs (physical BA group group) corresponding to the number of 64 slots corresponding to the logical BAs “00” to “15” with the logical BAs “00” to “15”. Each physical BA group in the physical BA group group is a physical BA for 16 blocks. Accordingly, the table construction unit 31 sets, for example, 16 blocks of physical BAs in one physical BA group.

  For example, the table construction unit 31 sets 16 blocks of physical BAs “x + 0” to “x + 15” to one physical BA group, and sets 16 blocks of physical BAs “v + 0” to “v + 15” to one physical BA group. Set to.

  Then, the table construction unit 31 assigns physical BAs “x + 0” to “x + 15” to the physical BA groups corresponding to the slot “00” of the logical BAs “00” to “15”. Further, the table construction unit 31 assigns physical BAs “v + 0” to “v + 15” to the physical BA group corresponding to the slot “63” of the logical BAs “00” to “15”.

  For example, the head addresses of physical BAs “x + 0” to “x + 15” and physical BAs “v + 0” to “v + 15” are registered in the BA conversion table 23A. In FIG. 3A, physical BA groups of physical BAs “x + 0” to “x + 15” are indicated by physical BA “x”. In FIG. 3A, physical BA groups of physical BAs “v + 0” to “v + 15” are indicated by physical BA “v”.

  Similarly, the table construction unit 31 sets 16 blocks of logical BAs “N” to “N + 15” (N is a multiple of 16) in one logical BA group. Then, the table construction unit 31 registers 16 blocks of physical BAs as one physical BA group in each slot in the BA conversion table 23A. Thus, the table construction unit 31 associates the physical BA group of each slot with the logical BA group and registers them in the BA conversion table 23A.

  In the BA conversion table 23A of FIG. 3, indexes such as logical BAs “00” to “15” and Slot “00” are shown, but the indexes may be omitted. In this case, the physical BA is read from the BA conversion table 23A on the assumption that each logical BA group includes 16 blocks of logical BA and the number of slots in each logical BA group is 64.

  The physical BA includes bad blocks that cannot be used as a storage area due to many errors. For example, a physical block may become a bad block due to an erase error or a program error (write failure).

  The validity management table 24A shown in FIG. 3B is a table for managing the validity of each logical block. In the validity management table 24A, the logical BA of each logical block is associated with information indicating validity (validity information). A logical block whose information indicating validity is “valid” is a normal logical block (good block), and a logical block whose information indicating validity is “invalid” is a bad block.

  For example, when the physical BA “v + 1” corresponding to the slot “63” of the physical BA “00” to “15” is a bad block, the logical BA “01” corresponding to the physical BA “v + 1” is the validity management table 24A. Registered as “invalid”. The validity management table 24A may register the number of erasures of each logical BA group.

  Here, a procedure for reading data from the NAND memory 4 will be described. FIG. 4 is a flowchart showing a procedure for reading data from the NAND memory. The host device 10 sends a read command and a logical address 41 to be read out to the controller 3 of the SSD 1.

  The host address conversion unit 34 of the controller 3 converts the logical address 41 into the logical BA 42 using the host address conversion table 21 (step S10). At this time, the host address conversion unit 34 converts the logical address 41 into a logical BA 42 and an offset within the logical block. The offset value is a value used when the slot position is calculated, and the offset unit is a data management unit in the SSD 1. The host address conversion unit 34 calculates the slot position C (C is any of 00 to 63) using the offset value.

  Further, the block address conversion unit 35 converts the logical BA 42 into the physical BA 43 using the BA conversion table 23A. Specifically, the block address conversion unit 35 calculates a value “A” and a remainder “B” obtained by dividing the logical BA by 16 (step S20). Then, the block address conversion unit 35 sets the “A + 1” level of the BA conversion table 23A as a physical BA read target position. The block address conversion unit 35 reads the physical BA at the slot position C at the “A + 1” level from the BA conversion table 23A (step S30). The block address conversion unit 35 calculates a value obtained by adding “B” to the read physical BA as the read-out physical BA 43 (step S40).

  The physical BA 43 calculated by the block address conversion unit 35 is a physical BA corresponding to the logical address 41 sent from the host device 10. The read control unit 33 sends a read command including the physical BA 43 to the NAND memory 4. Thereby, the data of the physical BA 43 corresponding to the logical address 41 is read.

  In this embodiment, the logical BA group and the physical BA group are configured by 16 block address groups. However, the logical BA group and the physical BA group may be configured by two or more block address groups. That's fine.

  Further, in this embodiment, the case where 64 slots are allocated to the logical BA group has been described, but the number of slots allocated to the logical BA group may be less than 64, or may be 65 or more. .

  As described above, according to the first embodiment, in the BA conversion table 23A, the logical BA having consecutive addresses and the physical BA having consecutive addresses are associated with each other. 23A can be efficiently compressed. Therefore, the memory capacity of the RAM 2 necessary for the SSD 1 can be reduced.

  In addition, since the size of the BA conversion table 23A stored in the NAND memory 4 or RAM 2 is reduced, the life of the SSD 1 can be extended. In addition, since the size of the BA conversion table 23A stored in the NAND memory 4 is reduced, it is possible to reduce the time required for writing and reading the BA conversion table 23A to the NAND memory 4.

  In addition, since the size of the BA conversion table 23A is reduced, it is possible to shorten the startup time of the SSD 1 and the transition time to the standby state. In addition, it is possible to reduce the cost of block address conversion from the logical BA to the physical BA. Further, the BA conversion table 23A can be constructed without increasing the number of logical blocks.

  Further, by using the BA conversion table 23A, the address conversion between the logical BA and the physical BA is accelerated (the address conversion is not delayed as compared with the case where the compression is not performed).

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, physical BA groups having substantially the same number of good blocks are collected and associated with one logical BA group.

  FIG. 5 is a flowchart showing a procedure for constructing a BA conversion table according to the second embodiment. FIG. 6 is a diagram for explaining a BA conversion table construction process (previous process) according to the second embodiment. FIG. 7 is a diagram illustrating a BA conversion table construction process according to the second embodiment. It is a figure for demonstrating latter process.

  As illustrated in FIG. 6, the table construction unit 31 accesses the NAND memory 4 and reads a physical block state 51 indicating a physical block state (valid / invalid) of the NAND memory 4 for each physical BA (step S110). . Is read. In the physical block state 51, the validity / invalidity of each physical block is shown in the order of the physical BA. FIG. 6 shows a case where the physical blocks “02”, “24”, and “31” in the physical block state 51 are bad blocks (invalid).

  Based on the physical block state 51, the table construction unit 31 generates a physical BA group and arranges the physical BA group (step S120). For example, the table construction unit 31 extracts 16 physical BAs from the physical block state 51 in order of increasing address values as physical BA groups. At this time, if the physical BA group composed of 16 physical BAs includes a bad block physical BA, the table construction unit 31 changes the physical block of the next good block after the bad block to the next physical BA group. Of the first physical BA. In the following, the bad block physical BA is referred to as a bad physical BA, and the good block physical BA is referred to as a good physical BA.

  For example, when generating a physical BA group from the physical block state 51 shown in FIG. 6, the table construction unit 31 extracts physical BAs “00” to “15” as one physical BA group. Specifically, the table construction unit 31 extracts the physical BAs “00” to “15” as the first physical BA group G1 (s1 in FIG. 6).

  Here, since the physical BA “02” is a bad physical BA, the table construction unit 31 sets the next physical BA “02” to be the physical BA “02” which is the next good physical BA of the physical BA “02”. 03 ". Then, the table construction unit 31 extracts a total of 16 physical BAs starting from the physical BA “03” as one physical BA group. Specifically, the table construction unit 31 extracts physical BAs “03” to “19” as one physical BA group G2 (s2 in FIG. 6).

  When a plurality of bad physical BAs are consecutive, the table construction unit 31 sets the next good physical BA after the continuous bad physical BA is interrupted as the top physical BA of the next physical BA group.

  The table construction unit 31 extracts the physical BAs “03” to “19” as the second physical BA group G2, and then extracts the third physical BA group. Here, since the bad physical BA is not included in the physical BAs “03” to “19”, the table constructing unit 31 sets the first physical BA of the next physical BA group as the physical BA “20”. Then, the table construction unit 31 extracts a total of 16 physical BAs starting from the physical BA “20” as one physical BA group. Specifically, the table construction unit 31 extracts the physical BAs “20” to “35” as the third physical BA group G3 (s3 in FIG. 6).

  Here, since the physical BA “24” is a bad physical BA, the table constructing unit 31 sets the top physical BA of the next physical BA group as the physical BA “25”. Then, the table construction unit 31 extracts a total of 16 physical BAs starting from the physical BA “25” as one physical BA group. Specifically, the table construction unit 31 extracts physical BAs “25” to “40” as the fourth physical BA group G4 (s4 in FIG. 6).

  Here, since the physical BA “31” is a bad physical BA, the table construction unit 31 sets the first physical BA of the next physical BA group as the physical BA “32”. The table construction unit 31 then extracts a total of 16 physical BAs starting from the physical BA “32” as a fifth physical BA group G5 (s5 in FIG. 6).

The table construction unit 31 groups all physical BAs into physical BA groups. That is, the table construction unit 31 repeats the following process.
(1) The table construction unit 31 extracts a total of 16 consecutive physical BAs as one physical BA group.
(2) If a bad physical BA is included in the extracted physical BA group, the table construction unit 31 sets the first good physical BA after the bad physical BA as the first physical BA in the next physical BA group. .

  Furthermore, the table construction unit 31 sets all physical BAs after the first bad physical BA in each physical BA group as bad physical BAs. For example, in the physical BA group G1 composed of the physical BAs “00” to “15”, the physical BA “02” is a bad physical BA, so the table construction unit 31 uses the physical BAs “02” to “15” in the physical BA group G1. Are all set to the bad physical BA.

  As a result, the number of bad physical BAs of the physical BA group G1 including the physical BAs “00” to “15” is set to 14. The number of bad physical BAs in the physical BA group G2 is set to 0, and the number of bad physical BAs in the physical BA group G3 is set to 12.

  Then, the table construction unit 31 organizes physical BA groups. Specifically, the table construction unit 31 generates bad block number information 52 by grouping each physical BA group by the number of bad physical BAs (s11 to s14 in FIG. 6). The bad block number information 52 is information obtained by grouping each physical BA group by the number of bad physical BAs. In the bad block number information 52, the number of bad physical BAs is associated with a physical BA group (group list).

  For example, in the bad block number information 52, a physical BA group G2 composed of physical BAs “03” to “19” is registered in a physical BA group having zero bad physical BA numbers. In the bad block number information 52, the physical BA “03” that is the first physical BA in the physical BA group G2 may be registered as information indicating the physical BA group G2.

  Similarly, in the bad block number information 52, the physical BA group G1 is registered in the physical BA group having 14 bad physical BA numbers. In the bad block number information 52, the physical BA “00”, which is the first physical BA in the physical BA group G1, is registered as information indicating the physical BA group G1.

  Thereafter, the table construction unit 31 constructs a BA conversion table 23B described later using the bad block number information 52. The BA conversion table 23B is a table having the same configuration as the BA conversion table 23A. That is, in the BA conversion table 23B, the physical BA groups for 64 slots are associated with one logical BA group.

  In order to construct the BA conversion table 23B, the table construction unit 31 sequentially extracts, from the bad block number information 52, physical BA groups having a small number of bad physical BAs by the number of 64 slots (s21 in FIG. 7). In other words, the physical BA groups are extracted from the entire physical BA group by 64 slots in the order of the number of good blocks. FIG. 7 shows a case where physical BA groups having 4 to 3 bad physical BAs are extracted by the number of 64 slots. Hereinafter, the physical BA groups for 64 slots extracted by the processing of s21 are referred to as physical BA group group Hx.

  The table construction unit 31 extracts the physical BAs “W” to “W + 15” as one physical BA group, and extracts the physical BAs “X” to “X + 15” as one physical BA group. Similarly, the table construction unit 31 extracts the physical BAs “Y” to “Y + 15” as one physical BA group and extracts the physical BAs “Z” to “Z + 15” as one physical BA group. In this way, the table construction unit 31 extracts 64 physical BA group groups Hx for 64 groups (the number of 64 slots) with 16 physical BAs as one physical BA group.

  Then, the table construction unit 31 forms a logical BA group for each physical BA corresponding to the extracted 64 slots. Specifically, the table construction unit 31 determines whether or not a logical BA group (a group of 16 logical BAs) can be formed using the extracted physical BA groups for the 64 slots (step S130). ). The table construction unit 31 determines that the logical BA groups can be formed using the physical BA groups for the 64 slots when the logical BAs for the 64 slots are extracted.

  When a logical BA group can be formed (step S130, Yes), the table construction unit 31 forms a logical BA group and registers it in the BA conversion table 23B (step S140). The physical BA group registered in the BA conversion table 23B is deleted from the bad block number information 52.

  The table construction unit 31 sets validity for each logical BA in the logical BA group when registering the logical BA group in the BA conversion table 23B. At this time, the table construction unit 31 selects the physical BA group of the slot with the largest number of bad physical BAs from the physical BA group group Hx. Since the table construction unit 31 extracts the physical BA groups in the order from the smallest number of bad physical BAs, the table construction unit 31 selects the physical BA group of the slot 63 which is the last slot (the physical BA group of the physical BA “Z”). Then, all the physical BAs set in the same stage as the bad physical BA of the selected physical BA group are set as the bad physical BA.

  In other words, in the physical BA group group, the table construction unit 31 has the least number of good blocks in the physical BA group group, and the number of consecutive bad blocks in each physical BA group and the number of consecutive good blocks from the top. A bad block is set in each physical BA group so as to have the same value as the physical BA group.

  For example, in the physical BA group of Slot 63, when the Mth (M is a natural number) level or later is a bad physical BA, all the physical BA groups of other Slots are also set as the bad physical BA after the Mth level. In the case of FIG. 7, in the physical BA group of the physical BA “Z”, the c3th level is a good physical BA, and the c4th level and later are bad physical BAs. For this reason, the table construction unit 31 sets the logical BA group group Hx2 in which all the physical BA groups of Slot 00 to 63 are set as the good physical BA and the c4th and subsequent stages are set as the bad physical BAs. (Not shown).

  In the case of the physical BA group group Hx extracted in s21 of FIG. 7, the physical BA “W + 4” and the physical BA “X + 4” are c4th-stage physical BAs. Therefore, the table construction unit 31 generates a logical BA group group Hx2 in which the physical BA “W + 4” or the physical BA “X + 4” is set as the bad physical BA.

  Then, the physical BAs of slots 00 to 63 in the c0 stage are set as one logical BA, and the physical BAs of slots 00 to 63 in the c1 stage are set as one logical BA. Similarly, the physical BAs of slots 00 to 63 in the c3 stage, the physical BAs of slots 00 to 63 in the c4 stage,..., And the physical BAs of slots 00 to 63 in the c15 stage are set as one logical BA. . Then, the table construction unit 31 sets validity for each logical BA.

  FIG. 8 is a diagram illustrating a configuration example of the BA conversion table and the validity management table according to the second embodiment. FIG. 8A shows the BA conversion table 23B, and FIG. 8B shows the validity management table 24B. The BA conversion table 23B is a table having the same configuration as the BA conversion table 23A, and the validity management table 24B is a table having the same configuration as the validity management table 24A.

  A physical BA group group Hx2 corresponding to the logical BA group is registered in the BA conversion table 23B. In the case of the physical BA group group Hx2, the physical BAs “W” to “Z” in the c0 stage are set to the logical BA “P”, and the physical BAs “W + 1” to “Z + 1” in the c1 stage are the logical BA “P + 1”. Set to Similarly, c3 stage physical BAs “W + 3” to “Z + 3”, c4 stage physical BAs “W + 4” to “Z + 4”,..., C15 stage physical BAs “W + 15” to “Z + 15” The logical BAs are set to “P + 3”, “P + 4” to “P + 15”, respectively.

  Then, 16 blocks of logical BA “P” to “P + 15” are set in one logical BA group, and are associated with the physical BA group group Hx2 of 16 blocks × 64 slots, and are stored in the BA conversion table 23B. be registered.

  In the BA conversion table 23B of FIG. 8A, logical BA groups of logical BAs “P” to “P + 15” are indicated by “logical BA P / (P + 15)”. Also, the first physical BA of the physical BA group is registered in the physical BA group of each slot. Accordingly, the physical BAs “W” to “Z” are registered in the BA conversion table 23B in association with “logical BA P / (P + 15)” (s22 in FIG. 7).

  The table construction unit 31 registers the validity of each logical BA in the logical BA group in the validity management table 24B (step S150). Here, since the logical BAs “P” to “P + 3” up to the c0 to c3 stages are set as the good physical BA, “valid” is set to the logical BAs “P” to “P + 3”. In addition, since the c4 to c15th stages are set as bad physical BAs, “invalid” is set to the logical BAs “P + 4” to “P + 15” from the c4th to c15th stages.

  Thereafter, the good block of the invalid logical BA is changed to the physical BA group and arranged (step S160). Specifically, the table construction unit 31 extracts a physical BA group having a physical BA converted from a good physical BA to a bad physical BA when generating the physical BA group group Hx2 from the physical BA group group Hx. To do. In other words, the table construction unit 31 extracts a physical BA group having a good physical BA that has not been registered in the BA conversion table 23B from the physical BA group group Hx.

  Here, since the good blocks of the physical BAs “W + 4” to “X + 4” are not used when forming the logical BA group of the physical BA group group Hx, the table construction unit 31 uses the physical BAs “W + 4” to “X + 4”. To create a new logical BA group. At this time, the top of the logical BA group is the physical BA “W + 4”, and the number of bad blocks is 15.

  In other words, when the physical BA group group Hx2 is generated, the physical BAs “W + 4” to “X + 4” are converted into bad physical BAs, so the physical BA groups of the physical BAs “W” to “X” are extracted. (S23 in FIG. 7).

  Then, the table construction unit 31 generates a new physical BA group using a good physical BA that has not been registered in the BA conversion table 23B (hereinafter referred to as an unregistered physical BA) for each extracted physical BA group. At this time, the table construction unit 31 sets the unregistered physical BA having the smallest value among the extracted physical BA groups as the first physical BA of the new physical BA group. The table construction unit 31 generates a new physical BA group for all the extracted physical BA groups.

  Here, a physical BA group consisting of physical BAs “W + 4” to “W + 19” and a physical BA group consisting of physical BAs “X + 4” to “X + 19” are generated as new physical BA groups.

  Then, the table construction unit 31 registers the generated new physical BA group in the bad block number information 52 (s24 in FIG. 7). For example, a physical BA group composed of physical BAs “W + 4” to “W + 19” has one good physical BA number, and is registered in a group list with 15 bad physical BA numbers.

  The table construction unit 31 repeats the same processing as s21 to s24 of FIG. 7 described above using the newly registered bad block number information 52. As a result, the physical BA group newly registered in the bad block number information 52 is also registered in the BA conversion table 23B. At this time, the newly registered physical BA group forms a physical BA group group for 64 slots together with other physical BA groups, and is registered in the BA conversion table 23B as the physical BA group group.

  Specifically, the physical BAs “W + 4” to “X + 4” in the d0 stage are set to the logical BA “Q”, and the physical BAs “W + 5” to “X + 5” in the d1 stage are set to the logical BA “Q + 1”. , D15th-stage physical BAs “W + 19” to “X + 19” are set to the logical BA “Q + 15”. Similarly, the physical BA “S” to “T” in the d0 stage of the other physical BA group are set to the logical BA “Q”.

  The physical BA group registered in the BA conversion table 23B does not have to be 16 physical BAs. For example, a new physical BA group composed of 12 physical BAs “W + 4” to “W + 19” may be registered in the BA conversion table 23B. In this case, logical BAs corresponding to the 13th and subsequent physical BAs are set to “invalid” in the bad block number information 52. In other words, in a new physical BA group, when the number of physical BAs is less than 16, it is treated that a bad block exists at the location of the missing physical BA.

  After the logical BA is set, the logical BA “Q” to “Q + 15” for 16 blocks are set in one logical BA group, and the physical BA group group Hx3 (16 blocks × 64 slots) (not shown) Are registered in the BA conversion table 23B.

  In the BA conversion table 23B of FIG. 8A, a group of logical BAs “Q” to “Q + 15” is indicated by “logical BA Q / (Q + 15)”. In addition, the first physical BA of the physical BA group is registered in the physical BA of each slot. Thereby, the physical BAs “W + 4” to “X + 4” and “S” to “T” are registered in the BA conversion table 23B in association with “logical BA Q / (Q + 15)”.

  Then, the table construction unit 31 registers the validity of each logical BA in the logical BA group in the validity management table 24B. Here, since the logical BA “Q” in the d0 stage is set to the good physical BA, “valid” is set to the logical BA “Q”. In addition, since the d1 to d11 stages are set as bad physical BAs and there are no physical BAs in the d12 to d15 stages, the logical BAs “Q + 1” to “Q + 15” up to the d1 to d15 stages have “Invalid” is set.

  Thereafter, the processes of steps S130 to S160 are repeated until a logical BA group cannot be formed. When it becomes impossible to form a logical BA group (step S130, No), the generation process of the BA conversion table 23B ends.

  If there are more physical BA groups than the number of 64 slots, the table construction unit 31 registers the physical BA group group in the BA conversion table 23B while maintaining the number less than 64 slots. In this case, when there are a plurality of good blocks in the physical BA group, the physical BA group may be divided into a plurality of blocks and the good blocks may be distributed to the divided physical BA groups. For example, when a physical BA group having two good blocks remains, the table construction unit 31 has two physical BAs, a physical BA group having one good block and a physical BA group having one good block. Create a group. Then, the table construction unit 31 generates a physical BA group group using two physical BA groups, and registers the physical BA group group in association with the logical BA group in the BA conversion table 23B.

  When the BA conversion table 23B is configured, if there is a bad block, a logical block corresponding to the bad block cannot be used. In this embodiment, the BA conversion table 23B is constructed while organizing the bad blocks, thereby increasing the degree of compression of the BA conversion table 23B, thereby reducing the memory capacity of the RAM 2 necessary for the SSD 1.

  As described above, when the table construction unit 31 constructs the BA conversion table 23B, the physical BA groups having substantially the same number of good blocks are collected and associated with one logical BA group. As a result, the compression rate of the BA conversion table 23B can be increased.

  FIG. 9 is a perspective view showing an example of a personal computer equipped with an SSD. The personal computer 1200 includes an SSD 1, a main body 1201, and a display unit 1202. Here, a case where the personal computer 1200 includes the SSD 1 will be described. The display unit 1202 includes a display housing 1203 and a display device 1204 accommodated in the display housing 1203.

  The main body 1201 includes a housing 1205, a keyboard 1206, and a touch pad 1207 that is a pointing device. The housing 1205 accommodates a main circuit board, an ODD (optical disk device) unit, a card slot, an SSD 1 and the like.

  The card slot is provided adjacent to the peripheral wall of the housing 1205. An opening 1208 facing the card slot is provided on the peripheral wall. The user can insert / remove an additional device into / from the card slot from the outside of the housing 1205 through the opening 1208.

  The SSD 1 may be used as a state of being mounted inside the personal computer 1200 as a replacement for a conventional HDD, or may be used as an additional device while being inserted into a card slot included in the personal computer 1200.

  FIG. 10 shows a system configuration example of a personal computer equipped with an SSD. The personal computer 1200 includes a CPU 1301, a north bridge 1302, a main memory 1303, a video controller 1304, an audio controller 1305, a south bridge 1309, a BIOS-ROM 1310, an SSD 1, an ODD unit 1311, an embedded controller / keyboard controller IC (EC / KBC) 1312, And a network controller 1313 and the like.

  The CPU 1301 is a processor provided to control the operation of the personal computer 1200, and executes an operating system (OS) loaded from the SSD 1 to the main memory 1303. Further, when the ODD unit 1311 enables execution of at least one of read processing and write processing on the loaded optical disc, the CPU 1301 executes those processing.

  The CPU 1301 also executes a system BIOS (Basic Input Output System) stored in the BIOS-ROM 1310. The system BIOS is a program for hardware control in the personal computer 1200.

  The north bridge 1302 is a bridge device that connects the local bus of the CPU 1301 and the south bridge 1309. The north bridge 1302 also includes a memory controller that controls access to the main memory 1303.

  The north bridge 1302 also has a function of executing communication with the video controller 1304 and communication with the audio controller 1305 via an AGP (Accelerated Graphics Port) bus or the like.

  The main memory 1303 temporarily stores programs and data and functions as a work area for the CPU 1301. The main memory 1303 is constituted by a DRAM, for example. A video controller 1304 is a video playback controller that controls a display unit 1202 used as a display monitor of the personal computer 1200.

  The audio controller 1305 is an audio playback controller that controls the speaker 1306 of the personal computer 1200. The south bridge 1309 controls each device on an LPC (Low Pin Count) bus 1314 and each device on a PCI (Peripheral Component Interconnect) bus 1315. The south bridge 1309 controls the SSD 1 that is a storage device for storing various software and data via the ATA interface.

  The personal computer 1200 accesses the SSD 1 on a sector basis. A write command, a read command, a flash command, and the like are input to the SSD 1 via the ATA interface (I / F).

  The south bridge 1309 also has a function for controlling access to the BIOS-ROM 1310 and the ODD unit 1311. The EC / KBC 1312 is a one-chip microcomputer in which an embedded controller for power management and a keyboard controller for controlling the keyboard (KB) 1206 and the touch pad 1207 are integrated. The EC / KBC 1312 has a function of turning on / off the power of the personal computer 1200 according to the operation of the power button by the user. The network controller 1313 is a communication device that executes communication with an external network such as the Internet.

  The personal computer 1200 supplies power to the SSD 1 and issues a stop request (Standby request) to the SSD 1. Even if the power supply from the personal computer 1200 to the SSD 1 is illegally cut off, it is possible to prevent a write error from occurring.

  As described above, according to the second embodiment, since the physical BA group constituted by continuous physical BAs is registered in the BA conversion table 23B, the construction time of the BA conversion table can be shortened. Also, conversion from logical BA to physical BA can be performed in a short time.

  In addition, since the physical BA groups are assembled in the order of decreasing number of bad physical blocks, it is possible to collect bad physical blocks. Accordingly, the compression rate of the BA conversion table 23B can be increased.

  Further, since the BA conversion table 23B is constructed by sequentially extracting the physical BA groups having a small number of bad physical BAs, the BA conversion table 23B can be searched without searching for a combination of good blocks or a combination of bad blocks. Can be built. Therefore, the construction process of the BA conversion table 23B can be performed in a short time according to the linear order of the number of physical blocks.

  As described above, according to the first and second embodiments, data in the nonvolatile memory can be managed with a management table having a small size.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... SSD, 3 ... Controller, 4 ... NAND memory, 10 ... Host apparatus, 23A, 23B ... BA conversion table, 24A, 24B ... Effectiveness management table, 31 ... Table construction part, 35 ... Block address conversion part, 51 ... Physical block state, 52 ... bad block number information, Hx ... physical BA group group.

Claims (5)

A physical block address group is generated by extracting a first predetermined number of physical block addresses in a non-volatile memory arranged in a semiconductor storage device used as an external storage device of a computer system, in order from the smallest address value. A first group generation step,
When the physical block address of the bad block is included in the physical block address group, the physical block address of the first good block after the bad block is changed to the first physical block address of the next physical block address group. And a second group generation step for generating the next physical block address group,
A first bad block setting step for setting all physical block addresses after the first bad block to bad blocks for each of the physical block address groups;
A group group generating step of generating a physical block address group group by extracting the physical block address group by a second predetermined number in order of increasing the number of good blocks from the whole of the physical block address group;
For each of the generated physical block address groups, the number of consecutive bad blocks in each physical block address group and the number of consecutive good blocks from the top are the least in the physical block address group. A second bad block setting step for setting a bad block in each physical block address group so as to have the same value as the physical block address group;
A logical block address group that is a plurality of continuous logical block addresses set by using a logical block address in the nonvolatile memory corresponding to a logical address specified by a host device, and the physical block address group group. A table generation step for generating an associated address management table;
The validity management table in which validity information indicating whether or not each logical block address in the logical block address group is a good block is set in the logical block address, whether or not the physical block address is a good block A validity setting step to generate based on
A third group generation step of generating the physical block address group using the physical block address set in the bad block in the second bad block setting step;
Including
For the physical block address group generated in the third group generation step, the second group generation step, the first bad block setting step, the group group generation step, the second bad block setting step, A management information generation method comprising repeating the table generation step, the validity setting step, and the third group generation step. A physical block address group is generated by extracting a first predetermined number of physical block addresses in a non-volatile memory arranged in a semiconductor storage device used as an external storage device of a computer system, in order from the smallest address value. A first group generation step,
When the physical block address of the bad block is included in the physical block address group, the physical block address of the first good block after the bad block is changed to the first physical block address of the next physical block address group. And a second group generation step for generating the next physical block address group,
A first bad block setting step for setting all physical block addresses after the first bad block to bad blocks for each of the physical block address groups;
A group group generating step of generating a physical block address group group by extracting the physical block address group by a second predetermined number in order of increasing the number of good blocks from the whole of the physical block address group;
For each of the generated physical block address groups, the number of consecutive bad blocks in each physical block address group and the number of consecutive good blocks from the top are the least in the physical block address group. A second bad block setting step for setting a bad block in each physical block address group so as to have the same value as the physical block address group;
A logical block address group that is a plurality of continuous logical block addresses set by using a logical block address in the nonvolatile memory corresponding to a logical address specified by a host device, and the physical block address group group. A table generation step for generating an associated address management table;
A management information generation method comprising: The validity management table in which validity information indicating whether or not each logical block address in the logical block address group is a good block is set in the logical block address, whether or not the physical block address is a good block A validity setting step to generate based on
A third group generation step of generating the physical block address group using the physical block address set in the bad block in the second bad block setting step;
Further including
For the physical block address group generated in the third group generation step, the second group generation step, the first bad block setting step, the group group generation step, the second bad block setting step, and the The management information generation method according to claim 2, wherein a table generation step is performed. The validity management table in which validity information indicating whether or not each logical block address in the logical block address group is a good block is set in the logical block address, whether or not the physical block address is a good block A validity setting step to generate based on
A third group generation step of generating the physical block address group using the physical block address set in the bad block in the second bad block setting step;
Further including
For the physical block address group generated in the third group generation step, the second group generation step, the first bad block setting step, the group group generation step, the second bad block setting step, The management information generation method according to claim 2, wherein the table generation step, the validity setting step, and the third group generation step are repeated. Non-volatile memory;
A controller that performs data read / write control on the nonvolatile memory based on a logical address designated by a host device;
With
The controller is
A table construction unit for constructing an address management table in which a logical block address in the nonvolatile memory corresponding to the logical address is associated with a physical block address in the nonvolatile memory corresponding to the logical block address; ,
The nonvolatile memory stores the address management table, and the controller performs data read / write control with respect to the nonvolatile memory using the address management table,
The table construction unit
The physical block address is extracted by a first predetermined number in order from a smaller address value to generate a physical block address group,
When the physical block address of the bad block is included in the physical block address group, the physical block address of the first good block after the bad block is changed to the first physical block address of the next physical block address group. To generate the next physical block address group,
For each of the physical block address groups, all physical block addresses after the first bad block are set as bad blocks,
The physical block address group is generated by extracting a second predetermined number of the physical block address groups in order of increasing number of the good blocks from the entire physical block address group,
For each of the generated physical block address groups, the number of consecutive good blocks and the number of consecutive bad blocks from the beginning of each physical block address group of the physical block address group Set a bad block in each physical block address group so that it has the same value as the physical block address group with the fewest good blocks,
A logical block address group that is a plurality of continuous logical block addresses set by using a logical block address in the nonvolatile memory corresponding to a logical address specified by a host device, and the physical block address group group. A memory system that generates an associated address management table.

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