JP5691739B2 - Voltage generation circuit - Google Patents

Description

  The present invention relates to a technique for generating a predetermined voltage.

  2. Description of the Related Art Conventionally, a technique (DC-DC converter) that generates a predetermined voltage and supplies it to a driving load by controlling a transistor connected to a DC power supply has been proposed. For example, Patent Document 1 proposes a technique for changing a cycle for controlling conduction / non-conduction of a transistor between a low load and a high load. Specifically, two systems of a reference clock signal having a predetermined frequency and a control clock signal having a variable frequency according to the load are generated in parallel, and the transistor is controlled according to the reference clock signal when the load is high. When the load is applied, the transistor is controlled in accordance with the control clock signal. According to the above configuration, it is possible to reduce power consumption when the load is low.

JP 2008-236822 A

However, in the technique of Patent Document 1, since the frequency of the control clock signal decreases as the load becomes light at low loads, the operating frequency of the transistor may enter the audible band. When a voltage generated by the DC-DC converter is used as a power supply voltage, a ripple component synchronized with the operating frequency of the transistor is superimposed on the power supply voltage. When a conventional DC-DC converter is used as a power supply voltage for a circuit that processes an audible band signal, there is a problem that noise is superimposed on the signal.
In view of the above circumstances, an object of the present invention is not to generate power supply noise even when the load is lightened.

  Means employed by the present invention to solve the above problems will be described. In order to facilitate the understanding of the present invention, in the following description, the correspondence between the elements of the present invention and the elements of the embodiments described later will be indicated in parentheses, but the scope of the present invention will be exemplified in the embodiments. It is not intended to be limited.

  The voltage generation circuit of the present invention includes a P-channel transistor (TR1), an output node (N) and an N-channel transistor (TR2) connected in series between a high-potential power supply and a low-potential power supply, and the voltage of the output node. An error signal generation unit (30) that generates an error signal (Err) that is a difference between the detection voltage (V1) corresponding to the reference voltage (V2), and is active only for a period corresponding to the magnitude of the error signal. When a control signal generation unit (50) that generates a control signal (CTL) and an active period of the control signal are longer than a reference time (Tref), a first time from the start of the active period until the reference time elapses When the P channel transistor is turned on in one period and the active period of the control signal is shorter than the reference time, the P channel transistor is turned on in the active period. A first driving unit (81) for switching on, a second driving unit (82 to 84) for controlling the N-channel transistor on or off, and a frequency of the control signal from a lower limit frequency (fmin) to an upper limit frequency (fmax) When the active period of the control signal is shorter than the reference time, the frequency of the control signal is the lower limit frequency, and when the active period of the control signal is longer than the reference time, A frequency control unit (60) for controlling the frequency of the control signal to be higher as the difference between the active period and the reference time becomes longer.

  According to the present invention, when the P-channel transistor and the N-channel transistor operate in synchronization with the control signal, the frequency of the control signal does not fall below the lower limit frequency. Therefore, the voltage output from the output node does not include a frequency component lower than the lower limit frequency. Therefore, when the voltage at the output node is smoothed and used as a power supply, the frequency component of the power supply ripple of the subsequent circuit can be set to the lower limit frequency or more.

  More specifically, the lower limit frequency is preferably higher than the audible band. In this case, even if the circuit in the subsequent stage processes a signal in the audible band, noise can be prevented from entering the audible band due to the power supply ripple.

  In the voltage generation circuit described above, the second drive unit turns on the N-channel transistor when the P-channel transistor is switched from on to off, and the reference time elapses after the P-channel transistor is turned on. If the potential of the output node falls below the low potential power supply before the time point, the N-channel transistor is turned off at the reference time point, and the potential of the output node is changed to the low potential power source after the reference time point. When the voltage is lower than, the N channel transistor is turned off when the potential of the output node is lower than the low potential power source.

According to the present invention, the N-channel transistor is turned on when the P-channel transistor is turned off, and turned off when the potential of the output node is lower than the low potential power source. However, if the potential of the output node falls below the low-potential power supply before the reference time, the N-channel transistor remains on even when the output node potential falls below the low-potential power supply, and the N-channel transistor is turned off at the reference time. Let Therefore, no matter how light the load is, the N-channel transistor and the P-channel transistor are always operated for the reference time. Therefore, the lower limit frequency of the ripple component superimposed on the voltage of the output node can be set.
In addition, when the N-channel transistor is operated when the potential of the output node is lower than the low potential power source, power consumption increases, but as the load becomes heavier, invalid power consumption decreases. Therefore, power consumption can be reduced as compared with the case where the lower limit frequency is set as the operating frequency of the transistor using the bleeder resistor.

In the voltage generation circuit described above, the frequency control unit includes a capacitive element (65), a comparison unit (68) that compares the voltage of the capacitive element with a predetermined voltage, and a supply unit that supplies current to the capacitive element ( 61, 62, 64) and a discharge unit (63) for discharging the electric charge charged in the capacitive element, and the supply unit is predetermined when the active period of the control signal is shorter than the reference time. When a current having a value is supplied to the capacitive element and an active period of the control signal is longer than the reference time, a time difference between the active period and the reference time is larger than the predetermined value. At other times, the current of the predetermined value is supplied to the capacitive element, and a reset signal (RES) for controlling the discharge unit is generated based on the output signal of the comparison unit. It was supplied to the control signal generating unit, the control signal generating section preferably generates the control signal in synchronization with the reset signal.
According to the present invention, when the voltage of the capacitive element reaches a predetermined voltage, a reset signal is generated, and the charge charged in the capacitive element is discharged by the reset signal, so that the frequency control unit functions as an oscillation circuit. Then, when the active period of the control signal is longer than the reference time, the charging current to the capacitive element is controlled so as to be increased by the difference between the active period and the reference time, so that the cycle of the reset signal is shortened. That is, when the load increases to a certain extent, the control signal can be controlled so that the frequency of the control signal increases according to the size of the load.

  In the voltage generation circuit described above, a reference signal generation unit (70) that generates a reference signal (72a) obtained by inverting a signal that becomes active during a period from the start of the active period of the control signal to the passage of the reference time; The second driving unit includes a detection signal generation unit (82) that generates a detection signal (82a) by detecting a period in which the potential of the output node is lower than the potential of the low-potential power supply, and the detection signal and the reference signal And a logic circuit (83) that calculates the logical product of the P channel transistor and a signal for controlling on / off of the P-channel transistor are supplied to the set terminal, and an output signal (83a) of the logic circuit is supplied to the reset terminal and output. It is preferable to include an SR flip-flop (84) for supplying a signal (DR2) to the gate of the N-channel transistor.

  According to the present invention, since the rise of the detection signal is masked by the reference signal by the logic circuit, even if the rise of the detection signal occurs before the reference time elapses after the P-channel transistor is turned on, this is masked. Thus, the N-channel transistor can be kept on, and the N-channel transistor can be turned off when the reference time has elapsed since the P-channel transistor was turned on. Thus, the N-channel transistor and the P-channel transistor are always operated only for the reference time. Therefore, the lower limit frequency of the ripple component superimposed on the voltage of the output node can be set.

It is a block diagram of the voltage generation circuit which concerns on embodiment of this invention. It is a timing chart of each signal. It is a graph which shows the relationship between the frequency of a reset signal, and load. 6 is a timing chart showing a relationship between a voltage of a node and various signals in a first region. It is explanatory drawing for demonstrating the relationship between the voltage of the node in a 1st area | region, and the ON time of a P channel transistor and an N channel transistor.

  FIG. 1 is a block diagram of a voltage generation circuit 100 according to an embodiment of the present invention, and FIG. 2 is a timing chart thereof. The voltage generation circuit 100 is a power supply circuit (DC-DC converter) that generates an output voltage VOUT corresponding to an input voltage VIN generated by a DC power supply and supplies the output voltage VOUT to the output terminal 14. A driving load (not shown) is connected to the output terminal 14. As shown in FIG. 1, the voltage generation circuit 100 includes a P-channel transistor TR1, an N-channel transistor TR2, a choke coil L, and a smoothing capacitor C.

  Transistors TR1 and TR2 are connected in series between the power supplies. Specifically, the drain of the transistor TR1 and the drain of the transistor TR2 are connected to each other at the output node N, the input voltage VIN is supplied to the source of the transistor TR1, and the source of the transistor TR2 is grounded. The choke coil L is interposed between the connection point N of the transistors TR1 and TR2 and the output terminal 14 (drive load). The smoothing capacitor C is connected to the output terminal 14 and smoothes the output voltage VOUT.

  The error signal generation circuit 30 generates an error signal Err corresponding to the output voltage VOUT generated at the output terminal 14. As shown in FIG. 1, the error signal generation circuit 30 includes a resistance element 322, a resistance element 324, a voltage source 34, and an amplifier (error amplifier) 36. The resistance element 322 and the resistance element 324 generate a feedback voltage V1 by dividing the output voltage VOUT fed back from the output terminal 14. The voltage source 34 is a DC power source that generates a predetermined comparison voltage V2. The feedback voltage V1 is supplied to the non-inverting input terminal of the amplifier 36, and the comparison voltage V2 is supplied to the inverting input terminal of the amplifier 36. The amplifier 36 amplifies the difference voltage between the feedback voltage V1 and the comparison voltage V2, and generates an error signal Err. Specifically, the error signal Err increases as the output voltage VOUT is higher than the comparison voltage V2, and the error signal Err decreases as the output voltage VOUT is lower than the comparison voltage V2.

  The triangular wave signal generation circuit 40 in FIG. 1 generates a triangular wave signal Vramp whose level changes with the period of the reset signal RES (see FIG. 2). The triangular wave signal generation circuit 40 includes a current source 42, a transistor 44, and a capacitive element 46. The voltage across the capacitive element 46 is supplied to the comparison circuit 50 as a triangular wave signal Vramp. The current source 42 is a constant current source that generates a predetermined current and supplies it to the capacitive element 46. The transistor 44 is a switch interposed between both ends of the capacitive element 46. During the period in which the transistor 44 is off, the capacitor 46 is charged with a constant current, so that the potential of the node 45 rises linearly. On the other hand, a pulsed reset signal RES is supplied to the gate of the transistor 44. During the active period of the reset signal RES, the transistor 44 is turned on, and the charge charged in the capacitor 46 is discharged. Thereby, a triangular wave signal Vramp is obtained.

  The comparison circuit 50 in FIG. 1 is composed of an operational amplifier including an inverting input terminal and a non-inverting input terminal. The error signal Err generated by the error signal generation circuit 30 is supplied to the non-inverting input terminal of the comparison circuit 50, and the triangular wave signal Vramp is supplied to the inverting input terminal of the comparison circuit 50. The comparison circuit 50 compares the error signal Err and the triangular wave signal Vramp to generate a control signal CTL corresponding to the comparison result. Specifically, as shown in FIG. 2, when the error signal Err exceeds the triangular wave signal Vramp, the control signal CTL is set to a high level, and when the error signal Err falls below the triangular wave signal Vramp, the control signal CTL is Set to low level.

  As described above, since the level of the error signal Err decreases as the load is lighter, the pulse width WX of each control pulse PX increases as the load increases (the pulse width WX decreases as the load decreases). As can be understood from the above description, the comparison circuit 50 functions as a pulse width modulation circuit that generates the control signal CTL in which the pulse PX having the pulse width WX corresponding to the error signal Err (output voltage VOUT) is arranged.

  The reset signal generation circuit 60 in FIG. 1 generates a reset signal RES having a constant period when the active period (high level) of the control signal CTL is shorter than a predetermined reference time Tref, and the active period of the control signal CTL. Is longer than the reference time Tref, the reset signal RES having a shorter period is generated as the difference between the reference time Tref and the active period becomes longer.

  The reset signal generation circuit 60 includes a first current source 61 that outputs a first current i1, a second current source 62 that outputs a second current i2, transistors 63 and 64, and a capacitive element 65. When the differential time signal Z is inactive (high level), the transistor 64 is off, and the capacitive element 65 is charged by the first current i1, but when the differential time signal Z is active (low level), the transistor 64 is turned on, and the capacitive element 65 is charged by the first current i1 and the second current i2.

  The non-inverting input terminal of the comparator 68 is connected to the node 66, while the comparison voltage V 3 is supplied from the voltage source 67 to the inverting input terminal. The output signal of the comparator 68 becomes high level when the voltage at the node 66 exceeds the comparison voltage V3. The waveform shaping circuit 69 generates a reset signal RES that becomes high level for a predetermined period in synchronization with the rising edge of the output signal of the comparator 68. The reset signal RES is supplied to the gate of the transistor 63. When the reset signal RES becomes high level, the transistor 63 is turned on, and the charge accumulated in the capacitor 65 is discharged. That is, the period of the reset signal RES is a time from when the voltage of the node 66 is grounded due to the discharge of the capacitive element 65 until the voltage V3 of the voltage source 67 is reached. The current flowing into the capacitor 65 is larger when the transistor 64 is turned on. Therefore, the longer the active period of the differential time signal Z, the shorter the cycle of the reset signal RES. Since the reset signal RES is fed back to the gate of the transistor 63, the reset signal generation circuit 60 functions as an oscillation circuit. In the present embodiment, the first current i1 and the second current i2 are assumed to have the same magnitude. The reset signal RES is supplied to the triangular wave signal generation circuit 40 and the differential time signal generation circuit 70. The triangular wave signal generation circuit 40 and the differential time signal generation circuit 70 operate in synchronization with the reset signal RES. For this reason, as shown in FIG. 2, the triangular wave signal Vramp, the control signal CTL, and the MaxPon signal 71a are synchronized with the reset signal RES. Therefore, the reset signal generation circuit 60 functions as a frequency control unit that controls the frequency of the control signal CTL.

  The differential time signal generation circuit 70 includes a pulse generation circuit 71 that generates a MaxPon signal 71a that is high for the reference time Tref after the reset signal RES becomes active, an inverter 72, and a NAND circuit 73. The high level period of the MaxPon signal 71a indicates the maximum time during which the P-channel transistor TR1 is turned on. That is, the P-channel transistor TR1 is not turned on beyond the reference time Tref.

  Further, the MaxPon signal 71a is inverted by the inverter 72, and the NAND circuit 73 calculates the inverted logical product of the inverted MaxPon signal 71a and the control signal CTL. As a result, the differential time signal Z becomes active (low level) when the high level period of the control signal CTL becomes longer than the reference time Tref as shown in FIG. As described above, since the transistor 64 is turned on when the differential time signal Z becomes active, as shown in FIG. 2, the slope of the voltage Y at the node 66 becomes steep during the period Tx during which the differential time signal Z is active.

  The drive unit 80 of FIG. 1 includes a NAND circuit 81 (first drive unit) that supplies a drive signal DR1 obtained by calculating the inversion of the logical product of the control signal CTL and the MaxPon signal 71a to the P-channel transistor TR1. The transistor TR1 is turned on while the drive signal DR1 is at a low level. The MaxPon signal 71a defines the maximum time for which the transistor TR1 is turned on. The drive unit 80 includes a comparator 82, an AND circuit 83, and an SR flip-flop 84. These configurations function as a second drive unit that generates a drive signal DR2 for controlling on / off of the N-channel transistor TR2.

The output signal of the SR flip-flop 84 becomes the drive signal DR2. The drive signal DR1 is supplied to the set terminal of the SR flip-flop 84. Accordingly, when the drive signal DR1 changes from low level to high level and the transistor TR1 changes from on to off, the drive signal DR2 changes from low level to high level.
The timing at which the drive signal DR2 transitions from the high level to the low level is determined by the output signal 83a of the AND circuit 83 supplied to the set terminal. The AND circuit 83 calculates a logical product of the signal 72a obtained by inverting the MaxPon signal 71a and the output signal 82a of the comparator 82, and outputs a signal 83a.
The voltage of the node N (the drain of the transistor TR2) is supplied to the inverting input terminal of the comparator 82, while the voltage of the source of the transistor TR2 is supplied to the non-inverting input terminal. Therefore, when the voltage at the source of the transistor TR2 (ground voltage) is higher than the voltage at the drain of the transistor TR2, the output signal 82a of the comparator 82 becomes high level.

  The time when the P-channel transistor TR1 is turned on is the time when the drive signal DR1 becomes active (low level), and becomes longer as the load becomes heavier, and becomes constant when the reference time Tref is reached. On the other hand, the time when the N-channel transistor TR2 is turned on is the time when the drive signal DR2 is active (high level). Since the drive signal DR1 is supplied to the set terminal of the SR flip-flop, the N-channel transistor TR2 is turned on when the P-channel transistor TR1 is switched from on to off.

Next, the timing at which the N-channel transistor TR2 switches from on to off is defined by the signal 83a supplied to the reset terminal. The AND circuit 83 that generates the output signal 83a functions as a mask unit that masks the output signal 82a of the comparator 82 using a signal 72a obtained by inverting the MaxPon signal 71a. That is, the rising edge of the output signal 83a generated between the time when the drive signal DR1 becomes active and the time when the reference time Tref elapses is masked by the signal 72a. As a result, the timing at which the N-channel transistor TR2 switches from on to off is the time when the reference time Tref elapses after the drive signal DR1 becomes active. On the other hand, when the rising edge of the output signal 82a of the comparator 82 occurs after the reference time Tref elapses after the drive signal DR1 becomes active, the N-channel transistor TR2 is switched from on to off at that time.
In this way, by controlling the timing at which the N-channel transistor TR2 is switched from on to off, it is possible to control the operation time of the P-channel transistor TR1 and the N-channel transistor TR2 not to be shorter than the reference time Tref.

In the above configuration, the frequency of the reset signal RES changes as shown in FIG. Among these, the PFM control is executed in the first region X1 corresponding to the light load and the second region X2 corresponding to the medium load, and the PWM control operating at the upper limit frequency fmax is executed in the third region X3 corresponding to the heavy load. .
First, in the first region X1 corresponding to a light load, the magnitude of the load is less than R1. This is a case where the active period of the control signal CTL is shorter than the reference time Tr. In this case, since the differential time signal Z becomes inactive, the transistor 64 is turned off. Therefore, the second current i2 does not flow into the node 66. Therefore, since the frequency of the reset signal RES is determined only by the first current i1, this frequency becomes a constant lower limit frequency fmin.

By the way, the voltage generation circuit 100 of this embodiment is used as a power source of a circuit that processes an audible band signal. The signal output from the node N is integrated by the coil L and the smoothing capacitor C to become the output voltage VOUT, but the voltage change at the node N cannot be completely removed.
When the ripple component superimposed on the output voltage VOUT enters the audible band, the power supply ripple becomes signal noise in the subsequent circuit. Therefore, in this embodiment, the lower limit frequency fmin is set to a frequency higher than the audible band.

FIG. 4 shows the voltage VN at the node N in the first region X1. In the first region X1, during the active period of the control signal CTL, the drive signal DR1 becomes active and the P-channel transistor TR1 is turned on. During the ON period of the P-channel transistor TR1, the output current IL is discharged from the node N, and the voltage VN increases.
Next, the drive signal DR2 becomes active from the start of the inactive period of the control signal CTL to the end of the active period of the MaxPon signal 71a, and the N channel transistor TR2 is turned on. During the ON period of the N-channel transistor TR2, the output current IL is sucked into the node N, and the voltage VN decreases.

  In the first region X1, the ON period of the N-channel transistor TR2 continues even when the voltage VN becomes a negative value. The substantial power supplied to the load is obtained by subtracting the area S2 of the negative voltage VN from the area S1 of the positive voltage VN. That is, the portion of the negative voltage VN becomes invalid power that is not supplied to the load. However, even when the load becomes light, the lower limit frequency fmin in the PFM control can be defined by operating the P-channel transistor TR1 and the N-channel transistor TR2.

  Next, with reference to FIG. 5, the relationship between the voltage VN of the node N in the first region X1 and the on-time of the P-channel transistor and the N-channel transistor will be described. FIG. 6A shows the case where the error signal Err is zero. In this case, the area S1 and the area S2 are equal. As a result, power is not supplied to the load, and power corresponding to the area S2 is wasted. If the load is slightly increased from this state, S1−S2> 0 as shown in FIG. In this case, power corresponding to the difference between the area S1 and the area S2 is supplied to the load. Further, when the load increases, S2 = 0 as shown in FIG. In this case, the voltage VN at the node N is not negative, and power is not wasted.

  As described above, in this embodiment, power is consumed even when power is not consumed by the load, but invalid power decreases as the load becomes heavier. In a DC-DC converter using conventional PFM control, when setting a lower limit frequency, it is conceivable to provide a bleeder resistor in parallel with the load. This is to prevent the operating frequency from falling below the lower limit frequency by constantly consuming electric power with the bleeder resistor. In this case, electric power is always consumed by the bleeder resistance even when the load becomes heavy. On the other hand, in the present embodiment, when the load becomes heavy, the invalid power decreases, so that the efficiency can be improved.

DESCRIPTION OF SYMBOLS 100 ... Voltage generation circuit, 14 ... Output terminal, TR1, TR2 ... Transistor, L ... Choke coil, C ... Smoothing capacitor, 30 ... Error signal generation circuit, 40 ... Triangular wave signal generation circuit, 50 ... ... Comparison circuit 60 ... Reset signal generation circuit Z ... Differential time signal 61 ... First current source 62 ... Second current source 65 ... Capacitance element 70 ... Differential time signal generation circuit 71... Pulse generation circuit, 80... Drive unit, 82... Comparator, 81... NAND circuit, 82... Comparator, 83 ... AND circuit, 84 ... SR flip-flop, DR1, DR2. Err ... error signal, RES ... reset signal, Vramp ... triangular wave signal, CTL ... control signal, 71a ... MaxPon signal.

Claims (5)

A P-channel transistor, an output node and an N-channel transistor connected in series between a high potential power source and a low potential power source;
An error signal generation unit that generates an error signal that is a difference between a detection voltage corresponding to the voltage of the output node and a reference voltage;
A control signal generation unit that generates a control signal that is active only during a period according to the magnitude of the error signal;
When the active period of the control signal is longer than a reference time, the P-channel transistor is turned on in a first period from the start of the active period until the reference time elapses, and the active period of the control signal is the reference period A first driver that turns on the P-channel transistor during the active period if the time is shorter than the time;
A second driver for controlling the N-channel transistor on or off;
When the frequency of the control signal is controlled in a range from a lower limit frequency to an upper limit frequency, and the active period of the control signal is shorter than the reference time, the frequency of the control signal is set as the lower limit frequency, and the active period of the control signal Is longer than the reference time, a frequency control unit that controls the frequency of the control signal to be higher as the time of the difference between the active period and the reference time is longer,
A voltage generation circuit comprising:   The voltage generation circuit according to claim 1, wherein the lower limit frequency is a frequency higher than an audible band. The second driving unit includes:
When the P-channel transistor switches from on to off, the N-channel transistor is turned on,
If the potential of the output node falls below the low-potential power supply before the reference time when the reference time elapses after the P-channel transistor is turned on, the N-channel transistor is turned off at the reference time. ,
If the potential of the output node falls below the low potential power source after the reference time, the N-channel transistor is turned off when the potential of the output node falls below the low potential power source.
The voltage generation circuit according to claim 1, wherein: The frequency control unit
A capacitive element;
A comparator for comparing the voltage of the capacitive element with a predetermined voltage;
A supply unit for supplying current to the capacitive element;
A discharge unit for discharging the charge charged in the capacitive element,
The supply unit
When an active period of the control signal is shorter than the reference time, a predetermined value of current is supplied to the capacitive element,
When the active period of the control signal is longer than the reference time, the difference time between the active period and the reference time supplies a current larger than the predetermined value to the capacitor, and the other time is the predetermined time. A current of a value to the capacitive element,
Generate a reset signal for controlling the discharge unit based on the output signal of the comparison unit, supply the reset signal to the control signal generation unit,
The control signal generation unit generates the control signal in synchronization with the reset signal;
The voltage generation circuit according to claim 1, wherein the voltage generation circuit is a voltage generation circuit. A reference signal generation unit that generates a reference signal obtained by inverting a signal that becomes active during a period from the start of the active period of the control signal to the passage of the reference time;
The second driving unit includes:
A detection signal generating unit that generates a detection signal by detecting a period in which the potential of the output node is lower than the potential of the low-potential power source;
A logic circuit that calculates a logical product of the detection signal and the reference signal;
An SR flip-flop that supplies a signal for controlling on / off of the P-channel transistor to a set terminal, an output signal of the logic circuit to a reset terminal, and supplies an output signal to the gate of the N-channel transistor; ,
The voltage generation circuit according to claim 1, wherein the voltage generation circuit is any one of claims 1 to 4.

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