JP5683525B2 - Power semiconductor module design method - Google Patents

Description

  The present invention relates to a design method for a power semiconductor module, and in particular, a design method capable of suppressing oscillation at turn-off in a bipolar power semiconductor module used in a power converter for driving an electric device such as a motor. About.

  A power semiconductor module using a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) has been increased in capacity. As the capacity increases, a plurality of power semiconductor chips (power semiconductor elements) are connected in parallel inside the power semiconductor module. For this reason, there are a plurality of resonance circuits formed in the package of the power semiconductor module by the inductance due to the connection for connecting the power semiconductor chip and the capacitance component inside the power semiconductor chip.

  In addition, since power semiconductor chips of various withstand voltage classes (for example, 600 V to 6500 V) are used for the power semiconductor module, the size of the capacity component of the power semiconductor chip may be different for each power semiconductor module. For this reason, the resonance circuit in the power semiconductor module and its resonance frequency are more complicated. It has been confirmed that oscillation occurs when the resonance frequency matches the characteristics of a bipolar power semiconductor element such as an IGBT chip. For this reason, it is difficult to increase the capacity of the power semiconductor module or to reduce noise.

  This oscillation is often observed during the IGBT turn-off period. The oscillation phenomenon is more important with respect to EMC (Electro-Magnetic Compatibility), and it is necessary to avoid this oscillation because it adversely affects EMC on other electronic devices. Moreover, there is a possibility that the IGBT malfunctions by superimposing an electromagnetic wave due to oscillation on the gate signal of the IGBT T itself.

  In order to avoid oscillation, it is necessary to specify a resonance circuit. However, in a power semiconductor module having a complicated three-dimensional structure, it is difficult to estimate and specify a resonance circuit. For this reason, conventionally, a power semiconductor module was actually made on a trial basis, and the presence or absence of oscillation was evaluated, and the evaluation result was fed back to the design to depend on a method for avoiding oscillation. For this reason, it has been difficult to improve design efficiency and reduce costs.

  Even if the resonance circuit can be specified, a method for suppressing the oscillation and reducing the influence is separately required. As a method for this, a method has been proposed in which a resistance element or a high-frequency loss element is inserted in the gate wiring to reduce noise superimposed on the gate signal. For example, Japanese Patent Laid-Open No. 4-65866 (Patent Document 1) discloses a technique using a resistance element. Japanese Patent Laying-Open No. 2001-185679 (Patent Document 2) discloses a technique using a ferrite core as a high-frequency loss element.

JP-A-4-65866 JP 2001-185679 A

  As described above, in order to reduce the influence of the oscillation of the power semiconductor module on the gate signal, evaluation by trial manufacture is necessary, and thus there is a problem that design efficiency is poor. The method of inserting a resistance element or a high-frequency loss element in the gate wiring brings about an increase in the number of parts and an increase in the loss of the power semiconductor module, so that it is difficult to reduce the cost, the loss and the size. In addition, it is difficult to calculate the oscillation frequency with the conventional method, and it is difficult to reliably avoid oscillation.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a power semiconductor module design method capable of avoiding oscillation and miniaturizing.

In summary, the present invention provides a method for designing a power semiconductor module including a bipolar power semiconductor element, wherein the bipolar power semiconductor element is integrated by integrating the reciprocal of the hole velocity over the thickness of a depletion layer generated in the bipolar power semiconductor element. A step of calculating a hole propagation time in a power semiconductor device, a step of creating an equivalent circuit of the power semiconductor module, a step of calculating a resonance frequency of the equivalent circuit, and the resonance frequency is an inverse of the hole propagation time. And a step of determining whether or not the frequency is within a predetermined range including a frequency represented by : wherein the predetermined range is in a range of 90% to 110% of a frequency represented by a reciprocal of the hall propagation time. Oh Ru.

  According to the present invention, the oscillation phenomenon of the bipolar power semiconductor element mounted on the power semiconductor module can be avoided, so that the noise of the semiconductor module can be reduced. In addition, according to the present invention, since the oscillation phenomenon can be avoided without increasing the number of parts, the semiconductor module can be downsized.

It is a schematic side view of a power semiconductor module. It is a schematic top view in a part of the power semiconductor module shown in FIG. It is a figure explaining the phenomenon which arises at the time of turn-off of an IGBT element. FIG. 6 shows a simplified model for simulation. It is a figure which shows the result of having analyzed the time change of the voltage between collector-emitters of an IGBT element by the simulator on the conditions which an IGBT element oscillates. It is the figure which expanded the time change of the oscillation voltage between the collector-emitters of the IGBT element shown in FIG. It is the figure which showed the electric field strength in a depletion layer. It is the figure which showed the hole velocity in a depletion layer. It is the figure which showed the time change of the hole density in the depletion layer obtained by simulation. It is the figure which showed the time change of the hole current density in the depletion layer obtained by simulation. It is the figure which showed the phase relationship of the electric current and voltage at the time of an oscillation. It is the figure which specified the peak position of the Hall current density in each time shown in FIG. It is the figure which showed the propagation velocity (black spot) and hole velocity (solid line) of the peak of the hole current density in a depletion layer. It is a figure which shows the structural example of the computer which performs the design method of the power semiconductor module according to embodiment of this invention. It is a flowchart explaining the design method of the power semiconductor module of embodiment of this invention.

<Embodiment>
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

  First, the configuration of the power semiconductor module will be described with reference to the drawings. In order to clearly show the effects of the embodiment of the present invention, a power semiconductor module having a configuration in which a high-frequency loss element is inserted will be described below.

  FIG. 1 is a schematic side view of a power semiconductor module. FIG. 2 is a schematic top view of a part of the power semiconductor module shown in FIG.

  Referring to FIGS. 1 and 2, power semiconductor module 100 is used for a power conversion device (an inverter or the like) that drives an electric device such as a motor. The power semiconductor module 100 includes a base plate 1, an insulating metallized substrate 2, an IGBT chip (IGBT element) 3A, a freewheeling diode chip (freewheeling diode element) 3B, aluminum wires 4 and 12, and main electrode terminals 5A and 5B. With.

  A material such as Cu, AlSiC, or Cu—Mo is used for the base plate 1. The surface of the base plate 1 is plated with Ni, and a resist is applied to the surface side (side on which the insulating metallized substrate 2 is mounted). The insulating metallized substrate 2 is made of a ceramic substrate and Al (or Cu) patterns mounted on both sides thereof. The number of insulating metallized substrates 2 is determined according to the scale of the module, for example, a plurality of sheets are prepared.

  The collector electrode on the back surface of the IGBT chip 3A is soldered on the insulating metallized substrate 2, and the cathode electrode on the back surface of the reflux diode chip 3B is soldered on the insulating metallized substrate 2. The insulating metallized substrate 2 is bonded to the base plate 1. The aluminum wire 4 connects the emitter electrode of the IGBT chip 3A and the anode electrode of the reflux diode chip 3B. The aluminum wire 12 is a gate wire connected to the gate electrode of the IGBT chip 3A. The main electrode terminals 5A and 5B are terminals through which a main current flows with an external circuit. The main electrode terminal 5A is electrically connected to the collector electrode of the IGBT chip 3A, and the main electrode terminal 5B is electrically connected to the emitter electrode of the IGBT chip 3A. Connected to. The main electrode terminals 5A and 5B are made of a Cu thin plate having Ni plating on the surface thereof, and are joined to a pattern on the insulating metallized substrate 2.

  The power semiconductor module 100 further includes a control circuit board 6, a case 7, a connection pin 8, a gate balance resistor 10, and a high frequency loss element 11. The control circuit board 6 is composed of a multilayer printed board, and a gate wiring pattern connected to the gate electrode of the IGBT chip 3A is formed in order to control the gate voltage of the IGBT chip 3A. The wiring is configured to be bonded to a pattern on the insulating metallized substrate 2 via connection pins (terminals) 8. The case 7 (not shown in FIG. 2) is attached to the base plate 1 with screws and silicone rubber.

  In the inverter on which the power semiconductor module 100 is mounted, the power semiconductor module 100 operates in accordance with a signal from the control circuit. Therefore, the power semiconductor module 100 is required to operate normally without malfunction according to the command of the signal. However, if oscillation occurs between the collector and the emitter when the IGBT chip 3A is turned off, the electromagnetic wave may affect the gate signal. In order to prevent this problem, as shown in FIG. 2, for example, a gate balance resistor 10 or a high-frequency loss element 11 is inserted into each gate wiring of a plurality of IGBT chips connected in parallel, and noise superimposed on the gate signal is reduced. A method of reducing may be used. The high frequency loss element 11 is constituted by a ferrite core, for example.

  However, the insertion of a gate balance resistor or the like causes a decrease in switching speed, resulting in an increase in switching loss. Also, with the conventional technology, it is difficult to predict the occurrence of oscillation before the power semiconductor module is prototyped.

  The inventor has confirmed that the high-frequency potential oscillation occurs in the main circuit collector-emitter wiring. As disclosed in Japanese Patent Laid-Open No. 2001-185679, in the module type semiconductor device, the collector side of the IGBT element is soldered to the pattern on the insulating substrate, and the emitter is wired by wire bonding. It is extremely difficult to insert a high-frequency loss element between the emitter wirings.

  Here, regarding the generation mechanism of the high-frequency potential oscillation generated when the power semiconductor module is turned off, “Plasma extraction transit time oscillations in bipolar power devices” (Bernd Gutsmann et al., Solid-State Electronics 46 (2002) p.133). -138) and "Investigation on IGBT High-Frequency Plasma Extraction Transient Time Oscillation" (Shigeto Fujita and three others, IEEE Transaction on Power Electronics, Vol. 24, No. 6 (2009) p.1570-1576) ing. Hereinafter, the outline will be described with reference to FIG. 3 using an IGBT as an example of a bipolar semiconductor.

  As shown in FIG. 3, when the IGBT chip 3A is turned off, a depletion layer (space charge layer) 21 having a thickness (W) depending on the voltage applied to the collector is formed in the n − layer 20.

  When the gate signal of the IGBT is turned on and a current flows from the collector to the emitter, holes (holes) are injected from the p + layer 24 into the n− layer 20. When the gate signal is turned off, holes are not injected from the p + layer 24 into the n− layer 20, but holes remain in the n− layer 20. Of the non-depleted region in the n − layer 20, the portion adjacent to the depletion layer 21 where holes remain is also referred to as a residual plasma layer. Due to the collector-emitter voltage, the holes 25 remaining in the n − layer 20 move to the emitter terminal. This phenomenon is that the collector current flows even after the depletion layer is formed in accordance with the rise in the collector-emitter voltage. This current is the tail current of the IGBT element.

  In a tail period in which a tail current is generated, in addition to holes contributing to the tail current, a bundle of holes 25 (also referred to as hole packets) from the residual plasma layer travels in the depletion layer 21 by an electric field. 3A operates as a negative resistance. The negative resistance is generated when a DC voltage in which a high frequency voltage having a specific frequency is superimposed on a bipolar semiconductor is applied. Gutsmann et al. Consider that the mechanism of negative resistance generation in an IGBT is the same as that of a Baritt diode (Barrier Injection Transit Time diode) oscillation, and consider the hole drift speed as a constant speed, and then the hole travel time ( It is calculated by adding the thickness (W) of the depletion layer divided by the hole drift velocity) and taking the reciprocal. When the calculated frequency matches the resonance frequency of the resonance circuit formed by the wiring in the power semiconductor module, the power semiconductor module operates as a negative resistance oscillator. In this model, the presence of the injection delay time is essential for the generation of negative resistance or gain.

  Siemieniec et al. "The Plasma Extraction Transit-Time Oscillation in Bipolar Power Devices-Mechanism, EMC Effects, and Prevention" (Ralf Siemieniec and three others, IEEE Transactions on Electron Devices, Vol. 53, No. 2, p. 369), it is assumed that the generation mechanism of the turn-off oscillation is the same as that of the BARITT diode oscillation, and the bundle of holes propagates at the same speed and at the same saturation speed as in the case of the BARITT diode oscillation. According to Siemieniec et al., Turn-off oscillation occurs when the natural frequency f of the resonant circuit and the time for which the bundle of holes propagates through the depletion layer is in the relationship of equation (1).

_{f = 3v s / 4W ... (} 1)

Here, W is the length of the depletion layer, and v _s is the saturation rate of holes.
In this model, a hole at one end of the depletion layer at the time of the peak of the voltage oscillation waveform (phase [pi / 2) is injected, propagated at a constant velocity v _s depletion layer between the 3/4 cycle phase It is assumed that the other end of the depletion layer is reached when is 2π. The injection delay time is assumed to be W / 3v _s corresponding to the time between phase 0 and phase π / 2.

  The inventor conducted an experiment and simulation of turn-off oscillation using a real-scale simulated high-voltage IGBT (HIGBT) module with regard to bipolar power semiconductor, especially IGBT turn-off oscillation, and suppose that a bundle of holes propagates at a saturation speed. The frequency of turn-off oscillation was found to be significantly different from the experimental results. Therefore, the inventor conducted a device simulation of turn-off oscillation generated in the simulated HIGBT module and examined the state of negative resistance generation. The origin of oscillation was negative resistance, and negative resistance was generated by the propagation of holes. Although the point is in common with PETT (Plasma Extraction Transit-Time) oscillation or BARTIT diode, it has been found that the propagation of holes is not uniform at the same speed. The state of propagation of the bundle of holes and the voltage waveform induced in the external circuit by the bundle of holes causing the negative resistance are not rectangular as in the PETT oscillation or the BARITT diode. It has been found that it is different from an oscillation or BARITT diode. The inventor has also found that the hole injection delay time is not related to the oscillation frequency, and has proposed a simple calculation method of the oscillation frequency when the IGBT chip oscillates. This calculation method will be described below.

FIG. 4 is a simulation model in which the semiconductor power module shown in FIGS. 1 and 2 is simplified, and shows both an equivalent circuit and an outline of a chip cross-sectional structure. The simulation is based on a cross-sectional structure of the IGBT chip and the free wheel diode chip, and a device simulator that simulates their operation, and an equivalent circuit based on the three-dimensional structure of the semiconductor power module (including the capacitance of the IGBT chip and free wheel diode chip). Circuit simulators simulating the time change in were linked to each other. FIG. 3 corresponds to the BB ′ cross section of FIG. FIG. 2 shows a power semiconductor module on which six IGBT chips 3A and six free wheel diode chips 3B are mounted. In this simulation model, three IGBT chips 3A on one insulating metallized substrate 2 are shown. The three free-wheeling diode chips 3B are combined into one to form two IGBT chips and two free-wheeling diode chips. The capacitance of the entire IGBT chip is determined by the collector-emitter capacitance C _CE , the gate-collector capacitance C _GC , and the gate-emitter capacitance C _GE . In the simulation model, the bottom areas of the actual IGBT chip and the reflux diode chip are tripled, and the respective capacitances are matched with the IGBT modules used in the experiment. The inductance L _bus (= L _bus / 2 + L _bus / 2) shown in FIG. is there. Inductance L _ext is an external inductance and was calculated from the experimental results. The capacitance of the IGBT chip and the diode and the inductance L _bus constitute a parallel resonance circuit. The natural frequency of this resonant circuit is 80 MHz. The simulation model does not include the gate balance resistor 10 and the high-frequency loss element 11.

FIG. 5 is a diagram showing a result of analyzing the collector-emitter voltage of the IGBT element by a simulator under the condition that the IGBT element oscillates in FIG. In the simulation of turn-off oscillation, it is necessary to calculate the propagation of holes inside the IGBT chip, which is the origin of oscillation generation. In addition, since turn-off oscillation is a high-frequency phenomenon, device simulation requires calculation with high time resolution and high space resolution, and takes a long time. For the device simulator, Medici (software from Synopsys) was used. The collector voltage was 1500V. From Figure 5, after the turn-off of IGBT elements, the collector - it can be seen that the oscillation in the emitter voltage V _CE is superimposed. The oscillation frequency is 80 MHz which is the same as the resonance frequency. Note that the turn-off oscillation observed in an actual device is 75.6 MHz, which is almost the same.

  FIG. 6 is an enlarged view of the vibration waveform in FIG. In FIG. 6, time 12.690 μs corresponds to approximately phase 0, and time 12.972 μs corresponds to approximately phase 2π.

FIG. 7 shows the electric field strength in the depletion layer of the IGBT chip at the peak of the oscillation waveform of FIG. 6 (phase π / 2). It can be seen that the electric field strength in the depletion layer is lower than the electric field strength of 105 V / cm at which holes in Si reach the saturation speed. The depth of the horizontal axis in FIG. 7 corresponds to the position x in the depletion layer shown in FIG. 3, and the boundary between the emitter-side p layer (p base layer) and the n − layer 20 is set to the origin 0, and toward the collector. (This also applies to FIGS. 8, 9, 10, 12, and 13 and the related description below.)
In FIG. 8, the relationship between the position in the depletion layer and the hole velocity obtained by device simulation based on the electric field strength shown in FIG. 7 is shown by a solid line. The higher the electric field strength, the higher the hole velocity. However, the higher the velocity, the larger the effective mass, and these are not proportional. Further, it can be seen from FIG. 8 that the hole does not reach the saturation speed (approximately 100 km / s).

  FIG. 9 shows a simulation result of the time change of the hole density in the depletion layer corresponding to the period shown in FIG. As shown in FIG. 9, in the simulation, it is observed that a bundle of holes propagates through the depletion layer. Each time in FIG. 9 corresponds to each time shown in FIG. From comparison between FIG. 6 and FIG. 9, it can be seen that this propagation occurs in the same period as the period of the vibration waveform. However, as shown in FIG. 9, since the diffusion of the bundle of holes is large, it is difficult to accurately grasp the state of propagation. That is, from the time variation of the hole density, it is not clear at what moment a bundle of holes is injected into the depletion layer, propagates through the depletion layer, and when it leaves the depletion layer. Therefore, it is not easy to obtain the relationship between the hall propagation time and the turn-off oscillation frequency, and the oscillation frequency cannot be predicted. Oscillation occurs when the frequency of the resonant circuit matches the oscillation frequency determined by the bipolar semiconductor element, but there is no means for easily estimating the oscillation frequency determined by the bipolar semiconductor element, so whether these frequencies match. Could not be determined. Therefore, whether or not the power module generates turn-off oscillation can be determined by performing a simulation over a long period of time to check for the presence of high-frequency vibration, or by actually performing a turn-off experiment to check for the occurrence of oscillation. There was no way.

  FIG. 10 shows the time variation of the hole current density obtained from the simulation (each time in FIG. 10 corresponds to the time in FIG. 6). FIG. 11 shows the Hall current density shown in FIG. 10 in the Ramo-Schottky equation (see WT Read “A Proposed High-Frequency, Negative-Resistance Diode”, BSTJ, vol. 37, p. 401, 1958). It is the calculation result of the time change of the current density induced | guided | derived to the external circuit by propagation of a hole obtained by applying. In FIG. 11, the time change of the current density induced in the external circuit is compared with the oscillation voltage waveform shown in FIG. From FIG. 11, it can be seen that the IGBT is a negative resistance because the current waveform is almost in phase with the voltage waveform.

From the time change in the hole current density shown in FIG. 10, it can be seen that the peak of the hole current density behaves so as to propagate through the depletion layer from the collector side to the emitter side. FIG. 12 shows how the peak of the hole current density propagates. The data in FIG. 12 is the same as that in FIG. 10, but it is easy to understand how the peak of the hole current density propagates by marking the peak of the hole current density at each time. Figures 6 and 12, the peak of the hole current density, the phase of V _CE is appearing about substantially the collector of the depletion layer at 0, it can be seen that reaching the emitter side of the depletion layer in the 2 [pi. That is, the time the peak of the hole current density propagate depletion is consistent with the time of one cycle of the vibration waveform of V _CE is turned off oscillation.

  FIG. 13 shows the propagation speed of the peak of the hole current density at the position x in the depletion layer as a black dot. The propagation speed of the peak of the hole current density can be obtained by dividing the distance traveled by the peak of the hole current density between the times shown in FIG. 12 by the corresponding time. In FIG. 13, in order to obtain the relationship between the position in the depletion layer and the propagation speed of the hole current density, plotting is performed using the result of the time interval finer than the hole current density distribution shown in FIGS. In FIG. 13, the relationship between the position in the depletion layer shown in FIG. 7 and the hole velocity is shown by a solid line. As shown in FIG. 13, it was found that the propagation speed (black dot) of the peak of the hole current density and the hole speed (solid line) are substantially equal.

In the above, the time the peak of the hole current density propagates depletion has been described to be consistent with the time of one cycle of the vibration waveform of V _CE is turned off oscillation. Further, as shown in FIG. 13, it was found that the propagation speed of the peak of the hole current density coincided with the hole speed. Therefore, the propagation time T _p can be obtained as shown in Equation (2) using the hole velocity v _h (x).

Here, _fr is the natural frequency of the resonant circuit, and L and C are the inductance and capacitance of the resonant circuit, respectively. Further, v _h (x) is the hole velocity at the position x in the depletion layer, and W is the length (thickness) of the depletion layer. The integration range corresponds to the range where the depletion layer occurs. The rightmost integral represents the time taken for the hole to propagate through the depletion layer. Hereinafter, the frequency (1 / T _p ) represented by the reciprocal of the propagation time T _p is also referred to as the oscillation center frequency. This frequency is a frequency determined by the IGBT element depending on conditions such as the structure of the IGBT element and the applied voltage.
In order to obtain the relationship between the position in the depletion layer and the hole velocity, the time resolution and spatial resolution may be coarser than in the case of simulating the oscillation phenomenon with time resolution sufficiently finer than the oscillation period. It can be obtained in a short time. Therefore, if the propagation speed of the Hall current density is substituted with the Hall speed, it can be easily determined in a short time whether or not the oscillation condition is satisfied.

Using the relationship between the position in the depletion layer and the hole velocity obtained from the simulation shown in FIG. 13, the time (1) corresponding to one wavelength of the natural vibration of the resonance circuit in the power module and the time for the hole to propagate through the depletion layer. / F _r ) is not the same, that is, by using a semiconductor power module that does not hold the expression (2), a semiconductor power module that does not generate turn-off oscillation can be easily obtained. That is, if the semiconductor power module has values of L and C that do not hold Expression (2), turn-off oscillation does not occur.

A semiconductor power module that does not oscillate at the time of turn-off can be obtained by adjusting the wiring length to obtain a semiconductor power module having values of L and C that do not satisfy the above formula (2).
In the turn-off oscillation, a sine wave voltage applied to the IGBT chip is amplified by a negative resistance. The sinusoidal voltage is generated when a parasitic resonance circuit in the IGBT module is excited by thermal excitation noise in the semiconductor. Therefore, the turn-off oscillation can be suppressed by preventing the parasitic resonance circuit having the natural frequency that matches the frequency when the IGBT chip oscillates from turning off from being present in the module.

Although it has been described above that the negative resistance is due to the propagation of holes, the holes are diffused as shown in FIG. Therefore, the negative resistance can be shown in a range of about ± 10% corresponding to the diffusion range from the oscillation center frequency (1 / T _p ) obtained by the equation (2). Therefore, even if the frequency of the parasitic resonance circuit does not completely match the reciprocal of the propagation time of the hole expressed by the equation (2), the device has a certain frequency range in which negative resistance is exhibited, for example, ± 10%. If so, turn-off oscillation can occur. Therefore, it is possible to obtain a semiconductor module in which turn-off oscillation does not occur more reliably by determining that Equation (2) does not hold within the range of ± 10% and setting the values of L and C.
Although the resonance circuit in this example is a parallel resonance circuit, oscillation can occur even in a series resonance circuit.

  FIG. 14 is a diagram showing a configuration example of a computer that executes a method for designing a power semiconductor module according to the embodiment of the present invention. Referring to FIG. 14, a mouse 114, a keyboard 116, and a display 118 are connected to a computer 150.

  The computer 150 is connected to the bus 120, a CPU (Central Processing Unit) 102, a ROM (Read Only Memory) 104 storing a program sent to the operating system, and the program to be executed And a RAM (Random Access Memory) 106 for storing data during program execution, and a hard disk (HDD) 108. The hard disk (HDD) 108 includes software (device simulator (device simulation program), electromagnetic field analysis software (electromagnetic field analysis program), oscillation center frequency calculation program, parasitic capacitance component extraction program, equivalent for executing this design method. A circuit model creation program, a resonance frequency calculation program, a frequency determination program, a design parameter change program, etc.) are stored.

  FIG. 15 is a flowchart illustrating a method for designing a power semiconductor module according to the embodiment of the present invention. In the present embodiment, the resonance frequency of the power semiconductor module on which the power semiconductor chip is mounted is extracted, and oscillation is avoided by obtaining the relationship between the resonance frequency and the oscillation center frequency of the power semiconductor chip.

  Referring to FIG. 15, the oscillation center frequency and the capacitance component of the power semiconductor chip are extracted by the processing of steps S1 to S3. The impedance of the package (indicated as “PKG” in FIG. 15) on which the power semiconductor chip is mounted is extracted by the processing in steps S11 to S13, and the resonance circuit is calculated.

  In step S1, the chip structure of the power semiconductor element (size, impurity concentration, arrangement, etc. of each region constituting the chip) is determined. Based on this chip structure, device simulation in step S2 is performed. When redesigning the chip structure of the power semiconductor element, device simulation is performed using the determined chip structure as an initial parameter, and parameters related to the chip structure are changed until an OK determination is made in step S6. Repeat thereafter.

Step S2 includes steps S2A to S2C. In step S2A, the computer executes device simulation of the power semiconductor chip using a device simulator such as the above-mentioned Medici. In step S2B, the hole drift velocity distribution is extracted by simulation. As shown in Expression (2), the oscillation center frequency 1 / T _p of the power semiconductor element is determined by the time that the holes travel in the depletion layer during the turn-off period of the power semiconductor chip.

  In step S2C, the oscillation center frequency of the power semiconductor element of the power semiconductor chip is calculated by the oscillation center frequency calculation program based on the relationship of Expression (2).

  In step S3, the capacitance component of the power semiconductor element is extracted from the device simulation result by the parasitic capacitance component extraction program.

  On the other hand, in step S11, the package structure of the power semiconductor module is determined. The “package structure” specifically includes, for example, the structure of a base plate, an aluminum wire or an insulating metallized substrate, and the structure of a main electrode for connecting a power semiconductor chip to external wiring. The electromagnetic field simulation in step S12 is performed using the determined package structure as an initial parameter.

  In step S12, an electromagnetic field simulation using electromagnetic field analysis software (for example, Q3D Extractor manufactured by Ansys) is executed on the package structure obtained in step S11. In step S13, the impedance of the power semiconductor module including the main electrode terminal, the wire, and the insulating metallized substrate is extracted by the simulation in step S12.

  In step S4, an equivalent circuit model is created by an equivalent circuit model creation program using the capacitance component of the power semiconductor chip obtained in step S3 and the impedance obtained in step S13. Next, in step S5, the resonance frequency is calculated from the equivalent circuit model by the resonance frequency calculation program. Subsequently, in step S6, the resonance frequency and the oscillation center frequency are compared and determined by the frequency determination program. If it is determined in step S6 that the resonance frequency does not exist within the predetermined frequency range including the oscillation center frequency, the design of the power semiconductor module is appropriate (OK), that is, the voltage oscillation at the turn-off time of the IGBT element. Does not occur.

  On the other hand, if it is determined in step S6 that the resonance frequency exists within a predetermined frequency range including the oscillation center frequency, the design of the power semiconductor module is not appropriate (NG), that is, voltage oscillation at the time of turn-off of the IGBT element. Means that

In the comparison and determination between the resonance frequency and the oscillation center frequency, it is possible to determine whether or not the resonance frequency matches the oscillation center frequency. However, the IGBT element can exhibit a negative resistance within a range of about ± 10% from the oscillation center frequency (1 / T _p ) obtained by Expression (2). Therefore, a frequency range for determination is provided, and the predetermined frequency range is set to ± 10% of the oscillation center frequency (that is, 90% to 110% of the oscillation center frequency), and the resonance frequency is based on the oscillation center frequency in step S6. When it is determined that the power semiconductor module is not within the range of ± 10% of the oscillation center frequency, it is determined that the design of the power semiconductor module is appropriate (OK), and the resonance frequency is determined based on the oscillation center frequency. If it is determined that the power semiconductor module is not properly designed (NG) when it is determined to be within the range of ± 10%, it is more preferable because a module that does not oscillate more reliably can be designed.
In addition, the frequency range for determination can also be taken as ranges other than the above. If the range is wider than ± 10% of the oscillation frequency, the margin for oscillation is further increased, so that a module that avoids oscillation more reliably can be obtained.

In step S6, the computer frequency determination program compares and determines the resonance frequency and the oscillation center frequency. If it is determined to be OK based on the criteria described above, the entire process is completed, and the design of the power semiconductor module is completed.
If the frequency determination program determines that the frequency determination program is NG in step S6, the computer design parameter change program determines the design parameters relating to the package structure (for example, the aluminum wire, the insulating metallized substrate and the wiring pattern formed on the surface thereof, and the size of the main electrode , Length, arrangement, etc.) are changed by a predetermined value to reset the package structure. Then, calculation, circuit component extraction, and equivalent circuit model creation are performed again from the step S12 in the order shown in FIG. 15, and the design parameters are repeatedly changed until the determination program determines OK in step S6.
When designing or examining the chip structure, when the frequency determination program determines NG in step S6, the design parameter change program changes the design parameter related to the chip structure from step S2 to FIG. Repeat until step S6. The above is the operation of the power semiconductor module design system by the computer.

  It is also possible for the designer to finish the design of the power semiconductor module based on the determination result in step S6, or to redesign the package structure or chip structure. It is also possible for the designer to manually compare and determine the oscillation center frequency calculated in step S2C and the resonance frequency calculated in step S5. If the designer redesigns, the calculation is performed again in the order shown in FIG. 15 from step S12 or step S2, and the determination of step S6 is made.

  According to the present embodiment, since it is possible to predict the presence or absence of oscillation on the simulation, it is not necessary to make a prototype. Therefore, the design efficiency can be improved. Further, since oscillation can be avoided, the noise of the power semiconductor module can be reduced.

  According to the present embodiment, it is possible to change the resonance frequency on the simulation by appropriately changing the equivalent circuit model. Therefore, oscillation of the power semiconductor module can be avoided without inserting a high-frequency loss element or a resistor into the gate. As a result, the loss can be reduced without increasing the rise time of switching of the power semiconductor.

  In addition, since it is not necessary to secure a region necessary for mounting a high-frequency loss element and a resistor in the power semiconductor module, it is possible to reduce the size and cost of the power semiconductor module.

In the present embodiment, the power semiconductor element has been described as an example of an IGBT element and a diode. The IGBT element is used as a switching element in an inverter circuit or a converter circuit of a power semiconductor module. However, even if it is not an IGBT element, a negative resistance region can exist if it is a bipolar semiconductor element. Therefore, even in a power semiconductor module equipped with a bipolar semiconductor element other than an IGBT element, the resonance frequency of an equivalent circuit composed of the capacitance component of the semiconductor element and the impedance of the package matches the oscillation center frequency of the bipolar semiconductor element. In the case of or in a predetermined frequency range including the oscillation center frequency, oscillation may occur. Oscillation can be avoided by applying this embodiment to the design of a semiconductor module equipped with a bipolar semiconductor element. Examples of the bipolar semiconductor element include a P / N junction diode, and examples of the bipolar semiconductor switching element include a bipolar transistor and a thyristor.
When a plurality of bipolar semiconductor elements having different structures or different characteristics are mounted on the power semiconductor module, the oscillation center frequency is calculated for each of the bipolar elements having different structures or different characteristics in step S2, and any of the bipolar semiconductor elements in step S6 is determined in step S6. When there is no resonance frequency near the oscillation center frequency (that is, within a predetermined range), OK is determined, and when there is a resonance frequency near any center frequency (within the predetermined range), NG is determined.

  It goes without saying that the design method in the present embodiment can be applied to both a power semiconductor module on which a single power semiconductor chip is mounted and a power semiconductor module on which a plurality of power semiconductor chips are mounted. In any power semiconductor module, it is possible to avoid oscillation by extracting the resonance frequency by the method described above and obtaining the relationship between the resonance frequency and the negative resistance region of the power semiconductor chip.

  In a power semiconductor module on which a plurality of power semiconductor elements are mounted, a main electrode terminal (main electrode terminal 5 shown in FIG. 2) and an aluminum wire (aluminum wire 4 shown in FIG. 2) for connecting a chip to be mounted to an external wiring. 12) and the impedance of the insulating substrate (insulating metallized substrate 2 shown in FIG. 2) exist in a complicated manner, so that there are many resonance frequencies. Therefore, there is a problem in that it is not easy to increase the capacity because oscillation is more likely to occur than in a power semiconductor module on which one power semiconductor element is mounted.

  However, since the resonance frequency can be changed by simulation, even if the structure of the power semiconductor module is complicated, the area necessary for mounting the high-frequency loss element and resistance corresponding to each power semiconductor element is secured to prevent oscillation. There is no need to do it. Therefore, particularly in a power semiconductor module on which a plurality of power semiconductor elements are mounted, it is possible to realize a reduction in size and cost of the power semiconductor module. Furthermore, even for complicated modules, a design that avoids oscillation while ensuring a margin can be made by simulation, and a large capacity and stable operation of the power semiconductor module can be easily realized.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 base plate, 2 insulating metallized substrate, 3A IGBT chip, 3B freewheeling diode chip, 4,12 aluminum wire, 5A, 5B main electrode terminal, 10 gate balance resistor, 11 high frequency loss element, 20 n-layer, 21 depletion layer, 24 p + layer, 25 holes, 100 power semiconductor module, 102 CPU, 104 ROM, 106 RAM, 108 HDD, 114 mouse, 116 keyboard, 118 display, 120 bus, 150 computer.

Claims (5)

A method for designing a power semiconductor module equipped with a bipolar power semiconductor element,
Calculating the hole propagation time in the bipolar power semiconductor element by integrating the reciprocal of the hole velocity over the thickness of the depletion layer generated in the bipolar power semiconductor element;
Creating an equivalent circuit of the power semiconductor module;
Calculating a resonance frequency of the equivalent circuit;
Determining whether the resonance frequency is within a predetermined range including a frequency represented by a reciprocal of the Hall propagation time ,
The method for designing a power semiconductor module, wherein the predetermined range is a range of 90% to 110% of a frequency represented by a reciprocal of the hall propagation time . The method of designing a power semiconductor module according to claim 1, wherein the hole velocity is obtained based on an electric field strength in the depletion layer region. The method for designing a power semiconductor module according to claim 1, wherein the bipolar power semiconductor element includes a semiconductor switch element. The method for designing a power semiconductor module according to claim 3, wherein the semiconductor switch element is an IGBT element. The bipolar power semiconductor element includes a plurality of IGBT elements,
5. The power semiconductor module design method according to claim 1, wherein the power semiconductor module includes a free-wheeling diode corresponding to each of the plurality of IGBT elements. 6.

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