JP5678862B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter that converts a voltage using a resonance current.

  High frequency operation is required to reduce the size of the power supply. However, when a high frequency operation is performed, the switching loss increases and the efficiency of the power supply is reduced. Also, a large heat sink is required to cool the switching element, increasing the size and cost of the system.

  The class E DC-DC converter 1 shown in FIG. 12 converts the voltage Vin input from the DC power supply 2 and outputs the voltage Vo to the load 3 (indicated by a resistor). Since the switching loss is very small (theoretically zero), it is particularly suitable for high-frequency operation (see Patent Document 1). The DC-DC converter 1 forms a closed circuit together with an inductor 4 and a MOS transistor 5 connected in series between input terminals, an inductor 6 and a capacitor 7 which are series resonant elements, and the MOS transistor 5, the inductor 6 and the capacitor 7. Thus, the diode 8 is configured to flow a negative resonance current Ir, the output capacitor 9 is configured to flow a positive resonance current Ir, and the like. A capacitor 11 and a diode 12 are connected in parallel to the MOS transistor 5. The positive direction of the resonance current Ir is indicated by an arrow in the figure.

  When the MOS transistor 5 is turned on when the drain-source voltage VDS (Q1) of the MOS transistor 5 is reduced to zero, the resonance current Ir flowing in the positive direction flows in the negative direction. Thereafter, when the MOS transistor 5 is turned off, the resonance current Ir flows into the capacitor 11, and the drain-source voltage VDS (Q1) rises rapidly.

However, such a class E DC-DC converter 1 has the following disadvantages.
(1) The output voltage Vo is controlled by variable frequency operation. In order to adjust the load current, the switching frequency must be varied over a wide range. For this reason, when the output voltage varies, the circuit operation becomes unstable.
(2) It is difficult to maintain zero voltage switching when the output current is small.
(3) The circuit does not operate when there is no load.
(4) Due to the resonance operation, high voltage stress is applied to the switching element (MOS transistor 5).
(5) The voltage stress applied to the switching element greatly depends on the capacitance value of the capacitor 11. However, it is difficult to increase the capacitance value of the capacitor 11 in order to realize zero voltage switching.

  In response to these disadvantages, various circuit configurations have been devised to control the class E DC-DC converter at a constant switching frequency and to maintain zero voltage operation from no load to full load. For example, the circuit described in Non-Patent Document 1 has a configuration in which two independent class E converters are combined. However, many components of four inductors and two resonant branches are required, increasing the cost and size of the system. In addition, it is difficult for the two resonance branches and the capacitor to actually perform symmetrical operations.

  The circuit described in Patent Document 2 can realize a fixed frequency operation by a phase shift control technique. However, the need for many components of four inductors and a large transformer increases the size and cost of the system. The circuit described in Patent Document 3 can realize zero voltage switching and a constant switching frequency under full load conditions by using a resonance circuit formed by a leakage inductance formed by a resonance capacitor and a primary winding of a transformer. However, large transformers with three windings increase system size and cost, thus degrading system performance.

US Pat. No. 4,607,323 US Pat. No. 5,065,300 US Pat. No. 7,388,762

Chuan-Qiang Hu et al, "Class E combined converter by Phase-shift Control", IEEE PESC'89, June. 1989, pp229-234

  The present invention has been made in view of the above circumstances, and its purpose is to maintain a zero voltage switching from no load to a maximum load while operating at a constant switching frequency and duty ratio, and to reduce voltage stress applied to the switching element. An object of the present invention is to provide a DC-DC converter that can be reduced and can be reduced in size and cost as compared with the conventional configuration.

  The DC-DC converter according to claim 1 is a first converter that inputs a DC voltage through an input terminal and outputs an alternating current due to resonance through an AC output node, and an output terminal that receives an AC current from the AC output node. And a second converter that outputs a DC voltage via the first converter, and a conversion control circuit that controls the first converter and the second converter.

  The first converter includes a tapped inductor and a resonant capacitor connected in series between one end of the input terminal and the AC output node, and a main connected between the tap of the tapped inductor and the other end of the input terminal. The switching element includes a parallel capacitor and a parallel diode connected in parallel with the main switching element.

  The second conversion unit forms a current path through which a current can flow bidirectionally between the AC output node and the other end of the input terminal, and sets the current conduction width of the current in at least one direction with respect to the AC current flowing through the current path. A controllable current control circuit, an output capacitor provided between the output terminals, and a rectification circuit that rectifies the current in the cut-off direction and flows it to the output capacitor during the period in which the current control circuit cuts off the current. I have.

  The conversion control circuit drives the main switching element with a drive signal having a fixed frequency and duty ratio, and controls the energization width of the current control circuit based on the detected voltage between the output terminals. The operations and effects of this configuration are as follows. However, since the forward voltage of the diode is low, it is set to zero. An alternating current due to resonance is referred to as a resonance current.

  When the main switching element is in the off-drive period, when a resonant current in this direction (positive direction) is flowing through the path consisting of the parallel diode, tapped inductor, resonant capacitor, current control circuit or rectifier circuit, it is applied to the main switching element. The voltage becomes zero. At this time, when the main switching element is driven on, the resonance current decreases to zero and then flows in the negative direction through a path through the main switching element. This negative resonance current flows back through the current control circuit or flows to the output capacitor through the rectifier circuit.

  Thereafter, when the main switching element is driven off, the resonance current flows into the parallel capacitor and the voltage applied to the main switching element rises. Since a tapped inductor is used, if the input voltage of the DC-DC converter is Vin, the output voltage is Vo, and the number of turns before and after tapping of the tapped inductor is N1 and N2, the voltage stress applied to the main switching element is (Vin · N2 + Vo · N1) / (N1 + N2). Eventually, the resonance current flows in the positive direction, and when the voltage between the terminals of the parallel capacitor becomes zero, the current flows through the parallel diode. This positive resonance current flows back through the current control circuit or flows to the output capacitor through the rectifier circuit.

  The electric power converted from the direct current state to the alternating current state by resonance in the first conversion unit is sent to the load according to the energization width of the current control circuit of the second conversion unit. That is, if the energization width of the current control circuit is widened, the transmission power to the load can be reduced, and if the energization width of the current control circuit is narrowed, the transmission power to the load can be increased. Therefore, by controlling the energization width of the current control circuit based on the detection voltage between the output terminals, while maintaining zero voltage switching without affecting the resonance operation from no load to the maximum load (full load) A stable conversion operation can be performed using a constant switching frequency and a constant duty ratio. Since this means has a single resonance circuit having one inductor with a tap and does not include other inductors or transformers, the size and cost can be reduced as compared with the conventional configuration.

  According to the means described in claim 2, the current control circuit has a configuration in which a first switching element and a second switching element having reverse conductivity are connected in series in opposite directions with an intermediate node interposed therebetween. The rectifier circuit is a full-wave rectifier circuit having a configuration in which a diode is provided in a forward direction on each path from both ends of the current control circuit to one end of the output terminal, and an intermediate node and the other end of the output terminal are connected.

  According to this configuration, the current control circuit is energized by turning on the switching element in which the conduction direction by the on drive coincides with the direction of the resonance current among the first and second switching elements, thereby supplying power to the load. Is refused. On the other hand, when the first and second switching elements are driven off, the current control circuit is cut off, the resonance current is rectified and flows to the load side, and power is supplied to the load. Since the full-wave rectifier circuit is employed, power can be supplied to the load in both the positive and negative periods of the resonance current.

  According to the means described in claim 3, among the diodes constituting the rectifier circuit, in parallel with the diode provided in the forward direction on the path from the AC output node to one end of the output terminal, the AC output node is connected from one end of the output terminal. The switching element for regeneration which supplies an electric current in the direction of is provided. Thereby, for example, when driving a load such as a motor, power can be regenerated from the load connected to the output terminal to the DC power source connected to the input terminal.

  According to the means described in claim 4, the current control circuit is constituted by a switching element having reverse conductivity. The rectifier circuit is a half-wave rectifier circuit having a configuration in which a diode is provided in a path from one end of the current control circuit to one end of the output terminal, and the other end of the current control circuit is connected to the other end of the output terminal.

  According to this configuration, the current control circuit is energized and the power supply to the load is cut off due to the reverse continuity of the switching element during a period in which the conduction direction due to the ON driving of the switching element is opposite to the direction of the resonance current. On the other hand, during the period in which the conduction direction due to the on-drive of the switching element coincides with the direction of the resonance current, the power supply to the load is cut off by the on-drive of the switching element, and the resonance current flows to the load side due to the off drive. Power is supplied. That is, the power supply to the load can be controlled in the half cycle of the resonance current.

  According to the means described in claim 5, the regenerative switching element is provided in parallel with the diode constituting the rectifier circuit so that a current flows from one end of the output terminal to the AC output node. Thereby, for example, when driving a load such as a motor, power can be regenerated from the load connected to the output terminal to the DC power source connected to the input terminal.

  According to the means described in claim 6, the switching element is composed of a MOS transistor. A parasitic capacitor and a parasitic diode are formed in the MOS transistor. These can be used as the parallel capacitor and the parallel diode described above. Further, reverse conductivity is imparted to the switching element of the current control circuit.

The block diagram of the DC-DC converter which shows the 1st Embodiment of this invention (A) is a path diagram of the current flowing from the DC power source through the MOS transistor Q1, and (b) is a diagram showing the driving state of the MOS transistor Q1 and the magnetic flux φ of the inductor Lt. Waveform diagram of the first converter Operation explanatory diagram of the first conversion unit Waveform diagram of second converter Operation explanatory diagram of the second conversion unit FIG. 1 equivalent diagram showing a second embodiment of the present invention Waveform diagram of driving state and resonance current of MOS transistors Q1 and Q2. 6 equivalent diagram FIG. 1 equivalent view showing a third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention 1 equivalent diagram showing the prior art

In each embodiment, substantially the same parts are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 6. FIG. 1 shows a configuration of a DC-DC converter that converts an input DC voltage into a DC voltage of a different level and outputs it. The DC-DC converter 21 includes a first conversion unit 24 that is a DC-AC converter, a second conversion unit 25 that is an AC-DC converter, a conversion control circuit 26, and a voltage detection circuit 27.

  The first converter 24 receives the DC voltage Vin from the DC power supply 22 via the input terminals 21a and 21b, and outputs an alternating current (hereinafter referred to as a resonance current) due to resonance through the node n2 (AC output node). The second converter 25 receives the resonance current from the node n2 and outputs a DC voltage Vo to the load 23 (indicated by the resistor Ro) via the output terminals 21c and 21d. The conversion control circuit 26 controls the first conversion unit 24 and the second conversion unit 25 based on the output voltage Vo and the target voltage Vref detected by the voltage detection circuit 27. The voltage detection circuit 27 is composed of, for example, a voltage dividing resistor, and includes a ground level conversion circuit as necessary.

  In the first converter 24, a tapped inductor Lt and a capacitor Cr (resonant capacitor) are connected in series between the input terminal 21a and the node n2. The inductor Lt has a configuration in which a tap is provided on a single inductor, and inductors L1 and Lr having turns N1 and N2 are formed with the tap interposed therebetween. The tap is connected to node n1. The inductor L1 is connected between the input terminal 21a and the node n1, and the inductor Lr is connected between the node n1 and the capacitor Cr.

  An N-channel MOS transistor Q1 (main switching element) is connected between the node n1 and the input terminal 21b (ground line 28). A capacitor C1 and a diode D1 are connected in parallel with the MOS transistor Q1. Since a parasitic capacitor and a parasitic diode are formed in the MOS transistor Q1, these are used as the capacitor C1 and the diode D1. If the capacitance of the parasitic capacitor is insufficient, another capacitor may be added.

  In the second converter 25, a current control circuit 29 capable of flowing current bidirectionally is connected between the node n2 and the input terminal 21b (ground line 28). In the current control circuit 29, an N-channel MOS transistor Q2 (first switching element) and a MOS transistor Q3 (second switching element) are connected in series in opposite directions with a node n3 (intermediate node) interposed therebetween. Capacitor C2 and diode D2 connected in parallel to MOS transistor Q2 and capacitor C3 and diode D3 connected in parallel to MOS transistor Q3 are the parasitic capacitor and parasitic diode of MOS transistors Q2 and Q3, respectively. If the capacitance of the parasitic capacitor is insufficient, another capacitor may be added. Since there are the diodes D2 and D3, the MOS transistors Q2 and Q3 have reverse conductivity, respectively.

  A filter capacitor Co (output capacitor) is connected between the output terminals 21c and 21d. The rectifier circuit 30 including the diodes D4 and D5 is a full-wave rectifier circuit that rectifies the current in the interrupted direction and flows it to the capacitor Co and the load 23 while the current control circuit 29 is interrupting the current. The diode D4 is connected in a forward direction to a path from one end (node n2) of the current control circuit 29 to the output terminal 21c, and the diode D5 is connected from the other end (input terminal 21b) of the current control circuit 29 to the output terminal 21c. Is connected in the forward direction to the route leading to. The node n3 is connected to the output terminal 21d.

  The conversion control circuit 26 drives the MOS transistor Q1 with a drive signal having a constant switching frequency and a duty ratio of 50%. Further, based on the detected output voltage Vo (detected voltage), the energization width of the MOS transistors Q2 and Q3 constituting the current control circuit 29 is controlled.

  Next, the operation of the present embodiment will be described with reference to FIGS. The inductor Lr and the capacitor Cr are resonance elements, and the resonance current Ir flowing through this resonance branch is assumed to be a sine wave.

  FIG. 2A shows a return path of a current flowing from the DC power supply 22 through the inductor L1 and the MOS transistor Q1 when the MOS transistor Q1 is turned on. FIG. 2B shows the on / off driving state of the MOS transistor Q1 and the magnetic flux φ of the inductor Lt. Ts is a switching period. During the ON period of the MOS transistor Q1, the magnetic flux φ of the inductor Lt increases linearly, and energy is stored in the inductor L1.

  When the MOS transistor Q1 is turned off, the energy stored in the inductor L1 and the input energy from the DC power supply 22 are sent to the second converter 25 through the resonance branch. As long as current flows through the inductors L1 and Lr during the off period of the MOS transistor Q1, the magnetic flux φ of the inductor Lt decreases linearly. The energy stored while the MOS transistor Q1 is on is sent to the second converter 25, and the energy required to obtain the output voltage Vo equal to the target voltage Vref is supplied to the load 23.

Since the inductor Lt is provided with a tap, an additional control parameter is formed for voltage conversion. The voltage stress VQ1 applied to the MOS transistor Q1 is expressed by equation (1) using the input voltage Vin, the output voltage Vo, and the number of turns N1 and N2 of the inductors L1 and Lr.
VQ1 = (Vin · N2 + Vo · N1) / (N1 + N2) (1)

  Thus, when the tapped inductor Lt is used, it becomes easy to control the voltage transfer rate Vo / Vin of the DC-DC converter 21 as a function of the tap position, and the voltage stress of the MOS transistor Q1 can be reduced. In the conventional class E converter, it is known that the voltage stress of the main transistor (corresponding to the MOS transistor Q1 of this embodiment) at a duty of 50% is about 3.6 times the input voltage Vin. Yes.

  FIG. 3 is a waveform diagram of the first converter 24, and FIG. 4 is an operation explanatory diagram of the first converter 24. One cycle of switching is divided into periods from Ta1 to Ta5 based on the current state. FIG. 4A shows the actual direction of current during the period Ta2 in which the MOS transistor Q1 is turned on and the positive drain current ID (Q1) flows. FIG. 4B shows the actual direction of current during the period Ta4 in which the MOS transistor Q1 is turned off and the negative discharge current IC1 flows through the capacitor C1. FIG. 4C shows the actual direction of current during the period Ta5 in which the MOS transistor Q1 is turned off and the diode D1 is energized.

  Here, the direction in which the resonance current Ir flows from the node n1 to the node n2 is positive. The direction in which the drain current ID (Q1) of the MOS transistor Q1, the current IC1 of the capacitor C1, and the current ID1 of the diode D1 flow from the node n1 to the ground line 28 is positive. Further, the current IL1 of the inductor L1 is positive in the direction flowing from the input terminal 21a to the node n1.

  Hereinafter, the operation in each period will be described. As is apparent from the direction of the current, the relationship of IL1 = ID1 + Ir is established in the periods Ta1 and Ta5, the relationship of IL1 = ID (Q1) + Ir is established in the period Ta2, and IL1 = in the periods Ta3 and Ta4. The relationship of IC1 + Ir is established.

(1) Period Ta1
At the start of the period Ta1, the MOS transistor Q1 is turned on. The MOS transistor Q1 is turned on when the current ID1 flows through the diode D1 and VDS (Q1) = 0, that is, when no charge is accumulated in the capacitor C1, and therefore, the zero voltage switching is performed. Even if the MOS transistor Q1 is turned on, the resonance current Ir flows in the positive direction within this period, so that dVDS (Q1) / d (2π) = 0 and zero current switching is performed.

(2) Period Ta2
Since the resonance current Ir changes from positive to negative at the start of the period Ta2, the current ID (Q1) flows through the MOS transistor Q1, and the current IL1 of the inductor L1 increases almost linearly. The resonance current Ir increases in the negative direction and then decreases. As described above, energy is stored in the inductor L1 during the periods Ta1 and Ta2.

(3) Period Ta3
At the start of the period Ta3, the MOS transistor Q1 is turned off. When the MOS transistor Q1 is turned off, VDS (Q1) = 0, so that zero voltage switching is performed. When the MOS transistor Q1 is turned off, the resonance current Ir flows in the positive direction. However, since the time when the MOS transistor Q1 is turned off does not necessarily coincide with the time when the resonance current Ir crosses from negative to positive, zero current switching is not performed.

  When the MOS transistor Q1 is turned off, the resonance current Ir that has been flowing in the MOS transistor Q1 so far flows into the capacitor C1 (IC1> 0), and the voltage VDS (Q1) of the MOS transistor Q1 rises. The voltage VDS (Q1) becomes maximum at the end of this period Ta3 when the current IC1 becomes zero. As described above, since the tapped inductor Lt is employed in the present embodiment, the voltage stress VQ1 of the MOS transistor Q1 can be adjusted to the required value according to the number of turns N1 and N2. For example, when N1 / N2 = 1, Vin = 288V, Vo = 15V, the voltage stress VQ1 can be suppressed to 152V according to the equation (1). On the other hand, in the conventional configuration, the voltage rises to about 1000 V (3.6 Vin). That is, in the conventional converter, a switching element having a high breakdown voltage that can withstand this high voltage is required.

(4) Period Ta4
At the start of this period Ta4, the current IC1 flowing through the capacitor C1 changes from positive to negative, and the charge of the capacitor C1 is discharged by the resonance current Ir. Along with this, the voltage VDS (Q1) decreases.

(5) Period Ta5
At the start of this period Ta5, the voltage VDS (Q1) becomes zero, and thereafter, the resonance current Ir flows through the diode D1.

  Next, the output voltage adjustment operation by the second converter 25 will be described. FIG. 5 is a waveform diagram of the second converter 25, and FIG. 6 is an operation explanatory diagram of the second converter 25. In order to be able to adjust the output voltage Vo while driving the MOS transistor Q1 with a drive signal having a constant frequency and a constant duty ratio, the conversion control circuit 26 drives the MOS transistors Q2, Q3 on and off in synchronization with the resonance current Ir.

  One cycle of switching is divided into periods from Tb1 to Tb8 based on the current state. FIGS. 5A to 5H show current paths in the periods Tb1 to Tb8, respectively. However, a current path through the MOS transistor Q1, the capacitor C1, or the diode D1 in the first conversion unit 24 and a current path not energized in the second conversion unit 25 are omitted.

  The conversion control circuit 26 turns on the MOS transistor Q2 when the resonance current Ir crosses from negative to positive zero, and turns on the MOS transistor Q3 when the resonance current Ir crosses zero from positive to negative. The conversion control circuit 26 shortens the ON energization width of the MOS transistors Q2 and Q3 when the output voltage Vo becomes lower than the target voltage Vref, and the ON energization width of the MOS transistors Q2 and Q3 when the output voltage Vo becomes higher than the target voltage Vref. Lengthen. As a result, the output voltage Vo can be controlled to be equal to the target voltage Vref.

Hereinafter, the operation in each period will be described.
(1) Period Tb1
At the start of the period Tb1, the resonance current Ir changes from negative to positive, and the MOS transistor Q2 is turned on. The MOS transistor Q2 is turned on when VDS (Q2) = 0, that is, when no charge is accumulated in the capacitor C2, and therefore is switched to zero voltage. Further, the MOS transistor Q2 is turned on when the resonance current Ir crosses zero, so that zero current switching is performed.

  On the other hand, the MOS transistor Q3 is off. Due to the rectification operation in the immediately preceding period Tb8, the charge corresponding to −Vo is accumulated in the capacitor C3, and therefore, the charge is discharged by the positive resonance current Ir in this period. Therefore, the resonance current Ir flows through the MOS transistor Q2 and the capacitor C3.

(2) Period Tb2
Since the voltage of the capacitor C3 becomes zero at the start of the period Tb2, the current ID3 starts to flow through the diode D3. The resonance current Ir flows through the MOS transistor Q2 and the diode D3.

(3) Period Tb3
At the start of the period Tb3, the MOS transistor Q2 is turned off. When the MOS transistor Q2 is turned off, VDS (Q2) = 0, so that zero voltage switching occurs, but zero current switching does not occur. When the MOS transistor Q2 is turned off, the resonance current Ir that has been flowing in the MOS transistor Q2 so far flows into the capacitor C2, and the voltage VC2 rises.

(4) Period Tb4
When the voltage VC2 becomes equal to the output voltage Vo at the start of the period Tb4, the diode D4 of the rectifier circuit 30 is energized, and the resonance current Ir flows through the diode D4, the capacitor Co (or load 23), and the diode D3. That is, the positive resonance current Ir is rectified and the capacitor Co is charged. By the period Tb1 to Tb4 described above, the control of the energization width and the rectifying action for the resonance current Ir in the positive direction are performed, and energy corresponding to the energization width is sent to the output side.

(5) Period Tb5
At the start of the period Tb5, the resonance current Ir changes from positive to negative, and the MOS transistor Q3 is turned on. Since the MOS transistor Q3 is turned on when VDS (Q3) = 0, that is, when no charge is accumulated in the capacitor C3, zero voltage switching is performed. Further, the MOS transistor Q3 is turned on when the resonance current Ir crosses zero, so that zero current switching is performed.

  On the other hand, the MOS transistor Q2 is off. Since the charge corresponding to + Vo is accumulated in the capacitor C2 by the rectification operation in the immediately preceding period Tb4, the charge is discharged by the negative resonance current Ir in this period. Therefore, the resonance current Ir flows through the MOS transistor Q3 and the capacitor C2.

(6) Period Tb6
Since the voltage of the capacitor C2 becomes zero at the start of the period Tb6, the current ID2 starts to flow through the diode D2. The resonance current Ir flows through the MOS transistor Q3 and the diode D2.

(7) Period Tb7
At the start of the period Tb7, the MOS transistor Q3 is turned off. When the MOS transistor Q3 is turned off, VDS (Q3) = 0, so that zero voltage switching is performed, but zero current switching is not performed. When the MOS transistor Q3 is turned off, the resonance current Ir that has been flowing in the MOS transistor Q3 so far flows into the capacitor C3, and the voltage VC3 rises in the negative direction.

(8) Period Tb8
When the absolute value of the voltage VC3 becomes equal to the output voltage Vo at the start of the period Tb8, the diode D5 of the rectifier circuit 30 is energized, and the resonance current Ir flows through the diode D5, the capacitor Co (or the load 23), and the diode D2. That is, the negative resonance current Ir is rectified and the capacitor Co is charged. During the period Tb5 to Tb8 described above, the energization width is controlled and rectified for the negative resonance current Ir, and energy corresponding to the energization width is sent to the output side.

Here, if the switching period of the MOS transistor Q1 is Ts, the control variable (energization width) for adjusting the output voltage is K, and the period of the resonance current Ir is 2π, the on-time Tr of the MOS transistors Q2 and Q3 is As shown in the equation (2). By changing the control variable K from 0 to π, the current passing through the diodes D4 and D5 is changed by full-wave rectification, and the output voltage Vo of the DC-DC converter 21 is adjusted.
Tr = Ts · K / (2π) (2)

  The operation at zero voltage switching and light load in the conventional converter depends on the relationship between the load resistance Ro that is actually driven and the maximum value Ro (max) of the load resistance that is the limit value of the light load operation. In order to operate while maintaining zero voltage switching, the condition of Ro <Ro (max) depending on circuit constants in the converter must be satisfied. On the other hand, the DC-DC converter 21 can overcome the above-described dependency by the newly introduced MOS transistors Q2 and Q3 of the second conversion unit 25.

  That is, in the case of no load, the MOS transistor Q2 is turned on and the diode D3 is energized when the resonance current Ir is positive, and the MOS transistor Q3 is turned on and the diode D2 is energized when the resonance current Ir is negative. Thereby, the equivalent load resistance seen from the 1st conversion part 24 which is a DC-AC converter becomes substantially zero. On the other hand, in the case of the maximum load (full load), the MOS transistor Q2 is turned off when the resonance current Ir is positive, and the MOS transistor Q3 is turned off when the resonance current Ir is negative. That is, the current control circuit 29 of the second conversion unit 25 is always cut off. Thereby, the equivalent load resistance viewed from the first conversion unit 24 becomes equal to the actual load resistance Ro.

  As a result, when the load 23 changes from no load to the maximum load, the equivalent load resistance viewed from the first converter 24 changes from zero to a resistance value corresponding to the maximum load. The condition of Ro <Ro (max) can always be satisfied by controlling the energization time of the MOS transistors Q2 and Q3 from K = π to K = 0. Therefore, the MOS transistor Q1 can maintain zero voltage switching for all load conditions. Considering each element such as maximum power output capability, optimum trade-off of voltage / current stress of MOS transistor Q1, and convenience for practical mounting, the drive signal of MOS transistor Q1 has a duty ratio of 50%. It is preferable to select.

  According to the present embodiment described above, in the first converter 24 that receives the DC voltage Vin and outputs the resonance current Ir, the inductor L1 that stores energy when the MOS transistor Q1 is turned on and the inductor Lr for resonance are provided. A single tap inductor Lt is used. This makes it easy to control the voltage transfer rate Vo / Vin as a function of the tap position of the inductor Lt, and the voltage stress VQ1 applied to the MOS transistor Q1 is changed from 3.6 Vin (Vin · N2 + Vo · N1). ) / (N1 + N2).

  A second conversion unit 25 including a current control circuit 29 and a rectifier circuit 30 is provided downstream of the first conversion unit 24, and a control variable K (energization width of the MOS transistors Q2 and Q3) is set based on the detected output voltage Vo. It was set as the structure controlled. Thereby, the equivalent load resistance seen from the 1st conversion part 24 can be changed dynamically according to the magnitude | size of the load 23, and the energy sent to the load 23 from the 1st conversion part 24 can be controlled. . As a result, under a wide load condition from no load to the maximum load, the MOS transistor Q1 can be controlled at a constant switching frequency and a constant duty ratio and can be zero-voltage switched. The voltage conversion operation can be performed stably even in a no-load state that is difficult to realize with the conventional configuration.

  In this case, the MOS transistors Q2, Q3 are also switched to zero voltage by the action of the capacitors C2, C3 and the diodes D2, D3. In addition, the MOS transistors Q1, Q2, and Q3 perform zero current switching when turned on. These zero voltage switching and zero current switching can greatly reduce the switching loss. When the duty ratio of the MOS transistor Q1 is set to 50%, the highest output power capability can be obtained.

  When a DC-DC converter is mounted on a vehicle, if the switching frequency of the MOS transistor Q1 changes widely, the resonance frequency enters the AM band or FM band of radio broadcasting, becomes radio noise, or falls to the audible range, which is annoying. It becomes acoustic noise. The DC-DC converter 21 of this embodiment can stabilize a wide range of frequency changes that have occurred in the conventional configuration due to a change in load current or a change in input voltage Vin, so that radio noise or acoustic noise can be easily generated. In addition, EMI can be reduced.

  In the conventional configuration in which the variable frequency operation is performed, if the capacitance value of the capacitor C1 is increased in order to reduce the voltage stress of the MOS transistor Q1, charge cannot be extracted within a predetermined period, and zero voltage switching cannot be realized. On the other hand, in this embodiment using a constant switching frequency, the voltage stress of the MOS transistor Q1 can be suppressed without affecting zero voltage switching. For this reason, in order to further reduce the voltage stress, the capacitance value of the capacitor C1 can be increased.

  The second converter 25 that inputs the resonance current Ir and outputs the DC voltage Vo includes a current control circuit 29 in which MOS transistors Q2 and Q3 having reverse conductivity are connected in series in the reverse direction, and a rectifier circuit that performs full-wave rectification. 30. For this reason, it is possible to supply power to the load 23 in both positive and negative periods of the resonance current. Further, since the DC-DC converter 21 has a single resonance circuit having one inductor Lt and does not require other inductors or transformers, the size and cost can be reduced as compared with the conventional configuration.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. The DC-DC converter 31 of this embodiment is obtained by changing the second conversion unit 25 of the DC-DC converter 21 described in the first embodiment into a half-wave rectifier circuit. A conversion unit 32, a conversion control circuit 33, and a voltage detection circuit 27 are included. A DC power supply 22 is connected to the input terminals 31a and 31b, and a load 23 is connected to the output terminals 31c and 31d. The input terminal 31b and the output terminal 31d are connected to the ground line 28.

  The second conversion unit 32 includes a current control circuit 34, a rectifier circuit 35, and a capacitor Co. The current control circuit 34 includes a MOS transistor Q2, a parasitic capacitor C2, and a parasitic diode D2 connected between the node n2 and the ground line 28, and can flow a current bidirectionally. The rectifier circuit 35 is a half-wave rectifier circuit including a diode D4 connected in a forward direction along a path from the node n2 to the output terminal 31c.

  The conversion control circuit 33 drives the MOS transistor Q1 with a drive signal having a constant switching frequency and a duty ratio of 50%. Further, based on the detected output voltage Vo, the energization width of the MOS transistor Q2 is controlled with respect to the positive current in synchronization with the resonance current Ir.

  FIG. 8 is a waveform diagram of the driving states of the MOS transistors Q1 and Q2 and the resonance current Ir, and FIG. 9 is an operation explanatory diagram of the second converter 32. One cycle of switching is divided into periods from Tc1 to Tc4 based on the current state. 9A to 9E show currents in the periods Tc1 to Tc5, respectively. However, the current path through the MOS transistor Q1, the capacitor C1, or the diode D1 in the first converter 24 is omitted. The conversion control circuit 33 drives the MOS transistor Q2 on when the resonance current Ir crosses from negative to positive zero. The conversion control circuit 33 controls the ON energization width of the MOS transistor Q2 in the same manner as the conversion control circuit 26 of the first embodiment.

Hereinafter, the operation in each period will be described.
(1) Period Tc1
At the start of the period Tc1, the resonance current Ir changes from negative to positive, and the MOS transistor Q2 is turned on. The MOS transistor Q2 is turned on when VDS (Q2) = 0, that is, when no charge is accumulated in the capacitor C2, and therefore is switched to zero voltage. Further, the MOS transistor Q2 is turned on when the resonance current Ir crosses zero, so that zero current switching is performed. The resonance current Ir flows through the MOS transistor Q2.

(2) Period Tc2
At the start of the period Tc2, the MOS transistor Q2 is turned off. When the MOS transistor Q2 is turned off, VDS (Q2) = 0, so that zero voltage switching is performed, but zero current switching is not performed. When the MOS transistor Q2 is turned off, the resonance current Ir that has been flowing in the MOS transistor Q2 so far flows into the capacitor C2, and the voltage VC2 rises.

(3) Period Tc3
When the voltage VC2 becomes equal to the output voltage Vo at the start of the period Tc3, the diode D4 of the rectifier circuit 35 is energized, and the resonance current Ir flows through the diode D4 and the capacitor Co (or the load 23). That is, the positive resonance current Ir is rectified and the capacitor Co is charged. During the period Tc1 to Tc3 described above, the control of the energization width and the rectifying action for the positive resonance current Ir are performed, and energy corresponding to the energization width is sent to the output side.

(4) Period Tc4
At the start of the period Tc4, the resonance current Ir changes from positive to negative. Since the charge corresponding to + Vo is accumulated in the capacitor C2 by the rectification operation in the immediately preceding period Tc3, the charge is discharged by the negative resonance current Ir in this period. Accordingly, the resonance current Ir flows through the capacitor C2.

(5) Period Tc5
Since the voltage of the capacitor C2 becomes zero at the start of the period Tc5, the current ID2 starts to flow through the diode D2. Therefore, the subsequent negative resonance current Ir flows through the diode D2. Since the current control circuit 34 does not include the MOS transistor Q3 for controlling the energization width with respect to the resonance current in the negative direction, energy cannot be sent to the output side during the periods Tc4 and Tc5.

  According to the present embodiment described above, when the load 23 changes from no load to the maximum load, Ro <Ro (max) is always established by controlling the energization time of the MOS transistor Q2 from K = π to K = 0. The condition can be met. Therefore, the present embodiment can provide the same effects as those of the first embodiment. However, since the second converter 32 employs a half-wave rectifier circuit, energy corresponding to the energization width can be sent to the output side only during a period in which the positive direction resonance current Ir flows.

(Third embodiment)
FIG. 10 shows a third embodiment obtained by modifying a part of the first embodiment. The second converter 42 of the DC-DC converter 41 includes a MOS transistor Q4 (regenerative switching element) that flows current in the direction from the output terminal 41c to the node n2 in parallel with the diode D4 constituting the rectifier circuit 43. . In addition, a MOS transistor Q5 is provided in parallel with the diode D5 constituting the rectifier circuit 43. The parallel diode D4 and the capacitor C4 and the parallel diode D5 and the capacitor C5 are the parasitic diodes and parasitic capacitors of the MOS transistors Q4 and Q5, respectively.

  According to this structure, the 2nd conversion part 42 can flow an electric current bidirectionally between input-output. The conversion control circuit 44 controls not only the power running operation for outputting a desired voltage Vo to the load 23 but also the regenerative power generated by the load 23, for example, a vehicle drive motor, to charge the DC power source 22, for example, a battery. can do.

(Fourth embodiment)
FIG. 11 shows a fourth embodiment in which a part of the second embodiment is modified in the same manner as the third embodiment. That is, the second conversion unit 52 of the DC-DC converter 51 includes a MOS transistor Q4 in parallel with the diode D4 constituting the rectifier circuit 53. According to this structure, the 2nd conversion part 52 can flow an electric current bidirectionally between input-output. The conversion control circuit 54 can control not only the power running operation but also the power obtained from the load 23 side to be regenerated to the DC power source 22.

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

In the second embodiment, the second converter 32 and the rectifier circuit 35 may include a MOS transistor Q3, a capacitor C3, and diodes D3 and D5 instead of the MOS transistor Q2, the capacitor C2, and the diodes D2 and D4. In this case, the energization width of the MOS transistor Q3 may be controlled with respect to the current in the negative direction in synchronization with the resonance current Ir.
In the third embodiment, the MOS transistor Q5 and the capacitor C5 may be omitted.
The energization widths of the MOS transistors Q2 and Q3 may be different from each other.

  In the drawings, 21, 31, 41, 51 are DC-DC converters, 21a, 21b, 31a, 31b, 41a, 41b, 51a, 51b are input terminals, 21c, 21d, 31c, 31d, 41c, 41d, 51c, 51d. Is an output terminal, 24 is a first conversion unit, 25, 32, 42, 52 are second conversion units, 26, 33, 44, 54 are conversion control circuits, 29, 34 are current control circuits, 30, 35, 43, 53 is a rectifier circuit, Q1 is a MOS transistor (main switching element), Q2 is a MOS transistor (first switching element), Q3 is a MOS transistor (second switching element), Q4 is a MOS transistor (regenerative switching element), D1, D4 and D5 are diodes, C1 is a capacitor, Cr is a capacitor (resonance capacitor), Co is a capacitor (output capacitor) Data), Lt inductor (inductor tapped), n2 is the AC output nodes, n3 is an intermediate node.

Claims (6)

A first converter that inputs a DC voltage via an input terminal and outputs an alternating current due to resonance through an AC output node, and a second converter that inputs an AC current from the AC output node and outputs a DC voltage via the output terminal And a conversion control circuit for controlling the first conversion unit and the second conversion unit,
The first converter is
A tapped inductor and a resonant capacitor connected in series between one end of the input terminal and the AC output node;
A main switching element connected between the tap of the tapped inductor and the other end of the input terminal;
A capacitor and a diode connected in parallel with the main switching element;
The second converter is
A current path that allows a current to flow in both directions is formed between the AC output node and the other end of the input terminal, and a current that can control the energization width of the current in at least one direction with respect to the AC current flowing in the current path. A control circuit;
An output capacitor provided between the output terminals;
A rectifier circuit that rectifies the current in the interrupted direction and flows the current to the output capacitor while the current control circuit cuts off the current;
The conversion control circuit drives the main switching element with a drive signal having a constant frequency and a duty ratio, and controls the energization width of the current control circuit based on a detection voltage between the output terminals. DC-DC converter. The current control circuit includes a configuration in which a first switching element and a second switching element having reverse conductivity are connected in series in opposite directions with an intermediate node interposed therebetween,
The rectifier circuit includes a diode in a forward direction on each path from both ends of the current control circuit to one end of the output terminal, and the intermediate wave node and the other end of the output terminal are connected to each other. The DC-DC converter according to claim 1, wherein:   A current flows from one end of the output terminal to the AC output node in parallel with a diode provided in a forward direction in a path from the AC output node to one end of the output terminal among the diodes constituting the rectifier circuit. The DC-DC converter according to claim 2, further comprising a switching element for regeneration. The current control circuit is composed of a switching element having reverse conductivity,
The rectifier circuit includes a diode in a path from one end of the current control circuit to one end of the output terminal, and a half-wave rectifier circuit configured such that the other end of the current control circuit and the other end of the output terminal are connected The DC-DC converter according to claim 1, wherein:   5. The DC-DC converter according to claim 4, further comprising a regenerative switching element that allows a current to flow from one end of the output terminal toward the AC output node in parallel with the diode constituting the rectifier circuit.   6. The DC-DC converter according to claim 1, wherein the switching element is composed of a MOS transistor.

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