JP5671443B2 - Polycrystalline silicon semiconductor device and manufacturing method thereof - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon semiconductor device and a manufacturing method thereof, and more specifically, a polycrystalline silicon thin film transistor (TFT) which is one of polycrystalline silicon semiconductor devices capable of effectively reducing the capacitance of a common gate line. It relates to the manufacturing method.

  Polycrystalline silicon (hereinafter, referred to as poly-Si as appropriate) has higher mobility and better light stability than amorphous silicon. Such polycrystalline silicon is used in a wide range of application fields, and in particular, is often used for TFTs and memory devices. The poly-Si TFT is used as a switching element of a display, for example. Display elements that use active elements such as TFT include TFT-LCD (Liquid Crystal Display), TFT-OLED (Organic Light Emitting Device), and the like.

  A TFT-LCD and a TFT-OLED have a structure in which a TFT is arranged in each pixel arranged in an XY matrix. Thus, the performance of LCDs, OLEDs, etc. in which a plurality of TFTs are arranged depends greatly on the electrical characteristics of the TFTs themselves. One of the important characteristics of TFT is the mobility of the Si active layer. Crystallization is essential to increase the mobility of the Si active layer. The research on crystalline silicon has been mainly focused on the development of poly-Si having properties similar to single crystals.

  On the other hand, in addition to a rigid and heat-resistant glass substrate, development of an LCD using a substrate made of an elastic and flexible material that is weak against heat, such as plastic, is in progress. Use of such a plastic substrate reduces the cost of the LCD. At the same time, the plastic substrate will be indispensable for the paper-like display, which will be the next generation development model.

  However, the disadvantage of plastic is that it is vulnerable to heat, and thus a low temperature process is required to apply the plastic substrate to the LCD. US Pat. No. 6,053,086 by Carry et al. Presents a method that can prevent plastic damage in the process of forming a silicon channel on a plastic substrate.

  However, according to the method such as carry, the silicon film not only exists as an active region under the gate, but also remains as an electrode portion that forms an unnecessary capacitance with the common gate line. Since the common gate line is obtained together with the gate, not only the gate insulating material but also the silicon material for forming the channel remains below the common gate line.

  This is because the gate insulating layer and the gate metal are deposited on the silicon and then the gate metal is patterned, doped and activated before the channel is patterned, so that the silicon existing in the portion excluding the channel region is removed. This is because the silicon region remains because the removal process is absent.

  The activated silicon remaining under the gate common line thus causes unnecessary parasitic capacitance between the gate common line and the substrate, and the gate common line eventually has a line resistance of the gate common line. At the same time, a distributed RC circuit is configured to cause signal transmission to the gate, so-called RC delay. Such a problem due to the parasitic capacitance similarly appears in a semiconductor element having a plurality of complementary transistors, for example, a CMOS transistor.

US Pat. No. 5,817,550

  The technical problem to be solved by the present invention is to eliminate the cause of the generation of the parasitic capacitance in the common gate line shared by the gates of the TFTs and effectively prevent the delay of the gate signal by the parasitic capacitance. A possible polycrystalline silicon semiconductor device and a method for manufacturing the same are presented.

A semiconductor device according to the present invention includes a substrate, a silicon film layer having a drain and a source formed by impurity doping, and a channel region therebetween, a gate corresponding to the channel region, and a gate and a channel. A pair of transistors, a separate input line connected together to the gates of the pair of transistors, a source of the first transistor and a second transistor of the pair of transistors. A separate output line coupled to the drain; a separate drive voltage line coupled to the drain of the first transistor; and a ground line coupled to the source of the second transistor. In this transistor, the channel of the silicon film layer is formed in the entire area under the gate. Wherein the region is formed.

  According to an embodiment of the semiconductor device of the present invention, an insulating layer having contact holes corresponding to the gate, source, and drain of the transistor is formed on the transistor, and the input line and output are formed on the insulating layer. A line, a driving voltage line, and a ground line are formed.

According to a preferred embodiment, the gates of the first and second transistors and the underlying gate insulating film have the same pattern, and the input line, the output line, the driving voltage line, and the ground line are formed of the same material. Is done .

According to the method for manufacturing a semiconductor device of the present invention, a substrate, a silicon film layer having a drain and a source formed by impurity doping, and a channel region therebetween, a gate corresponding to the channel region, and a lower portion of the gate are provided. In a method of manufacturing a semiconductor device including a first transistor and a second transistor including a gate insulating layer, forming a silicon material layer on a substrate, forming a gate insulating material layer on the silicon material layer, forming a gate material layer on the gate insulating material layer, wherein patterning the gate insulating material layer and the lower gate material layer, a gate insulating gate and its lower part of the first transistor and the second transistor Forming a layer, a channel of the first transistor, and both sides thereof A step of implanting a predetermined first impurity into a portion excluding a region corresponding to the source and drain; and a predetermined first impurity in a portion excluding the channel corresponding to the source and drain on both sides of the channel of the second transistor. A step of implanting two impurities and patterning the silicon material layer to form a channel region of a silicon film layer in an entire region under the gates of the first transistor and the second transistor; Forming a non-existing source and drain, forming an insulating layer on the stack formed up to now, and the source, drain and gate of the first and second transistors on the insulating layer Forming an electrical connection electrically connected to the device.

The step of forming an electrical connection part of the method for manufacturing a semiconductor device includes the step of forming contact holes corresponding to the source, drain and gate of the first and second transistors in the insulating layer, and on the insulating layer. And etching to form a predetermined pattern after forming the metal material layer. The step of forming the silicon material layer on the substrate may further include an amorphous silicon deposition step and an amorphous silicon crystallization step, and the first impurity may be B ⁺ (p−). Type) and the second impurity is P ⁺ (n− type).

  According to the present invention, the silicon material layer exists locally only under the gate, and therefore, the TFT polycrystalline silicon semiconductor having good electrical characteristics with the RC delay of the signal suppressed by the reduction of the parasitic capacitance. An element is obtained.

1 is a schematic view of an active matrix flat panel display to which a TFT according to the present invention is applied. FIG. 2 is an enlarged view showing one pixel of the flat display shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a sectional view taken along line B-B ′ in FIG. 2. FIG. 3 is a cross-sectional view taken along line C-C ′ in FIG. 2. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. It is process drawing explaining the manufacturing method of TFT by this invention. 1 is a schematic circuit diagram of a semiconductor device to which the present invention is applied. It is a top view which shows the layout of the semiconductor element by this invention. FIG. 9 is a sectional view taken along line D-D ′ of FIG. 8. FIG. 9 is a cross-sectional view taken along line E-E ′ of FIG. 8. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention. It is process drawing explaining the manufacturing method of the CMOS transistor by this invention.

Hereinafter, a TFT as a semiconductor device according to an embodiment of the present invention and a manufacturing method thereof, a CMOS transistor thereof, and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.
(TFT and manufacturing method thereof)

The TFT according to the present invention is applied to, for example, an AM (Active Matrix) -LCD and an AM-OLED as being arranged on an XY matrix on one substrate. X-Y matrix structure, as shown in FIG. 1, is arranged in a direction to not X _m and the source common line Y _o to not more than the gate common line X _o is Y _n and the gate common line perpendicular A TFT and a pixel electrode are provided in a pixel region having a known structure and existing at the intersection of these common lines. Here, the pixel electrode may be a pixel electrode of an OLED or a pixel electrode of an LCD.

  FIG. 2 is an enlarged view of one pixel region, and schematically shows an arrangement structure of the TFT 20, the pixel electrode 11, the common source line Y, and the common gate line X.

  As shown in FIG. 2, the common source line Y and the common gate line X are arranged vertically, and are electrically separated by an insulating layer (not shown). The gate common line X includes a jumper line X ″ provided at the intersection and a main line X ′ between the intersections. This is because the jumper line X ″ and the main line X ′ constituting the gate common line X are combined. These are formed through a separate process, and are connected to each other through a double rectangle and a contact portion in which two intersecting line segments are drawn and displayed in one rectangle. The contact portion shown in FIG. 2 represents a contact portion having a contact hole (described later) that electrically connects the upper and lower elements through an insulating layer. A TFT 20 and a pixel electrode 11 are provided in the pixel region. The TFT 20, the pixel electrode 11, the common source line Y and source 22, and the main line X ′ of the common gate line X are interconnected through the contact portion described above. The part to be noted here is that the gate common line is not only divided into two parts X ′ and X ″ as described above, but is also formed separately from the gate 21. In the case of the conventional TFT, since the gate common line and the gate are obtained from one metal thin film, a single main body is formed, which is a problem of the conventional gate common line, which is a problem of the conventional TFT. For removing a lower silicon material layer, the silicon material layer is a material used to form a channel, and is present under the gate common line according to the process characteristics of the conventional manufacturing method. However, the TFT according to the present invention does not have the lower silicon material layer in the common gate line, and this follows the characteristics of the manufacturing method according to the present invention described later.

  FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2, and is a vertical cross-sectional view showing a laminated structure of the TFT 20.

A SiO ₂ first insulating film 10 a is formed on the substrate 10, and a silicon film layer having an active layer and a source 22 and a drain 23 at both ends thereof is positioned thereon by poly-Si. A second insulating film 10b as a SiO ₂ gate insulating layer and a gate 21 are stacked at the center of the silicon film layer, that is, above the channel. Since the gate 21 and the second insulating film 10b below the gate 21 are simultaneously patterned, they have the same planar structure. An SiO ₂ third insulating film 10c serving as a first ILD (Inter Layer Dielectric) is formed on the stacked structure. A source contact hole 22a is formed in a portion corresponding to the source 22 in the SiO ₂ third insulating film 10c, and a source common line Y is connected thereto. On the source common line Y, a SiO ₂ fourth insulating layer 10d as a _second ILD is formed. Wherein on the drain 23 is the SiO ₂ third and insulating layer 10c and the drain contact hole 11a which penetrates the SiO ₂ fourth insulating layer 10d is formed, wherein the pixel electrode 11 are connected.

  FIG. 4 is a cross-sectional view taken along line B-B ′ of FIG. 2, and is a vertical cross-sectional view of the gate showing the connection structure of the gate and the common gate line connected thereto. FIG. 5 is a cross-sectional view taken along the line C-C ′ of FIG. 2 showing the stacked structure of the common gate line.

As shown in FIG. 4, in the TFT according to the present invention, a silicon material layer used for forming a channel exists only under the gate 21, and as shown in FIG. Does not exist at the bottom of The gate 21 overlapped with the channel 24 extends to a lower portion of the main line X ′ of the gate common line X, and the gate common line X is connected through a contact hole formed in the SiO ₂ third insulating layer 10c. It is in contact with the main line X ′. A SiO ₂ fourth insulating layer 10 d is formed on the main line X ′ of the gate common line X.

As shown in FIG. 5, the source common line Y is formed via the SiO ₂ fourth insulating layer 10d, and the main line X ′ provided with the source common line Y is the source common line. They are connected by a jumper line X ″ formed beyond Y.

  In the present invention as described above, the common gate line is formed separately from the gate, and therefore, silicon remaining under the common gate line can be removed. Such a structure is made possible by a structure in which the gate common line X 'is separated into two elements and formed separately from the gate.

  Hereinafter, a method of manufacturing a TFT according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the left part of each drawing is a plan view, and the right part is a cross-sectional view.

As shown in FIG. 6A, the SiO ₂ first insulating layer 10a is formed on the substrate 10 by a CVD (Chemical Vapor Deposition) method.

As shown in FIG. 6B, an a-Si (amorphous silicon) layer is formed on the substrate 10 on which the SiO ₂ first insulating layer 10a is formed by sputtering or PECVD (plasma enhanced chemical deposition).

As shown in FIG. 6C, the a-Si is crystallized by an Excimer (Exited Monomer) laser annealing to obtain a poly-Si layer. The annealing is performed by irradiating 1 to 10 times with a 308 nm XeCl excimer laser having an energy density of 150 to 300 mJ / cm ² .

6D, an SiO ₂ second insulating layer 10b used as a gate insulating layer is formed on the poly-Si layer to a thickness of about 1000 Å by ICP (Inductively Coupled Plasma) -CVD, PE (Plasma). (Enhanced) -CVD and sputtering.

As shown in FIG. 6E, a metal layer, for example, an Al (aluminum) layer used as the gate 21 is formed on the SiO ₂ second insulating layer 10b by a sputtering method.

  As shown in FIG. 6F, the Al layer is etched by a dry etching method using the first mask M1. The first mask M1 has a pattern corresponding to the shape of the gate. The gate 21 is patterned by such patterning, and the lower gate insulating layer 10b is patterned in the same shape. Through this, poly-Si is exposed through a portion not covered with the gate 21. The shape of the gate 21 has a portion that overlaps the channel of the TFT and a portion that is positioned below the common gate line as described above.

  As shown in FIG. 6G, a portion not covered with the gate 21 is doped with an impurity through an ion shower, and then activated by a 308 nm XeCl excimer laser.

  As shown in FIG. 6H, the source 22 and the drain 23 are formed by patterning poly-Si not covered with the gate by a dry etching method using a second mask. The lower portion of the gate 21 is left in a state where poly-Si is not doped with impurities, and thereafter functions as a channel.

As shown in FIG. 6I, a SiO ₂ third insulating layer 10c is formed as an ILD on the laminate to a thickness of about 3000 angstroms by ICP-CVD, PE-CVD, and sputtering.

As shown in FIG. 6J, a source contact hole 22a and a gate contact hole 21a are formed in the SiO ₂ third insulating layer using a third mask.

  As shown in FIG. 6K, a common source line and a common gate line are formed on the stacked structure shown in FIG. 6J. This includes a sputtering process of a metal, for example, a 2000 Å thick Al film, and a patterning process using a fourth mask (not shown). The common source line Y has a common source extension Y 'that extends over the source contact hole 22a and contacts the source 22 below. The gate common line X is cut off at a portion overlapping the source common line Y, and has a main line X 'passing over the gate contact hole 21a.

As illustrated in FIG. 6L, the SiO ₂ fourth insulating layer 10d is formed on the stacked structure illustrated in FIG. 6K by ICP-CVD, PE-CVD, or sputtering. The SiO ₂ fourth insulating layer 10d is used as a second ILD, and has a thickness of about 3000 Å as a layer on which a jumper line X ′ of the common gate line X, which will be described later, and the pixel electrode 11 are formed.

As shown in FIG. 6M, a conductive material, for example, an ITO thin film is deposited on the stacked structure shown in FIG. 6L, and then patterned to pass through the pixel electrode 11 and the source common line Y. A completed gate common line X is obtained by forming a jumper line X ″ for connecting both main lines X ′ of the gate common line X separated through the contact hole Xa.
(CMOS transistor and manufacturing method thereof)

FIG. 7 shows a basic circuit of a CMOS transistor. Referring to FIG. 7, a first transistor, for example, a p-type transistor 101, and a second transistor, for example, an n-type transistor 102 constitute one inverter. The source of the p-type transistor 101 and the drain of the n-type transistor 102 are both connected to the output line Vout, and their gates are connected to the input line Vin. The drive voltage V _DD is applied to the drain of the p− type transistor 101, and the source of the n− type transistor 102 is connected to the ground line. Since such a structure is known as a basic circuit of a CMOS transistor, a detailed description thereof is omitted here.

  8 is a schematic plan view showing a partial layout of a CMOS transistor according to the present invention, FIG. 9 is a cross-sectional view taken along line DD ′ of FIG. 8, and FIG. 10 is a cross-sectional view taken along line EE of FIG. FIG. In the drawing, a contact portion 20c, in which two intersecting line segments are drawn and displayed in a double rectangle and one rectangle in the double rectangle, is electrically connected to the upper and lower elements through an ILD insulating layer. 'Part.

Referring to FIGS. 8 and 9, the driving voltage line V _DD , the ground line Ground, and the output line Vout are contacted to the poly-Si layer through the contact hole 20c ′ provided in the ILD layer 20c. Here, the portion where the drive line V _DD is in contact is the drain of the p− type transistor 101, and the portion where the ground line Ground is in contact is the source of the n− type transistor 102. The portion where the output line Vout contacts is the source of the p− type transistor 101 and the drain of the n− type transistor 102. The line is made of metal, for example, aluminum.

8 and 10, the input line Vin is branched to form a contact hole 20c formed in the SiO ₂ ILD layer 20c at the gate 31a of the p-type transistor 101 and the gate 31b of the n-type transistor 102. 'Are connected through each. The gate 31a and the input line Vin are formed of a metal such as aluminum.

  Here, it should be noted that the gates 31a and 31b and the input line Vin connected thereto are separated into separate elements. This improves the problem caused by the parasitic capacitance by limiting the poly-Si existing under the gate only to the lower part of the gate, as in the structure description of the TFT described above. That is, the semiconductor device according to the present invention, for example, the above-described TFT or CMOS transistor does not have a lower silicon material layer such as a common gate line and an input line.

  Hereinafter, a method of manufacturing a TFT according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the left part of each drawing is a plan view, and the right part is a cross-sectional view.

As shown in FIG. 11A, the SiO ₂ first insulating layer 20a is formed on the substrate 10 by the CVD method.

As shown in FIG. 11B, an a-Si layer is formed on the substrate 20 on which the SiO ₂ first insulating layer 20a is formed by sputtering or PECVD.

As shown in FIG. 11C, the a-Si is crystallized by excimer laser annealing to obtain a poly-Si layer. Annealing of a-Si can be performed by 1 to 10 irradiations of a 308 nm XeCl excimer laser having an energy density of 150 to 300 mJ / cm ² .

As shown in FIG. 11D, a SiO ₂ second insulating layer 20b used as a gate insulating layer is formed on the poly-Si layer to a thickness of about 1000 Å by ICP-CVD, PE-CVD, or sputtering. To do.

As shown in FIG. 11E, a metal layer, for example, an Al layer 31, used as the gates 31a and 31b is formed on the SiO ₂ second insulating layer 20b by a sputtering method.

  As shown in FIG. 11F, the Al layer 31 is etched by a dry etching method using the first mask M1a to form gates 31a and 31b aligned with each other. The first mask M1a has a pattern corresponding to the shape of the gate. The gate 21 is patterned by such patterning, and the gate insulating layer 20b under the gate 21 is patterned in the same shape. Through this, poly-Si is exposed through the portions not covered by the gates 31a and 31b.

As shown in FIG. 11G, after selecting a region where a p-type transistor is to be formed using a PR (PhotoResist) mask 41, a predetermined first impurity, for example, P ⁺ is implanted into the remaining portion ( Impurity doping).

As shown in FIG. 11H, after removing the PR mask 41, the region where P ⁺ is implanted is activated by a 308 nm XeCl excimer laser. This time, after selecting the region where the n− type transistor is to be formed using the PR mask 42, a portion not covered with the PR mask 42 is implanted with a predetermined second impurity, for example, B ⁺ .

As shown in FIG. 11I, the PR mask 42 is removed. Through such a process, a P ⁺ doping region and a B ⁺ doping region are formed around each of the gates 31a and 31b, and the remaining portion is a region in which P ⁺ and B ⁺ are mixed and doped. The mixed doping region is removed in a subsequent process.

  As shown in FIG. 11J, poly-Si that is not covered by the quantity gates 31a and 31b is patterned by dry etching using the second mask M2a to form poly-Si 32a corresponding to the gates 31a and 31b. 32b is obtained. Both ends of each poly-Si 32a and 32b are a source and a drain doped with impurities. On the other hand, the entire lower part of the gates 31a and 31b is left undoped with poly-Si, and then functions as a channel between the source and the drain.

As shown in FIG. 11K, an SiO ₂ third insulating layer 20c is formed as an ILD to a thickness of about 3000 Å on the stacked portion by ICP-CVD, PE-CVD, and sputtering.

As shown in FIG. 11L, the third mask M3a is used to provide a large number of contact holes 20c ′ for the gate, source and gate contacts of the p− and n− type transistors in the SiO ₂ third insulating layer. Form.

As illustrated in FIG. 11M, the input line Vin, the output line Vout, the driving voltage line _VDD, and the ground line Ground are formed on the ILD third insulating layer 20c. These include sputtering deposition of a metal, eg, 2000 Angstrom Al film, and a patterning process using a fourth mask (not shown). The input line Vin, the output line Vout, the drive voltage line _VDD, and the ground line Ground are in electrical contact with the corresponding lower stack through the contact hole 20c ′.

  The manufacturing process of the present invention as described above is included as a part of a manufacturing process of an application element, for example, a CMOS transistor, and a part not described above follows a known process.

  Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely illustrative, and various modifications and equivalent other embodiments may be made by those skilled in the art. I understand. Therefore, the protection scope of the present invention must be determined by the technical idea of the claims.

  According to the present invention, a semiconductor device such as a TFT or a CMOS transistor having excellent electrical characteristics can be obtained, and the present invention can be applied to a flat panel display device such as an active matrix LCD or an active matrix OLED, a semiconductor transistor such as a semiconductor memory. Can be applied.

11 Pixel electrode 20 TFT
21 Gate 22 Source 23 Drain X Gate common line Y Source common line X 'Main per line X "Jumper line

Claims (8)

A substrate,
A silicon film layer having a drain and a source formed by impurity doping and a channel region therebetween, a gate corresponding to the channel region, and a gate insulating layer interposed between the gate and the channel. A pair of transistors;
A separate input line connected together to the gates of the set of transistors;
A separate output line coupled to the source of the first transistor and the drain of the second transistor of the set of transistors;
A separate drive voltage line connected to the drain of the first transistor;
A ground line connected to a source of the second transistor;
With
The semiconductor device according to claim 1, wherein a channel region of a silicon film layer is formed in an entire region under the gate.   An insulating layer having contact holes corresponding to the gate, source, and drain of the transistor is formed on the transistor, and the input line, output line, drive voltage line, and ground line are formed on the insulating layer. The semiconductor element according to claim 1.   2. The semiconductor device according to claim 1, wherein the gates of the first transistor and the second transistor and the gate insulating layer below the gates have the same pattern.   The semiconductor device according to claim 1, wherein the input line, the output line, the driving voltage line, and the ground line are formed of the same material. A first transistor comprising: a substrate; a silicon film layer having a drain and a source formed by impurity doping and a channel region therebetween; a gate corresponding to the channel region; and a gate insulating layer provided below the gate; In a method for manufacturing a semiconductor device comprising two transistors,
Forming a silicon material layer on the substrate;
Forming a gate insulating material layer on the silicon material layer;
Forming a gate material layer on the gate insulating material layer;
Patterning the gate material layer and a lower gate insulating material layer to form gates of the first and second transistors and a lower gate insulating layer;
Injecting a predetermined first impurity into the channel of the first transistor and a portion excluding regions corresponding to the source and drain on both sides thereof;
Injecting a predetermined second impurity into the channel of the second transistor and a portion excluding regions corresponding to the source and drain on both sides thereof;
The silicon material layer is patterned to form a channel region of a silicon film layer in an entire region under the gates of the first transistor and the second transistor, and a source and a drain that are not covered with the gates are formed. Stages,
Forming an insulating layer on the laminate formed in the previous steps;
Forming an electrical connection part electrically connected to the source, drain and gate of the first transistor and the second transistor on the insulating layer. The step of forming the electrical connection portion includes:
Forming contact holes corresponding to the source, drain and gate of the first transistor and the second transistor in the insulating layer;
6. The method of manufacturing a semiconductor device according to claim 5, further comprising: etching a predetermined pattern after forming a metal material layer on the insulating layer. Forming a silicon material layer on the substrate;
A deposition step of amorphous silicon;
6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of crystallizing amorphous silicon.   6. The method according to claim 5, wherein the first impurity is p-type and the second impurity is n-type.

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