JP5660462B2 - Printed wiring board - Google Patents

Description

The present invention relates to a printed wiring board incorporating an electronic component.

Patent Document 1 discloses embedding a semiconductor element in an insulating layer for thinning. The patent document 1 discloses a printed wiring board having an external terminal on one side and a printed wiring board having an external terminal on both sides.

JP 2006-222164 A

However, if an insulating layer and a conductor layer are further laminated on the printed wiring board of Patent Document 1, it is considered that the connection reliability between the electrode of the electronic component and the conductor layer on the insulating layer is lowered.

The printed wiring board disclosed in Patent Document 1 does not have a reinforcing core substrate for thinning, and incorporates electronic components in an insulating layer. For this reason, if another insulating layer is laminated on the insulating layer containing the electronic component, the amount of shrinkage differs greatly under the heat cycle between the layer containing the electronic component and the other insulating layer. Conceivable. As a result, it is considered that the amount of warpage of the printed wiring board increases. Therefore, it is considered that the connection reliability between the electrode of the electronic component and the conductor layer on the insulating layer is lowered.

An object of the present invention is to provide a thin printed wiring board with built-in electronic components and high connection reliability.

The printed wiring board according to the present invention has a first conductor layer, a first surface, and a second surface opposite to the first surface, and the second surface faces the first conductor layer. Formed on the first surface of the first resin insulation layer, the first resin insulation layer laminated on the first conductor layer, the electronic component housed in the first resin insulation layer and having an electrode. Formed in the first resin insulation layer, the first via conductor passing through the first resin insulation layer, and connecting the first conductor layer and the second conductor layer. A connection via conductor connecting the electrode of the electronic component and the second conductor layer, a first surface and a second surface opposite to the first surface, the second surface , The second resin insulation layer laminated on the first resin insulation layer, the second resin insulation layer so as to face the first surface of the first resin insulation layer, and the second resin insulation A third conductor layer formed on the first surface, and a second via conductor penetrating the second resin insulation layer and connecting the second conductor layer and the third conductor layer, Have. The second conductor layer is thicker than the third conductor layer.

The manufacturing process figure of the printed wiring board which concerns on embodiment of this invention. The manufacturing process figure of the printed wiring board of embodiment. The manufacturing process figure of the printed wiring board of embodiment. The manufacturing process figure of the printed wiring board of embodiment. The manufacturing process figure of the printed wiring board of embodiment. The manufacturing process figure of the printed wiring board of embodiment. Sectional drawing of the printed wiring board which concerns on embodiment of this invention. Application example of the printed wiring board of FIG. Sectional drawing of the printed wiring board which concerns on the modification of embodiment of this invention. Sectional drawing of the printed wiring board which concerns on another modification of embodiment of this invention. The top view which shows the diameter of the opening for via conductors.

[Embodiment 1]
A printed wiring board according to Embodiment 1 of the present invention will be described below with reference to FIGS.
FIG. 7 shows a printed wiring board according to the first embodiment, and FIG. 8 shows a package substrate 100 mounted on the printed wiring board according to the first embodiment. The printed wiring board of Embodiment 1 is mounted on the motherboard.

As shown in FIG. 7, the printed wiring board 1000 having solder bumps includes a first conductor layer 42, a first resin insulating layer 50 on the first conductor layer, and a second conductor on the first resin insulating layer. It has a conductor layer 58, a second resin insulation layer 60 on the first resin insulation layer and the second conductor layer, and a third conductor layer 68 on the second resin insulation layer.
The first conductor layer includes an external terminal 42. In FIG. 7, solder bumps 86D are formed on the external terminal. An electronic component 90 such as an IC chip is built in the first resin insulating layer. The electronic component has an electrode 92. The first resin insulation layer 50 and the second resin insulation layer 60 have a first surface and a second surface opposite to the first surface. The second surface of the first resin insulation layer faces the first conductor layer, and a second conductor layer 58 including a plurality of conductor circuits and via lands is formed on the first surface of the first resin insulation layer.

The first conductor layer and the second conductor layer are connected by a first via conductor 59A that penetrates the first resin insulating layer. The second conductor layer and the electrode of the electronic component are connected by a connection via conductor 59B that penetrates the first resin insulating layer. A second resin insulation layer is formed on the first surface of the first resin insulation layer and the second conductor layer. The first surface of the first resin insulation layer and the second surface of the second resin insulation layer are opposed to each other.
A third conductor layer is formed on the first surface of the second resin insulation layer, and the third conductor layer includes a plurality of conductor circuits and via lands. The second conductor layer and the third conductor layer are connected by a second via conductor 69 penetrating the second resin insulating layer. A solder resist layer 80 is formed on the first surface of the second resin insulation layer and the third conductor layer. The solder resist layer has an opening 80a, and a solder bump 86U is formed on the second via conductor or the third conductor layer exposed through the opening 80a.

In the first embodiment, a die attach 44 made of silver paste or the like is formed on the back surface (back surface) of the IC chip 90. Die attach is not essential, and the back surface of the IC chip may be exposed to the outside. Heat dissipation is further improved by exposing the die attach.

In FIG. 8, the printed wiring board of FIG. 7 is inverted. The pads 102 of the package substrate 100 are connected to the solder bumps 86D of the printed wiring board 1000. A memory 104 is mounted on the package substrate 100, and the memory and the package substrate 100 are connected by a wire 106. On the other hand, the printed wiring board is connected to the pads 202 of the motherboard 200 via the solder bumps 86U of the printed wiring board 1000.

As shown in FIG. 7, the first resin insulation layer 50 contains an IC chip, and the second resin insulation layer 60 does not contain an IC chip. For this reason, when the temperature of a printed wiring board changes, it is thought that the amount of expansion and contraction differs between the first resin insulating layer and the second resin insulating layer. Further, it is considered that the amount of shrinkage differs between the first resin insulating layer and the second resin insulating layer due to curing. Therefore, it is considered that the printed wiring board 10 is likely to warp or swell. However, in Embodiment 1, the thickness (d1) of the second conductor layer is thicker than the thickness (d2) of the third conductor layer. Since the conductor layer is more rigid than the resin insulating layer, it is considered that warping and undulation of the printed wiring board can be prevented by increasing the thickness of the second conductor layer. The third conductor layer is thinner than the second conductor layer. If the third conductor layer is thick like the second conductor layer, it is difficult to form fine wiring on the third conductor layer. Therefore, a printed wiring board that should be formed of two resin insulating layers is formed of three resin insulating layers. As a result, it is considered that the amount of shrinkage due to curing increases, and warping and undulation of the printed wiring board increase. In the first embodiment, the second conductor layer is present between the first resin insulating layer containing the electronic component and the second resin insulating layer not containing the electronic component. When the expansion / contraction amount is compared between adjacent resin insulation layers, the difference in expansion / contraction amount due to temperature change and the difference in shrinkage amount due to curing between the first resin insulation layer and the second resin insulation layer is greatest depending on the presence or absence of electronic components Conceivable. Therefore, it is considered that a large stress acts on the interface between the first resin insulation layer and the second resin insulation layer. It is considered that the printed wiring board is warped or undulated starting from the interface between the first resin insulating layer and the second resin insulating layer. In order to effectively prevent the warpage and waviness, in Embodiment 1, a thick conductor layer is formed between the first resin insulating layer and the second resin insulating layer. The thickness of the third conductor layer is smaller than the thickness of the second conductor layer in order to reduce the stress applied to the interface between the first resin insulation layer and the second resin insulation layer.

Further, the warpage amount is considered to increase as the distance from the built-in electronic component increases. For this reason, in order to suppress the warpage generated by incorporating the electronic component with the predetermined conductor layer, it is considered that the conductor layer farther from the electronic component needs to be thicker. However, in Embodiment 1, the thickness of the second conductor layer on the first resin insulation layer containing the electronic component is thicker than the thickness of the third conductor layer. Therefore, the printed wiring board of Embodiment 1 can efficiently suppress warpage and undulation.

The thickness (d1) of the second conductor layer 58 / the thickness (d2) of the third conductor layer 68 is desirably 1.2 to 5. The thickness d1 of the second conductor layer 58 is 10 μm to 125 μm, and the thickness d2 of the third conductor layer 68 is 7 μm to 30 μm.

The thickness d4 of the first conductor layer 42 is 10 μm to 75 μm. The thickness of the first conductor layer is not less than the thickness of the third conductor layer and not more than the thickness of the second conductor layer. The thickness (d1) of the second conductor layer 58 / the thickness (d4) of the first conductor layer 68 is 1 to 3, and the thickness of the first conductor layer (d4) / the thickness of the third conductor layer (d2). Is preferably 1-2. The warpage and undulation of the printed wiring board are reduced. Alternatively, the number of resin insulating layers can be reduced.

The first conductor layer is preferably thicker than the third conductor layer and thinner than the second conductor layer. The thickness of the first conductor layer / the thickness of the third conductor layer is preferably 1.1 to 1.5, and the thickness of the second conductor layer / the thickness of the first conductor layer is 1.5 to 3. desirable. Within this range, fine conductor circuits can be formed in the first conductor layer and the third conductor layer. Therefore, since the number of resin insulation layers is reduced, the amount of warpage of the printed wiring board is reduced. The thickness of the second conductor layer does not become larger than necessary. The warpage of the printed wiring board is effectively reduced. Therefore, a signal line can be formed also in the second conductor layer. The number of resin insulation layers is reduced. Therefore, a thin printed wiring board with a small amount of warpage can be obtained.

The thickness (d4) of the first conductor layer is equivalent to the thickness (d1) of the second conductor layer, and is preferably thicker than the thickness (d2) of the third conductor layer. The thickness of the first conductor layer / the thickness of the third conductor layer is preferably 1.2-3. By providing the thick second conductor layer 58 and the first conductor layer 42 on both surfaces of the first resin insulation layer, warpage of the first resin insulation layer can be suppressed.

The first conductor layer 42 includes external terminals for connecting to other substrates and electronic components. The first conductor layer is recessed at the same level as the second surface of the first resin insulation layer 50 or from the second surface. It is desirable to dent. When the IC chip is built in the second surface side of the first resin insulation layer so that the back surface of the IC chip faces the second surface of the first resin insulation layer, the first resin insulation layer on the second surface side is the first resin insulation layer. It is thought that the first resin insulation layer on the surface side is affected by the IC chip. However, in the first embodiment, since the first conductor layer 42 is recessed from the second surface of the first resin insulation layer 50 and is formed in the first resin insulation layer, the first resin insulation on the second surface side. The layer is believed to be reinforced with a first conductor layer. Therefore, it is considered that the stress generated by embedding the IC chip in the first resin insulation layer is alleviated by embedding the first conductor layer on the second surface side of the first resin insulation layer. Cracks are unlikely to occur in the first resin insulation layer.

The thickness (f1) of the first resin insulating layer 50 is 55 μm to 190 μm, and is about 15 to 40 μm thicker than the thickness of the electronic component 90. The first resin insulation layer may be formed of a plurality of resin insulation layers 50A and 50B (FIG. 10). In FIG. 10, the first resin insulation layer is formed of two resin insulation layers. The first via conductor passes through the two resin insulating layers. In this case, the first resin insulation layer includes each resin insulation layer containing an electronic component. It is preferable that the thickness of each resin insulation layer is substantially the same. The thickness (f2) of the second resin insulation layer 60 is 20 μm to 50 μm. The thickness of the second resin insulation layer is preferably thinner than the thickness of the first resin insulation layer. Since shrinkage due to curing is reduced, the amount of warping and waviness of the printed wiring board is reduced.

The bottom diameter e1 of the first via conductor 59A is 30 μm to 120 μm, and the top diameter e2 is 30 μm to 200 μm. The bottom diameter e5 of the second via conductor 69 is 30 μm to 80 μm, and the top diameter e6 is 30 μm to 100 μm. The bottom diameter e3 of the connection via conductor 59B is 30 μm to 80 μm, and the top diameter e4 is 30 μm to 100 μm. As shown in FIG. 7, the bottom diameter is the diameter of the conductor layer, via conductor, and via conductor opening on the electrode of the electronic component, and the top diameter is the via conductor opening on the first surface of the resin insulating layer. (See FIG. 11).

The top diameter of the first via conductor 59 </ b> A is preferably larger than the top diameter of the second via conductor 69. The volume of the via conductor in the first resin insulating layer containing the electronic component is increased. Thereby, since the rigidity of the 1st resin insulation layer becomes high, a printed wiring board becomes difficult to warp. The top diameter of the first via conductor / the top diameter of the second via conductor is desirably 1.05 to 4.

It is desirable that the top diameter of the connection via conductor 59B is also larger than the top diameter of the second conductor. The top diameter of the connection via conductor / the top diameter of the second via conductor is preferably 1.05 to 3. Furthermore, the rigidity of the first resin insulating layer is increased. In addition, a small via conductor can be formed in the second resin insulating layer. Therefore, the number of via conductors that can be formed in the second resin insulation layer increases. Moreover, since the via land formed in the second conductor layer is reduced, the number of resin insulating layers is reduced. As a result, a thin printed wiring board with a small amount of warpage can be obtained. The top diameter of the connection via conductor is equal to or smaller than the top diameter of the first via conductor. When the top diameter of the connection via conductor is smaller than the top diameter of the first via conductor, an IC chip having a large number of electrodes can be incorporated.

With reference to FIGS. 1-8, the manufacturing method of the printed wiring board of Embodiment 1 is demonstrated below.
A double-sided copper clad laminate 30 having a thickness of 0.2 to 0.8 mm and a copper foil 40 having a thickness of 5 to 100 μm are prepared (FIG. 1A).

The copper foil 40 is joined to the double-sided copper clad laminate 30 by an adhesive or ultrasonic connection (FIG. 1 (B)). A plating resist having a predetermined pattern is formed on the copper foil, and a nickel film 42N is formed on the plating resist non-formed portion by electrolytic plating. The thickness of the nickel film is 5 μm. A gold film 42A and a nickel film 420N are formed on the nickel film by electrolytic plating. The first conductor layer 42 is formed on the nickel film 420N by electrolytic copper plating. The thickness of the first conductor layer is 10 to 75 μm. The plating resist is removed (FIG. 1C). A die attach 44 is formed by a conductive paste such as an Au-Sn paste at the IC chip attachment position of the copper foil 40 (FIG. 1D).

An electronic component 90 such as an IC chip is mounted on the die attach 44 (FIG. 2A). In the first embodiment, the back surface of the IC chip is bonded to the die attach. The thickness (T) of the electronic component is 40 to 150 μm. The die attach is cured by heat treatment. A B-stage resin film containing inorganic particles such as silica and an epoxy resin is laminated on the electronic component 90 and the first conductor layer. The thickness of the resin film is about 15 to 40 μm thicker than the thickness (T) of the electronic component. Thereafter, the resin film is cured by heat treatment. A first resin insulation layer is formed on the copper foil and the first conductor layer. The electronic component is accommodated in the first resin insulating layer (FIG. 2B). The thickness of the first resin insulation layer is 55 to 190 μm, which is about 15 to 40 μm thicker than the thickness of the electronic component. The distance (L) from the upper surface of the electrode of the electronic component to the first surface of the first resin insulation layer is 15 to 40 μm. An opening 50a for forming the first via conductor and an opening 50b for forming the connection via conductor are formed in the first resin insulating layer 50 with a laser (FIG. 2C). The top diameter (e2) of the opening 50a and the top diameter (e4) of the opening 50b are different, and e2 is preferably larger than e4. It is preferable that e2 / e4 is 1.1-2. Since the first via conductor is thickened, the first resin insulating layer in the portion where the electronic component is not incorporated is reinforced with the first via conductor. Warping and undulation of the printed wiring board can be suppressed.
An electroless plating film 51 is formed on the surface of the first resin insulating layer 50 by the electroless plating process (FIG. 2D).

A plating resist 54 having a predetermined pattern is formed on the electrolytic plating film 51 (FIG. 3A). Through the electrolytic plating treatment, the openings 50a and 50b are filled with plating, and an electrolytic plating film 56 is formed in the portion where the plating resist is not formed (FIG. 3B). The plating resist 54 is removed, and the electroless plating film 51 between the electrolytic plating films 56 is removed. The second conductor layer 58, the first via conductor 59A, and the connection via conductor 59B are completed (FIG. 3C).
A second resin insulation layer 60 is formed on the second conductor layer and the first resin insulation layer (FIG. 3D). The thickness of the second resin insulation layer is preferably 25 to 45 μm. The second resin insulating layer includes inorganic particles such as silica and an epoxy resin. Furthermore, the second resin insulating layer may include a reinforcing material such as glass cloth.

An opening 60a for forming a second via conductor is formed in the second resin insulating layer 60 with a laser (FIG. 4A). The top diameter of the second via conductor is preferably smaller than the top diameter of the first via conductor or the connection via conductor. The number of resin insulation layers is reduced. An electroless plating film 61 is formed on the surface of the second resin insulating layer 60 by the electroless plating process (FIG. 4B). A plating resist 64 having a predetermined pattern is formed on the electroless plating film 61 (FIG. 4C).

Through the electrolytic plating process, the opening 60a is filled with plating, and an electrolytic plating film 66 is formed in the portion where the plating resist is not formed (FIG. 5A). The plating resist 64 is removed, and the electroless plating film 61 between the electrolytic plating films 66 is removed. The third conductor layer 68 and the second via conductor 69 are completed (FIG. 5B). The thickness of the third conductor layer is thinner than the thickness of the second conductor layer. Further, the thickness of the third conductor layer is preferably thinner than the thickness of the first conductor layer.

A solder resist layer 80 having an opening 80a is formed on the second resin insulating layer and the third conductor layer (FIG. 6A). The double-sided copper-clad laminate 30 and the copper foil 40 are separated (FIG. 6B). The copper foil 40 is removed by etching with a selective etchant (FIG. 6C). As the etchant, for example, an etchant disclosed in JP-A-2005-105411 is used.
Subsequently, the nickel film 42N on the external terminal 42 is removed by etching with a selective etchant. The gold film on the external terminal is exposed. The printed wiring board 10 is completed. As an etchant, for example, Nickel selective etchant-NC manufactured by Nippon Chemical Industry Co., Ltd. is used.

A solder bump 86U is formed on the third conductor layer or the second via conductor exposed through the opening 80a of the solder resist layer 80, and a solder bump 86D is formed on the first conductor layer. A printed wiring board 1000 having solder bumps is completed (FIG. 7). Then, the package substrate 100 is mounted on the printed wiring board 10 via the solder bumps 86D, and the printed wiring board 1000 is mounted on the daughter board 200 via the solder bumps 86U (FIG. 8).

[Embodiment 2]
In Embodiment 1, the number of resin insulation layers is two. However, the number of layers is not limited to two.
The third resin insulation layer 70, the third via conductor 79, and the fourth conductor layer 78 are formed on the second resin insulation layer and the third conductor layer by the same process as that shown in FIGS. Can be formed. The thickness of the third resin insulation layer is the same as the thickness of the second resin insulation layer. The sizes of the top diameter and the bottom diameter of the opening for the third via conductor are the same as the sizes of the top diameter and the bottom diameter of the opening for the second via conductor. The thickness of the fourth conductor layer is the same as the thickness of the third conductor layer, and the relationship of the thickness of the second conductor layer / the thickness of the fourth conductor layer is the relationship of the thickness of the second conductor layer / the thickness of the third conductor layer. It is the same. The relationship of the thickness of the first conductor layer / the thickness of the fourth conductor layer is the same as the relationship of the thickness of the first conductor layer / the thickness of the third conductor layer.

Similar to FIG. 6A, a solder resist layer is formed on the third resin insulating layer and the fourth conductor layer. Thereafter, a printed wiring board having solder bumps is manufactured in the same process as in the first embodiment (FIG. 9).

[Example]
With reference to FIGS. 1-6, the manufacturing method of the printed wiring board of an Example is demonstrated below.
A double-sided copper clad laminate 30 having a thickness of 0.8 mm and a copper foil 40 having a thickness of 5 μm are prepared (FIG. 1A).

The copper foil 40 is joined to the double-sided copper clad laminate 30 by ultrasonic waves (FIG. 1B). A plating resist having a predetermined pattern is formed on the copper foil, and a nickel film 42N is formed on the plating resist non-formed portion by electrolytic plating. The thickness of the nickel film is 5 μm. A gold film 42A and a nickel film 420N are formed on the nickel film by electrolytic plating. The first conductor layer 42 is formed on the nickel film 420N by electrolytic copper plating. The thickness of the first conductor layer is 15 μm. The plating resist is removed (FIG. 1C). The die attach 44 is formed by the Au-Sn paste at the IC chip attachment position of the copper foil 40 (FIG. 1D).

An IC chip 90 is mounted on the die attach 44 (FIG. 2A). The back surface of the IC chip is bonded to the die attach. The thickness (T) of the electronic component is 100 μm. The die attach is cured by heat treatment. A B-stage resin film containing silica particles and an epoxy resin is laminated on the electronic component 90 and the first conductor layer. Thereafter, the resin film is cured by heat treatment. A first resin insulation layer is formed on the copper foil and the first conductor layer. An IC chip is incorporated (FIG. 2B). The thickness of the first resin insulation layer is 140 μm. An opening 50a for forming the first via conductor and an opening 50b for forming the connection via conductor are formed in the first resin insulating layer 50 with a laser (FIG. 2C). The top diameter (e2) of the opening 50a is 120 μm, and the top diameter (e4) of the opening 50b is 60 μm. Both bottom diameters (e1, e3) are 45 μm.
An electroless copper plating film 51 is formed on the surface of the first resin insulation layer 50 by the electroless copper plating process (FIG. 2D).

A plating resist 54 having a predetermined pattern is formed on the electroless copper plating film 51 (FIG. 3A). Through the electrolytic copper plating treatment, the openings 50a and 50b are filled with copper plating, and an electrolytic copper plating film 56 is formed in the plating resist non-forming portion (FIG. 3B). The plating resist 54 is removed, and the electroless copper plating film 51 between the electrolytic copper plating films 56 is removed. The second conductor layer 58, the first via conductor 59A, and the connection via conductor 59B are completed (FIG. 3C). The thickness of the second conductor layer is 30 μm.
A second resin insulation layer 60 is formed on the second conductor layer and the first resin insulation layer. (FIG. 3D). The thickness of the second resin insulation layer is 35 μm. The second resin insulation layer includes silica particles, epoxy resin, and glass cloth.

An opening 60a for forming a second via conductor is formed in the second resin insulating layer 60 with a laser (FIG. 4A). The top diameter of the opening 60a is 50 μm, and the bottom diameter is 45 μm. An electroless copper plating film 61 is formed on the surface of the second resin insulating layer 60 by the electroless copper plating process (FIG. 4B). A plating resist 64 having a predetermined pattern is formed on the electroless copper plating film 61 (FIG. 4C).

By the electrolytic copper plating treatment, the opening 60a is filled with copper plating, and an electrolytic copper plating film 66 is formed in the portion where the plating resist is not formed (FIG. 5A). The plating resist 64 is removed, and the electroless copper plating film 61 between the electrolytic copper plating films 66 is removed. The third conductor layer 68 and the second via conductor 69 are completed (FIG. 5B). The thickness of the third conductor layer is 12 μm.

A solder resist layer 80 having an opening 80a is formed on the second resin insulating layer and the third conductor layer (FIG. 6A). The double-sided copper-clad laminate 30 and the copper foil 40 are separated (FIG. 6B). The copper foil 40 is removed with an etching solution disclosed in JP-A-2005-105411. Subsequently, the nickel film 42N on the external terminal is removed by etching with a selective etching solution. The gold film on the external terminal is exposed. As an etchant, for example, Nickel selective etchant-NC manufactured by Nippon Chemical Industry Co., Ltd. is used. The printed wiring board 10 is completed (FIG. 6C).

DESCRIPTION OF SYMBOLS 10 Printed wiring board 50 1st resin insulation layer 58 2nd conductor layer 59A 1st via conductor 60 2nd resin insulation layer 68 3rd conductor layer 69 2nd via conductor 70 3rd resin insulation layer 78 3rd conductor layer 79 3rd Via conductor 90 Electronic parts

Claims (14)

A first conductor layer;
A first resin having a first surface and a second surface opposite to the first surface, the second surface being laminated on the first conductor layer so as to face the first conductor layer An insulating layer;
An electronic component housed in the first resin insulation layer and having an electrode;
A second conductor layer formed on the first surface of the first resin insulation layer;
A first via conductor passing through the first resin insulation layer and connecting the first conductor layer and the second conductor layer;
A connection via conductor formed in the first resin insulation layer and connecting the electrode of the electronic component and the second conductor layer;
The second conductor layer and the first surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the first resin insulation layer. A second resin insulation layer laminated on the resin insulation layer;
A third conductor layer formed on the first surface of the second resin insulation layer;
A printed wiring board having a second via conductor penetrating the second resin insulation layer and connecting the second conductor layer and the third conductor layer;
The second conductor layer is thicker than the third conductor layer. In the printed wiring board of Claim 1,
The first resin insulation layer is thicker than the second resin insulation layer. In the printed wiring board of Claim 2,
The diameter (top diameter) of the first via conductor on the first surface of the first resin insulation layer is larger than the diameter (top diameter) of the second via conductor on the first surface of the second resin insulation layer. In the printed wiring board of Claim 1,
The diameter (bottom diameter) of the first via conductor on the first conductor layer is smaller than the diameter (bottom diameter) of the connection via conductor on the electrode of the electronic component. The printed wiring board of claim 1:
A value obtained by dividing the thickness of the second conductor layer by the thickness of the third conductor layer is 1.2 to 5. The printed wiring board of claim 3:
A value obtained by dividing the top diameter of the first via conductor by the top diameter of the second via conductor is 1.05-4. In the printed wiring board of Claim 1,
Further, the third conductor layer and the second surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the second resin insulation layer. A third resin insulation layer laminated on the second resin insulation layer, a fourth conductor layer formed on the first surface of the third resin insulation layer, and the third resin insulation layer; A third via conductor connecting the third conductor layer and the fourth conductor layer, and the fourth conductor layer and the third conductor layer are substantially equal in thickness. In the printed wiring board of Claim 7,
The thickness of the second resin insulation layer and the thickness of the third resin insulation layer are substantially equal. In the printed wiring board of Claim 5,
Further, the third conductor layer and the second surface have a first surface and a second surface opposite to the first surface, and the second surface faces the first surface of the second resin insulation layer. A third resin insulation layer laminated on the second resin insulation layer, a fourth conductor layer formed on the first surface of the third resin insulation layer, and the third resin insulation layer; A third via conductor connecting the third conductor layer and the fourth conductor layer, wherein the thickness of the fourth conductor layer is substantially equal to the thickness of the third conductor layer; The thickness and the thickness of the third resin insulating layer are substantially equal. 2. The printed wiring board according to claim 1, wherein the first resin insulating layer does not have a reinforcing material. The printed wiring board according to claim 10, wherein the reinforcing material is formed of fibers. 2. The printed wiring board according to claim 1, wherein the first resin insulation layer is an outermost resin insulation layer. 13. The printed wiring board according to claim 12, wherein a solder resist layer is formed on the first surface of the second resin insulation layer. The printed wiring board according to claim 10, wherein the second resin insulating layer has a reinforcing material.

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