JP5660359B2 - Power factor correction circuit - Google Patents

Description

  The present invention relates to standby power reduction of a power factor correction circuit in high frequency regulation.

  FIG. 9 is a circuit diagram showing an AC-DC converter including a conventional power factor correction circuit. The AC-DC converter shown in FIG. 9 includes a rectifier DB that rectifies an AC input voltage from an AC power supply and outputs a rectified voltage, a boost chopper circuit 26 that boosts the rectified voltage from the rectifier DB, and a boost chopper circuit 26. It has a DC-DC converter circuit 27 that converts the boosted voltage into a stabilized DC voltage and supplies it to a load. The AC-DC converter is further provided with a control circuit 23 for controlling them.

The rectifier circuit DB rectifies the AC voltage from the AC power source Vin and sends it to the power factor correction converter 26. The power factor improving converter 26 improves the power factor of the AC voltage including the pulsating flow, converts it to a DC voltage having a voltage value higher than the input AC voltage, and sends the DC voltage to the DC-DC converter 27. The DC-DC converter 27 boosts the DC voltage from the power factor correction converter 26 and outputs it as a DC voltage.

The control circuit 23 includes a DC / DC unit control circuit 20a for controlling the DC-DC converter 27, a PFC unit control circuit 10a for controlling the power factor correction converter 26, a PFC on / off switching circuit 24, and a load state determination circuit. 25.
The DC / DC unit control circuit 20a outputs the pulse width of the pulse signal VG for driving the second switching element Q2 based on the detection result of the output voltage detection circuit 31 provided at the output terminal of the DC-DC converter 27. Control is performed so that the pulse width is narrowed as the load becomes light while keeping the voltage constant.
The load state determination circuit 25 includes an on period comparison circuit 21 and a reference period output circuit 22.
The reference period output circuit 22 includes a changeover switch 22a, a first reference period generation circuit 22b, and a second reference time generation circuit 22c. The first reference period generation circuit 22b generates a pulse signal V1 having a first reference on period. The second reference time generation circuit 22c generates a pulse signal V2 having a second reference on period shorter than the first reference on period. The change-over switch 22a selects either the pulse signal V1 from the first reference period generation circuit 22b or the pulse signal V2 from the second reference time generation circuit 22c according to the signal V4 from the ON period comparison circuit 21. Then, it is supplied to the ON period comparison circuit 21 as a pulse signal V3.
The on-period comparison circuit 21 includes an on-period and a reference period of the pulse signal VG supplied from the DC / DC unit control circuit 20a to the gate terminal of the second switching element Q2 formed of a MOS transistor in the DC-DC converter 27. The ON period of the pulse signal V3 from the output circuit 22 is compared. A signal V4 representing the result of comparison by the on period comparison circuit 21 is supplied to the PFC on / off switching circuit 24 and also to the changeover switch 22a of the reference period output circuit 22.
In the PFC on / off switching circuit 24, the on period comparison circuit 21 compares the second reference on period of the pulse signal V2 output from the reference period output circuit 22 with the on period of the pulse signal VG, and turns on the pulse signal VG. When the signal V4 indicating that the period is equal to or shorter than the second reference ON period is output, the operation of the PFC unit control circuit 10a is stopped, thereby stopping the ON / OFF operation of the first switching element Q1.
In the PFC on / off switching circuit 24, the on period comparison circuit 21 compares the first reference on period of the pulse signal V1 output from the reference period output circuit 22 with the on period of the pulse signal VG, and the pulse signal VG. When the signal V4 indicating that the ON period is equal to or longer than the first reference ON period is output, the PFC unit control circuit 10a is activated, thereby switching the first switching element Q1.

That is, since the pulse width of the pulse signal VG becomes narrower as the output load becomes lighter, the load state of the output is compared with the reference ON period of the pulse signals V1 to V2 output from the reference period output circuit 22 And the power factor correction circuit can be turned on and off.

As described above, since the power factor correction circuit is stopped at the time of light load and the current of the circuit to be controlled is reduced, the power supply efficiency at the time of light load is improved.
Japanese Patent No. 3741035

As described above, in the conventional AC-DC converter, the power factor correction circuit is stopped at the time of light load to suppress power consumption. However, the power factor correction circuit detects the rectified voltage obtained by rectifying the AC input voltage from the AC power supply, although it is not shown in the figure, the detection voltage is detected at a low voltage by a voltage dividing resistor. Even if the operation is stopped, the power consumption of the input voltage detection circuit composed of resistors is generated.
That is, the suppression of power consumption at the time of no load is insufficient, and an extra power consumption of several tens mW to 100 mW is caused by the AC input voltage.

  An object of the present invention is to provide a power factor improving circuit that is adapted to the new standard LEVEL V of “ENAGY STAR”, improves the power factor, is inexpensive, and further suppresses standby power.

In order to solve the above-mentioned problem, the invention of claim 1 boosts a rectified voltage obtained by rectifying an AC input voltage from an AC power supply by turning on / off the first switching element and improves the power factor to increase the output voltage. Is output to a DC-DC converter circuit driven by the first pulse signal,
When the first pulse signal having a pulse width corresponding to the output voltage of the DC-DC converter circuit is input and an ON pulse of the first pulse signal is generated, a delayed pulse signal having a pulse width corresponding to the rectified voltage is generated. It raises a delay circuit for generating a second pulse signal by combining the first pulse signal and before Kioso extension pulse signal,
The delay circuit widens the pulse width of the delayed pulse signal as the rectified voltage increases, and narrows the pulse width of the delayed pulse signal as the rectified voltage decreases.
A switch driving circuit for driving the first switching element by the second pulse signal generated by the delay circuit;
The delay circuit has a voltage detection circuit for detecting the rectified voltage for generating a delayed pulse signal having a pulse width corresponding to the rectified voltage,
It has a circuit which isolate | separates the said voltage detection circuit from GND when the pulse width of the said 2nd pulse signal produced | generated by the said delay circuit is zero.

  According to the present invention, the delay circuit generates a delayed pulse signal having a pulse width corresponding to the rectified voltage, and synthesizes the first pulse signal obtained from the DC-DC converter and the delayed pulse signal. Since the second pulse signal is generated, the second pulse signal is an on-pulse signal having a pulse width changed according to a voltage obtained by rectifying the alternating current. That is, since the switching element and the switching element can be driven on and off by a pulse signal whose pulse width has changed in accordance with the voltage obtained by rectifying the alternating current, the power factor can be improved by conforming to the new standard LEVEL V of “ENAGY STAR”, and at a low cost. In addition, it is possible to provide a power factor correction circuit that further suppresses standby power.

  Hereinafter, embodiments of the power factor correction circuit of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing an AC-DC converter including a power factor correction circuit according to an embodiment. The AC-DC converter shown in FIG. 1 includes a rectifier DB that rectifies an AC input voltage from an AC power supply Vin and outputs a rectified voltage, a smoothing capacitor C1 connected to the output terminal of the rectifier DB, and a rectified voltage of the rectifier DB. A power factor improving circuit (PFC) 2 that boosts the power factor and improves the power factor, and a DC-DC converter circuit 3 that converts the voltage boosted by the power factor improving circuit 2 into a stabilized DC voltage and supplies the stabilized DC voltage to the load, have.

  In the DC-DC converter circuit 3, a series circuit of a primary winding P1 of a transformer T1 and a switching element Q2 composed of a MOSFET is connected to both ends of a capacitor C2 of the power factor correction circuit 2. A series circuit of a diode Ds and a capacitor Cs is connected to both ends of the secondary winding S1 of the transformer T1, and a voltage detection amplifier circuit (VAMP) 30 for detecting the output voltage of the capacitor Cs is connected to both ends of the capacitor Cs. ing. A photocoupler PC1 is connected to the voltage detection amplifier circuit 30, and the photocoupler PC1 outputs a current corresponding to the output voltage detected by the voltage detection amplifier circuit 30 to the DD control circuit 20.

  A series circuit of a diode D2 and a capacitor C3 is connected to both ends of the auxiliary winding P2 of the transformer T1, and a connection point between the diode D2 and the capacitor C3 is a resistance for starting the DD control circuit 20 and the DD control circuit 20. It is connected to one end of R3.

  The DD control circuit 20 generates a pulse signal having a pulse width corresponding to the output voltage from the photocoupler PC1, and controls the output voltage to a predetermined voltage by controlling the on / off of the switching element Q2 with this pulse signal.

  Next, the power factor correction circuit 2 will be described. The power factor correction circuit 2 constitutes a step-up chopper circuit, and a series circuit of a step-up reactor L1 and a switching element Q1 composed of a MOSFET is connected to both ends of the smoothing capacitor. A series circuit of a diode D1 and a capacitor C2 is connected between the drain and source of the switching element Q1.

  A series circuit of a resistor R1, a resistor R2, and a switch element Q10 composed of a MOSFET is connected to both ends of the output of the rectifier DB, and a connection point between the resistor R1 and the resistor R2 is connected to the PFC control circuit 10. The PFC control circuit 10 receives a gate pulse signal (hereinafter abbreviated as a pulse signal) of the switching element Q2 made of a MOSFET from the DD control circuit 20 of the DC-DC converter circuit 3, and the gate and gate of the switching element Q1. Applied to the ON / OFF circuit 13. The PFC control circuit 10 improves the power factor by turning on / off the switching element Q1 based on the pulse signal of the switching element Q2 and the voltage obtained by dividing the rectified voltage of the rectifier DB by the resistors R1 and R2. Further, the switch element Q10 is turned on via the gate ON / OFF circuit 13 by the pulse signal of the PFC control circuit 10.

  FIG. 2 is a detailed diagram of a PFC control circuit diagram in the power factor correction circuit of the embodiment. In FIG. 2, the detection unit 11 including a resistor R1 and a resistor R2 detects a rectified voltage obtained by rectifying an AC input voltage via the switch element Q10, and outputs the detected rectified voltage to the cathode of the diode D3. .

  The PFC control circuit 10 receives the pulse signal (first pulse signal) from the DD control circuit 20 and has a pulse width corresponding to a rectified voltage obtained by rectifying the AC input voltage when an ON pulse of the pulse signal is generated. A delay circuit 12 that generates a signal and generates a PFC gate signal (second pulse signal) by synthesizing the pulse signal and the delayed pulse signal, and drive circuits Q3 and Q4 that drive the switching element Q1 by the PFC gate signal , R6 and overcurrent protection circuits R4, R5, C4, Q5, R7, R8, Q6, D4 for limiting the current flowing through the switching element Q1.

  In the delay circuit 12, a series circuit of a capacitor C5 and a resistor R13 is connected between the gate side terminal of the switching element Q2 of the DD control circuit 20 and the negative terminal of the rectifier DB, and a resistor R11 and a resistor R12 are connected. Are connected in series.

  The base of the transistor Q8 is connected to the connection point between the resistors R11 and R12, and the emitter of the transistor Q8 is connected to the connection point between the capacitor C5 and the resistor R13. The gate side terminal of the DD control circuit 20 is connected to the emitter of the transistor Q7, and the base of the transistor Q7 is connected to the anode of the diode D3 and the collector of the transistor Q8 via the resistor R10. The cathode of the diode D3 is connected to the connection point between the resistor R1 and the resistor R2.

  The collector of the transistor Q7 is connected to the base of the transistor Q3, the base of the transistor Q4, and the anode of the diode D4 via the resistor R9. The cathode of the diode D4 is connected to the collector of the transistor Q5 and one end of the resistor R8. The emitter of the transistor Q5 is connected to the negative terminal of the rectifier DB, and the base of the transistor Q5 is connected to one end of the resistor R5, one end of the resistor R7, and one end of the capacitor C4.

  In the drive circuit, the collector of the transistor Q3 is connected to the gate side terminal of the DD control circuit 20, the emitter of the transistor Q3 is connected to the emitter of the transistor Q4 and one end of the resistor R6, and the other end of the resistor R6 is the switching element Q1. And the anode of the diode D5 of the gate ON / OFF circuit 13 are connected. The collector of the transistor Q4 is connected to the negative terminal of the rectifier DB.

In the gate ON / OFF circuit 13, the cathode of the diode D5 is connected to the capacitor C6, the resistor R15, and the gate of the switch element Q10. One end of the capacitor C6 and the resistor R15 and the source of the switch element Q10 are connected to the negative terminal of the rectifier DB.

  Next, the operation of the PFC control circuit 10 configured as described above and shown in FIG. 2 will be described with reference to FIGS. FIG. 3 shows a rectified divided signal obtained by rectifying the AC input voltage. FIG. 4 is a timing chart of each signal in the delay circuit near the top A of the divided voltage signal after rectification at the rated load. FIG. 5 is a timing chart of each signal in the delay circuit near the bottom B of the divided voltage signal after rectification at the rated load.

  The delay circuit 12 receives the pulse signal from the DD control circuit 20 and, when an on-pulse of the pulse signal is generated, the pulse width corresponding to the voltage value of the collector voltage signal of the transistor Q8 based on the rectified voltage obtained by rectifying the AC input voltage Is generated, and the PFC gate signal is generated by combining the pulse signal and the delayed pulse signal. The PFC gate signal has a pulse width that is narrower by the pulse width of the delayed pulse signal than the pulse width of the pulse signal.

  The delay circuit 12 widens the pulse width of the delayed pulse signal as the rectified voltage increases, makes the PFC gate signal a pulse width narrower than the pulse width of the pulse signal, narrows the pulse width of the delayed pulse signal as the rectified voltage decreases, When the rectified voltage reaches the bottom region, the pulse width of the delayed pulse signal is made zero.

  First, the operation of the delay circuit 12 near the top A of the divided voltage signal after rectification will be described with reference to FIG. Based on the point c voltage (pulse divided signal c) obtained by dividing the pulse signal a from the DD control circuit 20 by the resistors R11 and R12, the point b voltage (differentiating circuit) of the differentiating circuit by the capacitor C5 and the resistor R13. When the difference voltage between the signal b) and the voltage at point c reaches the base-emitter voltage Vbe of the transistor Q8, the transistor Q8 is turned on.

  In addition, since the rectified voltage at the connection point between the resistor R1 and the resistor R2 near the top A of the divided voltage signal f after rectification is higher than the potential at the point e, the diode D3 is off.

For this reason, the differentiation circuit signal b, which is the voltage at the point b of the differentiation circuit by the capacitor C5 and the resistor R13, starts from the time t1 when the pulse signal a from the DD control circuit 20 is turned on, as shown in FIG. The PFC gate signal d is output from time t2 which decreases with the elapsed time and becomes lower by the base-emitter voltage Vbe of the transistor Q8 than the pulse divided signal c which is the potential at the point c. The transistor Q3 is turned on by the PFC gate signal d, and the switching element Q1 is turned on.
At the same time, the parallel circuit of the capacitor C6 and the resistor R15 is charged with the PFC gate signal d via the diode D5 of the gate ON / OFF circuit 13. The gate ON / OFF circuit 13 generates a gate ON / OFF circuit signal g that is a gate voltage of the switch element Q10, and
Switch element Q10 is turned on. Here, it is desirable to set the discharge time constant of the capacitor C6 and the resistor R15 to a value longer than the period of the AC input voltage frequency. In order to suppress the drive loss of the PFC gate signal d, it is desirable to set the resistor R15 to a high resistance.

  Next, when the pulse signal a from the DD control circuit 20 becomes zero, a current flows through the path of the gate of the switching element Q1, the emitter and base of the transistor Q4, and the base and collector of the transistor Q3. As a result, since the transistor Q4 is turned on, the gate voltage of the switching element Q1 becomes zero, and the switching element Q1 is turned off.

  As described above, when the rectified voltage at the connection point f between the resistor R1 and the resistor R2 is high, the delay circuit 12 has the PFC gate signal d with a delay time fixed by the time constant between the capacitor C5 and the resistor R13. Is output. The gate ON / OFF circuit 13 rectifies and smoothes the PFC gate signal d to drive the gate of the switch element Q10.

  Next, the operation of the delay circuit 12 near the bottom B of the rectified divided signal f will be described with reference to FIG. The voltage waveform of the collector voltage signal e 'of the transistor Q8 in FIG. 5 is a value close to zero volts.

  When the rectified voltage at the connection point f between the resistor R1 and the resistor R2 becomes equal to or lower than the voltage obtained by subtracting the base-emitter voltage Vbe of the transistor Q7 and the forward voltage of the diode D3 from the pulse signal a voltage of the DD control circuit 20. A current flows through the path of the pulse signal a of the DD control circuit 20 → the transistor Q7 → the resistor R10 → the diode D3 → the resistor R2 →→ the switch element Q10 → the ground.

  For this reason, the transistor Q7 is in an on state during a period in which the pulse signal a from the DD control circuit 20 is on. Therefore, the PFC gate signal d ′ is turned on in synchronization with the pulse signal a from the DD control circuit 20 regardless of the period from time t1 to time t2.

That is, when the rectified voltage obtained by rectifying the AC input voltage is near the bottom B, the delay time is zero, and when the rectified voltage is near the top A, the PFC pulse signal d ′ is set with a preset delay time. Is output to the switching element Q1 to control the power factor.
Therefore, when the rectified voltage is in the vicinity of the top A, the step-up rate decreases, and the power factor can be sufficiently improved. For this reason, the power factor can be improved by conforming to the new standard LEVEL V of “ENAGY STAR”, and an inexpensive power factor improvement circuit can be provided.
FIG. 6 shows waveforms of the rectified divided signal f of the alternating current input voltage and the drain current PFCId flowing through the switching element Q1 at this time. FIG. 7 shows the relationship between the AC input voltage and the PFC output voltage.

  Further, when the load current becomes light, the pulse width of the pulse signal a from the DD control circuit 20 becomes narrower in order to stabilize the output voltage of the DC-DC converter circuit 3. The waveform of each signal of the power factor correction circuit at light load is shown in FIG. In the example of FIG. 8, the pulse width of the pulse signal a is a period from time t1 to time t2. Since the delay time by the differentiating circuit does not change with respect to the load current, the differentiating circuit signal b is always in a high potential state with respect to the pulse divided signal c. For this reason, the transistor Q8 is not turned on.

  Further, since the discharge current of the capacitor C1 can be reduced by a light load, the charging voltage of the capacitor C1 does not vary greatly regardless of the input voltage waveform. Therefore, the transistor Q7 does not turn on because the voltage at the voltage dividing point f of the rectified voltage is higher than the voltage of the pulse signal due to the influence of the charging voltage of the capacitor C1. For this reason, when the pulse width of the pulse signal from the DD control circuit 20 becomes a predetermined delay time or less, the PFC pulse signal d is not output.

That is, the delay circuit sets the PFC gate signal d to a pulse width that is narrower than the pulse width of the pulse signal a as the load of the DC-DC converter circuit 3 becomes lighter, and the load of the DC-DC converter circuit 3 is equal to or less than a predetermined load power. Then, the pulse width of the PFC gate signal d is set to zero. For this reason, in the light load state, the operation of the power factor correction circuit 2 is not performed, the power consumption of the power factor correction circuit 2 is eliminated, and the conversion efficiency can be improved.
When the pulse width of the PFC gate signal d becomes zero, there is no pulse input to the gate ON / OFF circuit 13. Accordingly, the capacitor C6 and the resistor R15 are discharged, the gate ON / OFF circuit signal g becomes zero, and the switch element Q10 is turned off. That is, the detection unit 11 is disconnected from the ground, the power consumption of the resistors R1 and R2 becomes zero, and the power consumption of the detection unit 11 in a no-load to light load state can be suppressed.

  As described above, according to the embodiment, since the switching element Q1 can be driven by the PFC gate signal whose on-pulse width is changed according to the AC input voltage, the power factor can be improved by conforming to the new standard LEVEL V of “ENAGY STAR”. Therefore, it is possible to provide a power factor correction circuit that is inexpensive and further suppresses standby power.

It is a circuit diagram which shows the AC-DC converter containing the power factor improvement circuit of an Example. It is a detailed view of a PFC control circuit diagram in the power factor correction circuit of the embodiment. It is a figure which shows the divided voltage signal after rectification | rectification which rectified the alternating current input voltage. It is a timing chart of each signal in the delay circuit near the top of the divided voltage signal after rectification at the rated load. It is a timing chart of each signal in the delay circuit near the bottom of the divided voltage signal after rectification at the rated load. It is a figure which shows the waveform of the rectified partial voltage signal f of the alternating current input voltage, and the drain current PFCId which flows into the switching element Q1. It is a figure which shows the relationship between the alternating current input voltage and PFC output voltage of an Example. It is a figure which shows the waveform of each signal of the power factor improvement circuit at the time of light load. It is a circuit diagram which shows the AC-DC converter containing the conventional power factor improvement circuit.

Vin AC power supply DB, rectifier T1, T1a transformer P1, P1a Primary winding S1, S2a Secondary winding P2, P2a Auxiliary winding L1, L Step-up reactors D1-D5 Diodes Q1, Q2, Switching elements Q3-Q8 Transistor C2 , C12, Cs Smoothing capacitors C1, C3, C4, C5, C6 capacitors
CP1 Comparator R1-R15 Resistor PC1 Photocoupler Q10 Switch element
DESCRIPTION OF SYMBOLS 2,26 Power factor improvement circuit 3,27 DC-DC converter circuit 10, 10a PFC control circuit 11 Detection part 12 Delay circuit 20, 20a DD control circuit

Claims (1)

A DC-DC converter circuit that boosts a rectified voltage obtained by rectifying an AC input voltage from an AC power supply by turning on / off the first switching element and improves a power factor to drive a boosted output voltage by a first pulse signal. Power factor correction circuit that outputs to
When the first pulse signal having a pulse width corresponding to the output voltage of the DC-DC converter circuit is input and an ON pulse of the first pulse signal is generated, a delayed pulse signal having a pulse width corresponding to the rectified voltage is generated. It raises a delay circuit for generating a second pulse signal by combining the first pulse signal and before Kioso extension pulse signal,
The delay circuit widens the pulse width of the delayed pulse signal as the rectified voltage increases, and narrows the pulse width of the delayed pulse signal as the rectified voltage decreases.
A switch driving circuit for driving the first switching element by the second pulse signal generated by the delay circuit;
The delay circuit has a voltage detection circuit for detecting the rectified voltage for generating a delayed pulse signal having a pulse width corresponding to the rectified voltage,
A power factor correction circuit comprising: a circuit that disconnects the voltage detection circuit from GND when a pulse width of the second pulse signal generated by the delay circuit is zero.

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