JP5659950B2 - A / D converter - Google Patents

Description

  The embodiment referred to in this application relates to an A / D converter (Analog-to-Digital Converter).

  In recent years, a successive approximation register (SAR) that can be realized as an A / D converter with a relatively simple circuit configuration, is highly compatible with a CMOS process, and can be manufactured at a relatively low cost. A type of A / D converter is drawing attention.

  For example, when a successive approximation A / D converter is formed in a semiconductor integrated circuit of a CMOS process, a method called charge redistribution based on switched capacitor technology is the mainstream. This is because it is relatively easy to realize a switch close to an ideal in the CMOS process.

  Conventionally, various A / D conversions such as a charge redistribution successive approximation A / D converter that reduces the occupied area, or an A / D converter that achieves high resolution without increasing the circuit scale. A vessel has been proposed.

JP 2008-236420 A JP 2008-187537 A

  In the charge redistribution type successive approximation A / D converter described above, for example, in order to improve the resolution by 1 bit, a large-capacity capacitor for holding charges must be provided by switching, and the occupation area is greatly increased. An increase is to come.

  According to an embodiment, an A / D converter is provided that includes a plurality of capacitors, a plurality of switches, a comparison circuit, a control circuit, and a resolution improving unit.

  The plurality of capacitors receive an analog input signal and accumulate electric charge according to the input voltage of the input signal, and the plurality of switches apply the input voltage and the reference voltage by switching the capacitors. To do.

The comparison circuit has an operation state controlled according to a clock signal, controls the plurality of switches, performs charge redistribution by the plurality of capacitors, and sequentially compares, and the control circuit outputs an output of the comparison circuit. Receiving and controlling the plurality of switches to output a digital output signal corresponding to the analog input signal.

The resolution improving unit defines a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit by using a comparison time by the comparison circuit that becomes longer as the input voltage is smaller .

  The disclosed A / D converter has an effect that the resolution can be improved without significantly increasing the occupied area.

It is a block diagram which shows an example of an A / D converter. FIG. 2 is a block diagram showing a case where the resolution is improved by 1 bit in the A / D converter of FIG. 1. It is a block diagram which shows an example of the A / D converter which concerns on a present Example. It is a figure for demonstrating an example of the comparison circuit in the A / D converter shown in FIG. It is a figure for demonstrating operation | movement of the comparison circuit in the A / D converter shown in FIG. It is a block diagram which shows an example of the resolution improvement part in the A / D converter shown in FIG. 3 with a comparison circuit. FIG. 7 is a block diagram illustrating an example of a TDC circuit in the resolution improving unit illustrated in FIG. 6. It is a figure for demonstrating operation | movement of the TDC circuit shown in FIG. FIG. 7 is a diagram (part 1) for explaining the operation of the resolution improving unit illustrated in FIG. 6; FIG. 7 is a diagram (part 2) for explaining the operation of the resolution improving unit illustrated in FIG. 6; It is a flowchart which shows an example of the A / D conversion process in the A / D converter which concerns on a present Example.

  First, before describing the embodiment of the A / D converter in detail, the A / D converter and its problems will be described with reference to FIG. 1 and FIG.

  FIG. 1 is a block diagram showing an example of an A / D converter, which shows a charge redistribution type successive approximation A / D converter, which has a resolution of 10 bits and is differentially driven. Is shown. In FIG. 1, reference numeral 11 is a first capacitor circuit, 12 is a second capacitor circuit, 2 is a comparator (comparator circuit), and 3 is a SAR control circuit.

  Further, reference numerals CP0, CP1, CP2,..., CP10 and CN0, CN1, CN2,..., CN10 denote capacitors (capacitance elements), and notations such as 1C, 1C, 2C,. Indicates the relative magnitude of the capacity.

  Further, reference symbols SWP1, SWP2, SWP3,..., SWP10, SWN1, SWN2, SWN3,..., SWN10, and SWCP and SWCN represent switches.

  Reference numeral Vref is a predetermined reference voltage, GND is a ground voltage, Vin + is a voltage of one of the differential analog input signals (first signal), and Vin− is the other of the differential analog input signals. The voltage of the signal (second signal) is shown.

  As shown in FIG. 1, the A / D converter includes a first capacitor circuit 11 and a second capacitor circuit 12, a comparison circuit 2, and a SAR control circuit (control circuit: SAR CNTL) 3.

  Here, the first capacitance circuit 11 includes a first capacitor including a plurality of capacitors CP0, CP1, CP2,..., CP10, and a first switch including a plurality of switches SWP1, SWP2, SWP3,. Have a group.

  One end of each capacitor CP0, CP1, CP2, CP3,..., CP10 is connected to one input of the comparison circuit 2, and the other end is connected to the corresponding switch SWP1, SWP2, SWP3,. It is connected. Here, one input of the comparison circuit 2 is grounded (GND) via the switch SWCP. Note that the voltage of one input of the comparison circuit 2 is represented by Vcomp +.

  Each of the switches SWP1, SWP2, SWP3,..., SWP10 selects one of the voltage Vin + of the first signal, the reference voltage Vref, and the ground voltage GND, and the other ends of the corresponding capacitors CP0, CP1, CP2,. To be applied. The other end of the capacitor CP0 is grounded.

  Here, the capacitances of the capacitors CP1, CP2, CP3,..., CP10 are set to increase by 1C, 2C, 4C,. The capacitor CP0 is set to the same capacitance 1C as the capacitor CP1.

  Similarly, the second capacitor circuit 12 includes a second capacitor including a plurality of capacitors CN0, CN1, CN2,..., CN10, and a second switch including a plurality of switches SWN1, SWN2, SWN3,. Have a group.

  One end of each capacitor CN0, CN1, CN2, CN3,..., CN10 is connected to the other input of the comparison circuit 2, and the other end is connected to the corresponding switch SWN1, SWN2, SWN3,. It is connected. Here, the other input of the comparison circuit 2 is grounded via the switch SWCN. The voltage at the other input of the comparison circuit 2 is represented by Vcomp−.

  Each of the switches SWN1, SWN2, SWN3,..., SWN10 selects any one of the voltage Vin-, the reference voltage Vref and the ground voltage GND of the second signal, and other than the corresponding capacitors CN0, CN1, CN2,. It is applied to the end. The other end of the capacitor CN0 is grounded.

  Here, the capacitances of the capacitors CN1, CN2, CN3,..., CN10 are set to increase by the power of 2 of 1C, 2C, 4C,. The capacitor CN0 is set to the same capacitance 1C as the capacitor CN1.

  The SAR control circuit 3 controls the above-described switches SWP1, SWP2, SWP3,..., SWP10, SWN1, SWN2, SWN3,..., SWN10, and SWCP, SWCN, and performs the following processing, for example.

  That is, first, the switches SWCP and SWCN are short-circuited (ON) to connect Vcomp + and Vcomp− to GND, and Vin + is selected by the switches SWP1 to SWP10, and Vin− is selected by the switches SWN1 to SWN10. As a result, the capacitors CP0 to CP10 are charged with a charge of Vin +, and the capacitors CN0 to CN10 are charged with a charge of Vin−.

  Further, the switches SWCP and SWCN are opened (turned off), and GND is selected by the switches SWP1 to SWP10 and SWN1 to SWN10. As a result, the voltage Vcomp + of one input of the comparison circuit 2 becomes Vcomp + = − Vin +, and the voltage Vcomp− of the other input becomes Vcomp − = − Vin−.

  Next, only the switches SWP10 and SWN10 connected to the capacitors CP10 and CN10 having a capacitance of 512C are switched. That is, the reference voltage Vref is selected by the SWP10 and the reference voltage Vref is selected by the SWN10. As a result, Vcomp + = Vref / 2−Vin + and Vcomp− = Vref / 2−Vin−.

  This is because the total capacity of the capacitors CP0 to CP9 is 512C, which is equal to 512C, which is the capacity of the capacitor CP10, and the total capacity of the capacitors CN0 to CN9 is 512C, which is equal to 512C, which is the capacity of the capacitor CN10. is there.

  Then, the state of Vcomp + = Vref / 2−Vin + and Vcomp− = Vref / 2−Vin− is determined by the comparison circuit 2 to obtain the most significant bit (MSB). That is, when Vcomp + <Vcomp−, the output (determination result) Dcomp of the comparison circuit 2 is “1”, and when Vcomp +> Vcomp−, Dcomp is “0”.

  Further, only the switches SWP9 and SWN9 connected to the capacitors CP9 and CN9 having a capacitance of 256C are switched. First, when the determination result Dcomp of the previous (MSB) is “1”, Vref is selected by SWP9 and GND is selected by SWN9. As a result, Vcomp + = 3Vref / 4−Vin + and Vcomp− = Vref / 2−Vin−.

  On the other hand, when the previous determination result Dcomp is “0”, GND is selected by SWP9 and Vref is selected by SWN9. As a result, Vcomp + = Vref / 2−Vin +, and Vcomp− = 3Vref / 4−Vin−.

  Regardless of the previous determination result, when Vcomp + <Vcomp−, the determination result (the determination result of the second highest bit) Dcomp is “1”, and when Vcomp +> Vcomp−, the second bit The determination result Dcomp is “0”.

  Then, similarly to the switches SWP9, SWN9, capacitors CP8, CN8 having capacitances of 128C, 64C,..., 1C; CP7, CN7; ...; switches SWP8, SWN8 connected to CP1, CN1, SWP7, SWN7; , SWN1 are sequentially switched.

  In this manner, the same processing is repeated until the switches SWP1 and SWN1 are switched, whereby the A / D converter shown in FIG. 1 converts the differential analog input signals (Vin +, Vin−) to 10-bit digital. The signal Dout can be converted.

  FIG. 2 is a block diagram showing a case where the resolution is improved by 1 bit in the A / D converter of FIG. In other words, FIG. 2 shows a charge redistribution successive approximation A / D converter having a resolution of 11 bits.

  In the successive approximation A / D converter of the charge redistribution method, for example, the least significant bit (LSB) that depends on the capacitor having the capacitance 1C is determined with the same accuracy. The capacity of the capacitor to be used is increased.

  That is, as apparent from the comparison between FIG. 2 and FIG. 1 described above, the A / D converter having 11-bit resolution is twice the maximum capacity 512C of the A / D converter of FIG. Capacitors CP11 and CN11 having a capacity of 1024C are added.

  The operation of the A / D converter in FIG. 2 is the same as the operation of the switches SWP10 and SWN10 corresponding to the maximum capacity capacitor in the A / D converter in FIG. 1, and the switch corresponding to the capacitors CP11 and CN11 having the maximum capacity 1024C. What is necessary is just to apply to SWP11 and SWN11.

  In this way, the charge redistribution successive approximation A / D converter is a capacitor having a capacity that is twice the maximum capacity of the 10-bit resolution A / D converter, for example, in order to improve the resolution by 1 bit. CP11 and CN11 must be added.

  For example, when capacitors CP11 and CN11 having a large capacity of 1024C are added, the chip area is greatly increased. Furthermore, the addition of the large-capacity capacitors CP11 and CN11, for example, doubles the capacitance (input capacitance) with respect to the input signals (Vin +, Vin-), so that the power consumption of the preceding circuit of the A / D converter is also increased. Will increase.

  Although FIG. 1 and FIG. 2 show the differential drive A / D converter, the same applies to a single-ended A / D converter, and the signal logic can be changed as appropriate. Furthermore, it goes without saying that the number of bits for converting an analog signal into a digital signal is not limited to 10 or 11 bits.

  Hereinafter, embodiments of the A / D converter will be described in detail with reference to the accompanying drawings. FIG. 3 is a block diagram showing an example of the A / D converter according to the present embodiment, and shows a charge redistribution type successive approximation A / D converter.

  In FIG. 3, reference numeral 11 is a first capacitor circuit, 12 is a second capacitor circuit, 2 is a comparator (comparator), 3 is a SAR control circuit, and 4 is a resolution improving unit.

  As apparent from the comparison between FIG. 3 and FIG. 1 described above, the A / D converter of this embodiment adds a resolution improving unit 4 to the A / D converter of FIG. bit (for example, about 2 to 3 bits) is improved.

  The configurations of the first and second capacitance circuits 11 and 12, that is, the configurations and operations of the capacitors CP0 to CP10 and CN0 to CN10, and the switches SWP1 to SWP10, SWN1 to SWN10, and SWCP and SWCN are described with reference to FIG. It is the same as the throat.

  That is, as described with reference to FIG. 1, in the A / D converter of this embodiment, for example, as in the A / D converter of FIG. 1, for example, differential analog input signals (Vin +, Vin−) Is converted into a 10-bit digital signal Dout.

  In the A / D converter of this embodiment, a resolution improving unit 4 is provided that uses the comparison time of the comparison circuit 2 and converts an analog input signal into a digital signal with a resolution that exceeds the comparison determination of the comparison circuit 2. It has been. The configuration and operation of the resolution improving unit 4 will be described in detail later with reference to FIG.

  First, as a premise in the A / D converter of this embodiment, it is assumed that the quantization noise is random. That is, the input voltage in the last conversion of SAR becomes quantization noise, and the quantization noise is random when the input signal is not a DC signal.

  Furthermore, with reference to FIG. 4 and FIG. 5, the prerequisites for the A / D converter of this embodiment will be described. FIG. 4 is a diagram for explaining an example of a comparison circuit in the A / D converter shown in FIG. 4A is a circuit diagram showing an example of the comparison circuit 2, and FIG. 4B is a timing diagram for explaining the operation of the comparison circuit 2 shown in FIG. It is.

  As shown in FIG. 4A, the comparison circuit 2 includes p-channel MOS transistors Qp1 to Qp6 and n-channel MOS transistors Qn1 to Qn7. Here, the transistors Qp3, Qp4 and Qn2 to Qn5 constitute a differential amplifier, and receive the differential input voltages VI− and VI + at the gates of the transistors Qn3 and Qn5.

  The input voltage VI + of the differential amplifier (comparing circuit 2) corresponds to, for example, the voltage Vcomp + in FIG. 3, and the input voltage VI− of the differential amplifier corresponds to, for example, the voltage Vcomp− in FIG. To do.

  Transistors Qp1 and Qn1, and transistors Qp6 and Qn7 constitute an inverter, respectively, and output outputs Vout− and Vout + defined by the magnitudes of input voltages VI− and VI + of the differential amplifier.

  Further, the transistors Qp2, Qp5 and Qn6 control the operation state of the comparison circuit 2 according to the clock signal CLK. Specifically, when the clock signal CLK is “1 (high level)”, the comparison circuit 2 is turned on. It comes to be activated.

  4B, when the clock signal CLK changes from “0 (low level)” to “1”, the comparison circuit 2 in FIG. 4A outputs an output delayed by a predetermined conversion time Td. Vout (Vout +, Vout−) is output, and the conversion time Td (comparison time) is smaller as the difference between the input voltages VI− and VI + is smaller, that is, as VI + −VI− is smaller. become longer.

  FIG. 5 is a diagram for explaining the operation of the comparison circuit in the A / D converter shown in FIG. 3, showing the range of the voltage Vcomp + −Vcomp−, that is, the voltage VI + −VI−. It is.

  As described with reference to FIG. 1, the comparison circuit 2 performs switching from the MSB determination to the LSB determination sequentially.

  Here, in the MSB determination performed by switching the switches SWP10 and SWN10 connected to the capacitors CP10 and CN10 having the maximum capacity 512C, the range in which the voltage of VI + −VI− can be Vref / 2.

On the other hand, in the LSB determination performed by switching the switches SWP1 and SWN1 connected to the capacitors CP1 and CN1 having the maximum capacity 1C, the range that the voltage of VI + −VI− can take is Vref / 1024 (= V _LSB ). .

  Here, the lower bit for which the comparison circuit 2 performs the determination by switching the switch connected to the capacitor having a smaller capacity, the range in which the voltage of VI + −VI− can be reduced and the conversion time Td becomes longer. That is, when the difference (VI + −VI−) between the input voltages of the comparator circuit 2 is small, the potential difference of the latch becomes small, so that the conversion time Td is extended.

  In the A / D converter of the present embodiment, a conversion time Td having a predetermined length, for example, the conversion time Td when the comparison circuit 2 is determined by the minimum capacity 1C is used to obtain the comparison circuit 2. An A / D conversion value having a higher resolution (lower bits) than the resolution to be obtained is obtained.

  In other words, the A / D converter of this embodiment uses the conversion time Td (comparison time) of the comparison circuit 2 having a predetermined time by the minute possible improvement unit 4 to improve the resolution by the comparison determination of the comparison circuit 2. A / D conversion is performed with a resolution exceeding that.

  FIG. 6 is a block diagram showing an example of a resolution improving unit in the A / D converter shown in FIG. 3 together with a comparison circuit. FIG. 7 is a block diagram showing an example of the TDC circuit in the resolution improving section shown in FIG. 6, and FIG. 8 is a diagram for explaining the operation of the TDC circuit shown in FIG.

  As shown in FIG. 6, the resolution improving unit 4 includes an OR gate 41, a TDC (Time-to-Digital Converter) circuit 42, and a TDC control circuit (TDC CNTL) 43.

  The TDC circuit 42 converts the time from the rising timing of the clock signal CLK to the rising timing of the output Vend of the OR gate 41 into a digital code and outputs the digital code to the TDC control circuit 43.

  Here, the OR gate 41 receives the outputs Vout + and Vout− of the comparison circuit 2 and outputs a signal Vend that rises to “1” when either one of the outputs Vout (Vout +, Vout−) becomes “1”. To do. Therefore, the TDC circuit 42 outputs a digital code corresponding to the conversion time Td in the comparison circuit 2.

  As shown in FIG. 7, the TDC circuit 42 includes, for example, a plurality of inverters I0 to I7 that constitute a delay line, a plurality of flip-flops FF0 to FF7 that record a delay, and an encoder ENC.

  The encoder ENC converts the sumo metacode into a binary code, and the TDC circuit 42 in FIG. 7 outputs a 3-bit TDC code. As described above, the TDC circuit 42 converts the conversion time Td of the comparison circuit 2 from the rising timing of the clock signal CLK to the rising timing of the signal Vend into a 3-bit TDC code and outputs it. .

  Here, the outputs of FF0 to FF7 take into account logic inversion by I0 to I7, for example, FF0, FF2, FF4, and FF6 output positive logic outputs to the encoder ENC, and FF1, FF3, FF5 , FF7 outputs a negative logic output to the encoder ENC.

  Therefore, in the example of FIG. 8, since the signals START [1], START [3], START [5], START [7] are inverted by FF1, FF3, FF5, FF7, the encoder ENC has “1, 1, 1, 0, 0, 0, 0, 0 "is input.

  In order to simplify the description, the TDC circuit 42 of FIG. 7 has shown an example of outputting a 3-bit TDC code. However, as an actual application, for example, a TDC code of about 5 bits is output, At this time, for example, the resolution can be improved by about 2 to 3 bits.

  9 and 10 are diagrams for explaining the operation of the resolution improving unit shown in FIG. Here, FIG. 9A shows the relationship between the conversion time and the TDC code with respect to the input voltage difference of the comparison circuit, and FIG. 9B shows the relationship between the appearance frequencies with respect to the TDC code.

  FIG. 10A shows the threshold value in the TDC code when the resolution is improved by 1 bit, and FIG. 10B shows the threshold value in the TDC code when the resolution is improved by 2 bits.

  As shown in FIG. 9A, the input voltage difference (VI + −VI−) of the comparison circuit 2 is divided at equal intervals on the horizontal axis, and the conversion time Td (comparison time) of the comparison circuit 2 is plotted on the vertical axis. If it is taken, it becomes a nonlinear characteristic.

  That is, when A / D conversion + TDC is performed a sufficient number of times (N times) and a histogram is created for the TDC result, the relationship between the TDC code and the appearance frequency (frequency) is biased as shown in FIG. 9B. Become a thing.

  Specifically, as shown in FIG. 9A, when the input voltage difference (VI + −VI−) is divided at equal intervals, the conversion times Td of the corresponding comparison circuits 2 do not become equal intervals. Note that as the 3-bit TDC code, “000”, “001”, “010”, “011”, “100”, “101”, “ 110 ”and“ 111 ”.

  Further, when the TDC code is taken on the horizontal axis and the appearance frequency of the TDC code is taken on the vertical axis, a histogram as shown in FIG. 9B is obtained. Here, the appearance frequency of the TDC code increases as the input voltage difference (VI + −VI−) decreases, and the appearance frequency decreases as the input voltage difference increases.

  In the A / D converter of this embodiment, since the quantization noise is random, in the histogram as shown in FIG. 9B, a boundary where the frequencies are equal is set as the bit determination threshold Th.

  The histogram is created, for example, by obtaining the TDC code converted by the TDC circuit 42 a plurality of times (for example, N times). Further, the threshold value Th in the histogram can be updated in the background.

  After the A / D conversion is started, when a sufficient number of conversions are performed to complete the histogram, the TDC code can be processed to improve the resolution by + n bits.

  That is, when the resolution is improved by 1 bit, for example, as shown in FIG. 10A, a threshold value Th0 that is the same frequency as the application frequency is set. That is, as described above, since the quantization noise is random, the TDC code boundary in which the frequency is just halved by dividing the biased histogram of FIG. 9B by half is half of the input voltage (= quantization noise). It becomes a boundary (threshold).

  Then, a bit to be added (+ n bit: 1 bit) is defined depending on which of the two areas delimited by the threshold Th0 is included in the TDC code. Then, by repeating this process a plurality of times, a plurality of bits can be added.

  Specifically, in the example of FIG. 10A, when the TDC code is “000”, “001”, “010”, the added 1 bit is defined as “0”, and “011”, “100” ], “101”, “110”, “111”, the added 1 bit is defined as “1”.

  When the resolution is improved by 2 bits, as shown in FIG. 10B, for example, threshold values Th1, Th2, and Th3 that are the same frequency with respect to the application frequency are set. Then, a bit to be added is defined depending on which of the four areas divided by the threshold values Th1, Th2, and Th3 is included in the TDC code.

  Specifically, in the example of FIG. 10B, when the TDC code is “000”, 2 bits to be added are defined as “00”, and when the TDC code is “001”, “010”, it is added. The two bits to be specified are defined as “01”.

  Further, when the TDC code is “011” or “100”, the 2 bits to be added are defined as “11”, and when the TDC code is “101”, “110”, or “111”, the 2 bits to be added are defined. It is defined as “11”.

  Thus, according to the A / D converter of the present embodiment, for example, the number of bits obtained by digital conversion without adding the capacitors CP11 and CN11 having a capacity of 1024C as in the A / D converter of FIG. It becomes possible to increase.

  As the TDC circuit 42, for example, when a circuit that generates a TDC code of about 5 bits is applied, it is possible to improve the resolution of, for example, about 2 to 3 bits by setting the threshold value described above. become.

  Here, the comparison time (conversion time Td) of the comparison circuit 2 by the TDC circuit 42 is converted into a TDC code because the last bit of the SAR-ADC (successive comparison type A / D conversion), that is, the minimum capacity 1C. The comparison time by the capacitors CP1 and CN1 is targeted.

  FIG. 11 is a flowchart illustrating an example of A / D conversion processing in the A / D converter according to the present embodiment. When the A / D conversion process starts, first, in step ST1, SAR A / D conversion is performed. In other words, for example, the A / D conversion of the input signal is performed by performing successive approximation using a plurality of capacitors and a plurality of switches, as described in detail with reference to FIG.

  Next, the process proceeds to step ST2, for example, using the conversion time Td (comparison time) of the comparison circuit 2 with the minimum capacity 1C as described in detail with reference to FIGS. Is converted into a TDC code, and the process proceeds to step ST3.

  In step ST3, the TDC conversion result (TDC code obtained by converting the comparison time) is added to the histogram as shown in FIG. 9B, and the process proceeds to step ST4. In step ST4, it is determined whether the number of A / D conversions is smaller than N, and if it is determined that the number of A / D conversions <N (yes), the process returns to step ST1 and the same processing is repeated.

  In step ST4, if it is determined that the number of A / D conversions is not <N (no), that is, if the number of A / D conversions is N or more, the process proceeds to step ST5, and the TDC conversion result N times before is obtained. It deletes from a histogram and progresses to step ST6.

  Here, in step ST5, after the A / D conversion is started, the conversion is performed a sufficient number of times (N times), and the histogram based on the new N times of TDC conversion results is used in the next step ST6. .

  The number (N) of performing A / D conversion for obtaining a high-precision histogram is set to an appropriate number according to the required A / D conversion accuracy and the number of bits of the TDC code by the TDC circuit. . The threshold value (Th0; Th1 to Th3) in the histogram can be updated in the background.

  In step ST6, threshold values Th0, Th1 to Th3 for obtaining additional bits (+ n bits) as described with reference to FIG. 10 are determined, and the process proceeds to step ST7. In step ST7, an additional bit (+ n bit) based on the threshold values Th0 and Th1 to Th3 is obtained, and an A / D conversion result including the additional bit is obtained. Such an A / D conversion process is repeated.

  As described above, according to the A / D converter of this embodiment, the resolution can be improved without adding a large-capacity capacitor without causing a significant increase in chip area and power consumption of the previous circuit. It becomes possible to improve.

  In the above description, the differential drive A / D converter is shown as an example, but the same applies to a single-ended A / D converter, and the signal logic can be changed as appropriate. . Furthermore, it goes without saying that the number of bits for converting an analog signal into a digital signal can be designed in various ways.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A plurality of capacitors that receive an analog input signal and store electric charge according to the input voltage of the input signal;
A plurality of switches for switching and applying the input voltage and the reference voltage to each capacitor;
A comparison circuit for controlling the plurality of switches and performing sequential comparison by performing charge redistribution by the plurality of capacitors;
A control circuit that receives the output of the comparison circuit and controls the plurality of switches to output a digital output signal corresponding to the analog input signal;
A resolution improving unit that defines a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit by using a comparison time by the comparison circuit;
An A / D converter characterized by comprising:

(Appendix 2)
The resolution improving unit is
A TDC circuit for converting a comparison time by the comparison circuit into a digital code;
A TDC control circuit that receives a digital code from the TDC circuit and outputs a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit;
2. The A / D converter according to appendix 1, wherein:

(Appendix 3)
The TDC circuit converts a comparison time by the comparison circuit using a capacitor having a minimum capacitance among the plurality of capacitors into a digital code,
The TDC control circuit outputs a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit by the capacitor with the minimum capacitance;
3. The A / D converter according to appendix 2, wherein

(Appendix 4)
The TDC circuit converts a time from a clock signal transition timing to a comparison determination timing by the comparison circuit into a digital code,
The TDC control circuit determines the output signal according to a boundary where the appearance frequency of the digital code is the same frequency.
4. The A / D converter according to appendix 2 or appendix 3, wherein

(Appendix 5)
The boundary is
It is set as a threshold value in a histogram created by obtaining the digital code converted by the TDC circuit a plurality of times.
The A / D converter according to appendix 4, wherein the A / D converter is characterized in that

(Appendix 6)
The threshold in the histogram is updated in the background.
The A / D converter according to appendix 5, which is characterized in that.

(Appendix 7)
The resolution improving unit is
Improving the resolution of 2 bits or 3 bits exceeding the resolution exceeding the comparison judgment of the comparison circuit;
The A / D converter according to any one of Supplementary Note 1 to Supplementary Note 6, wherein:

(Appendix 8)
The input signal includes a differential first signal and a second signal;
The plurality of capacitors includes a first capacitor group that receives the first signal and a second capacitor group that receives the second signal;
The plurality of switches include a first switch group for the first capacitor group, and a second switch group for the second capacitor group,
The comparison circuit sequentially compares voltages redistributed by the first capacitor group and the second capacitor group, and
The control circuit receives the output of the comparison circuit, controls the first switch group and the second switch group, and outputs a digital output signal corresponding to the analog and differential input signals;
The A / D converter according to any one of appendix 1 to appendix 7, which is characterized in that.

(Appendix 9)
Each of the first capacitor group and the second capacitor group includes a plurality of capacitors each having a capacitance that is a power of 2.
9. The A / D converter according to appendix 8, wherein

(Appendix 10)
Each of the first capacitor group and the second capacitor group includes two capacitors having a minimum capacitance among the plurality of capacitors.
The A / D converter according to appendix 9, wherein:

2 Comparator (comparison circuit)
3 SAR control circuit (control circuit: SAR CNTL)
4 Resolution Improvement Unit 11 First Capacitance Circuit 12 Second Capacitance Circuit 41 OR Gate 42 TDC Circuit 43 TDC Control Circuit (TDC CNTL)

Claims (5)

A plurality of capacitors that receive an analog input signal and store electric charge according to the input voltage of the input signal;
A plurality of switches for switching and applying the input voltage and the reference voltage to each capacitor;
A comparison circuit that controls an operation state according to a clock signal, controls the plurality of switches, performs charge redistribution by the plurality of capacitors, and sequentially compares;
A control circuit that receives the output of the comparison circuit and controls the plurality of switches to output a digital output signal corresponding to the analog input signal;
Using the comparison time by the comparison circuit that becomes longer as the input voltage is smaller, a resolution improvement unit that defines a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit;
An A / D converter characterized by comprising: The resolution improving unit is
A TDC circuit for converting a comparison time by the comparison circuit into a digital code;
A TDC control circuit that receives a digital code from the TDC circuit and outputs a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit;
The A / D converter according to claim 1, comprising: The TDC circuit converts a comparison time by the comparison circuit using a capacitor having a minimum capacitance among the plurality of capacitors into a digital code,
The TDC control circuit outputs a digital output signal corresponding to the input signal with a resolution exceeding the comparison determination of the comparison circuit by the capacitor with the minimum capacitance;
The A / D converter according to claim 2. The TDC circuit converts from the transition timing of the clock signal the time to comparison determination timing by the comparison circuitry to a digital code,
The TDC control circuit determines the output signal according to a boundary where the appearance frequency of the digital code is the same frequency.
The A / D converter according to claim 2 or 3, wherein The input signal includes a differential first signal and a second signal;
The plurality of capacitors includes a first capacitor group that receives the first signal and a second capacitor group that receives the second signal;
The plurality of switches include a first switch group for the first capacitor group, and a second switch group for the second capacitor group,
The comparison circuit sequentially compares voltages redistributed by the first capacitor group and the second capacitor group, and
The control circuit receives the output of the comparison circuit, controls the first switch group and the second switch group, and outputs a digital output signal corresponding to the analog and differential input signals;
The A / D converter according to any one of claims 1 to 4, wherein the A / D converter is provided.

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