JP5657767B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a wiring board and an IC (Integrated Circuit) chip mounted thereon, and more particularly to a heat dissipation structure in the semiconductor device.

  The amount of heat generated during the operation of an IC chip such as a liquid crystal driver IC tends to increase. The increasing tendency of the IC chip heat generation is particularly remarkable in a semiconductor device using a flexible wiring board as compared with a semiconductor device using a rigid wiring board. For this reason, the importance of the heat dissipation structure in the semiconductor device is increasing.

  The flexible wiring board has a structure in which a conductor layer such as wiring is formed on a flexible insulating film. For example, a conductor layer is formed by bonding a copper foil to a polyimide film that is an insulating film. Due to its thinness, the flexible wiring board has a smaller heat capacity and a lower mechanical strength than a rigid wiring board. For this reason, it is generally difficult to mount heavy parts such as a heat sink (heat sink) on the flexible wiring board.

  In order to cope with the heat generation problem when a flexible wiring board is used, Patent Documents 1 and 2 disclose a heat dissipation structure of a tape carrier package (TCP) which is one of semiconductor devices using the flexible wiring board. doing. Among these, the TCP disclosed in Patent Document 1 has the following configuration. That is, an IC chip having a “heat radiating” electrode separately from electrodes used for signal input / output with an external device is mounted on the flexible wiring board. Further, a heat radiation conductive pattern physically separated from the signal wiring pattern is formed on the surface of the flexible wiring board. The heat radiation electrode of the IC chip and the heat radiation conductive pattern of the wiring board are connected via a conductor such as a gold bump or solder. In this specification, connecting via conductors such as gold bumps and solder is referred to as “conductor connection”.

  Patent Document 2 also discloses that a heat radiation conductive pattern is formed on the surface of the flexible wiring board for heat radiation of the IC chip mounted on the flexible wiring board. However, in Patent Document 2, there is no connection between the electrode of the IC chip and the conductive pattern for heat dissipation. Specifically, Patent Document 2 discloses a structure (FIG. 3 of Patent Document 2) in which the IC chip and the heat dissipation conductive pattern are physically separated from each other and the IC chip and the heat dissipation conductive pattern. The structure (FIG. 6 of patent document 2) arrange | positioned so that may touch physically is disclosed. More specifically, in FIGS. 3 and 6 of Patent Document 2, there is no conductor connection between the electrode of the IC chip and the conductive pattern for heat dissipation, and the short side of the rectangular IC chip is covered. The structure formed so that the conductive pattern for heat dissipation opposes is shown.

JP 2007-158001 A JP 2004-111996 A

  As described above, in the heat dissipation structure of the semiconductor device disclosed in Patent Document 1, the heat dissipation conductive pattern formed on the flexible wiring board and the heat dissipation electrode of the IC chip are connected by a conductor having a low thermal resistance. Has a structure. Thereby, since the thermal resistance between the IC chip and the conductive pattern for heat dissipation is lowered, an improvement in the heat dissipation effect can be expected. However, when terminals having different potentials are arranged around the IC chip, or when there is a concern about electrostatic discharge (ESD), there is a gap between the IC chip electrode and the heat dissipation conductive pattern. There are many cases where conductors cannot be connected. For example, when the IC chip is a driver IC that drives a liquid crystal display panel, the driver IC may be damaged by discharge when a charged human body comes into contact with the liquid crystal display panel. Since the heat dissipation conductive pattern generally has a large surface area to enhance the heat dissipation effect, if the heat dissipation conductive pattern and the IC chip are conductively connected, the probability of damage to the IC chip due to ESD increases. End up.

  On the other hand, as described above, the heat dissipation structure disclosed in Patent Document 2 has a structure in which no conductor connection is made between the electrode of the IC chip and the conductive pattern for heat dissipation. More specifically, in FIGS. 3 and 6 of Patent Document 2, the conductive pattern for heat dissipation and the chip electrode are electrically insulated, and the conductive pattern for heat dissipation is opposed across one side of the rectangular chip. It has been shown to form. This structure has an advantage that it is easy to avoid damage to the IC chip due to ESD, and is considered to be effective in a case where a conductor cannot be connected between the electrode of the IC chip and the conductive pattern for heat dissipation.

  However, in the heat dissipation structure disclosed in Patent Document 2, the IC chip and the heat dissipation conductive pattern are arranged so as to be in physical contact without contact between the IC chip electrode and the heat dissipation conductive pattern. The structure (FIG. 6 of Patent Document 2) is considered to be difficult to adopt in practice. This is especially true in flip chip mounting (face-down mounting) where the IC chip surface on which the functional circuit and the electrodes are formed is directed to the wiring board side. Many electrode pads are often placed around the periphery of an IC chip that requires miniaturization from the standpoint of ensuring connection stability. Physically dissipate conductive patterns and IC chips by avoiding electrodes. It is usually difficult to make contact.

  On the other hand, among the heat dissipation structures disclosed in Patent Document 2, when attention is paid to the structure (FIG. 3 of Patent Document 2) in which the IC chip and the heat dissipation conductive pattern are physically separated, the rectangular IC The length of the interface between the chip and the conductive pattern for heat dissipation is at most about the length of the short side of the IC chip. Therefore, heat conduction from the IC chip to the heat radiation conductive pattern is not sufficient, and the temperature of the IC chip rises, and the temperature gradient around the IC chip may be increased.

  In other words, in the heat dissipation structure of the semiconductor device disclosed in Patent Documents 1 and 2, the heat conduction from the IC chip to the heat dissipation conductive pattern is insufficient when the conductor connection between the electrode of the IC chip and the heat dissipation conductive pattern is not possible. There is a problem.

One embodiment of the present invention is a semiconductor device including a wiring substrate having a conductive pattern formed on at least one main surface, and an IC chip mounted on the wiring substrate. The IC chip has a plurality of electrodes for conductor connection with the wiring board.
The conductive pattern includes a lead wiring pattern and a heat dissipation pattern. The lead-out wiring pattern is connected to at least one of the plurality of electrodes via a conductor. The heat radiation pattern is physically separated from both the IC chip and the lead-out wiring pattern, and has a larger surface area than the lead-out wiring pattern.
Further, the lead-out wiring pattern and the heat dissipation pattern are arranged to face each other with a gap therebetween, and the shapes of the portions where the lead-out wiring pattern and the heat dissipation pattern are opposed to each other have a concavo-convex shape. Are arranged so as to mesh with each other through the gap.

  According to one embodiment of the present invention described above, heat can be efficiently extracted from the IC chip by the conductive lead wiring pattern that is conductively connected to the electrode of the IC chip. In addition, since the concave and convex shapes of the lead-out wiring pattern and the heat dissipation pattern are arranged so as to engage with each other through the gap, the total extension of the gap can be made sufficiently long, and the space between the lead-out wiring pattern and the heat dissipation pattern can be increased. The thermal resistance is reduced. Therefore, the thermal resistance from the IC chip to the heat radiation pattern can be lowered, and the heat radiation effect can be enhanced. The total extension in the length direction of the gap can be easily made longer than the length of the short side of the IC chip.

  According to the above-described aspect of the present invention, even when the conductor of the IC chip electrode and the heat radiation pattern cannot be connected, the thermal resistance between the IC chip and the heat radiation pattern is lowered and the heat radiation effect is enhanced. Can do.

It is a top view which shows typically the structure of the semiconductor device concerning Embodiment 1 of invention. FIG. 2 is a plan view schematically illustrating an example of an electrode layout of an IC chip included in the semiconductor device illustrated in FIG. 1. FIG. 2 is an enlarged plan view showing the periphery of a lead-out wiring pattern and a heat dissipation pattern included in the semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram in the cutting line AA of FIG. FIG. 2 is a semiconductor device plan view and a temperature distribution graph for explaining a heat dissipation effect of the semiconductor device shown in FIG. 1. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a figure which shows the modification of a lead-out wiring pattern and the pattern for thermal radiation. It is a top view which shows typically the structure of the semiconductor device concerning Embodiment 2 of invention. FIG. 13 is an enlarged plan view showing the periphery of a lead-out wiring pattern and a heat dissipation pattern included in the semiconductor device shown in FIG. 12.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
The semiconductor device according to the present embodiment is a tape carrier package (TCP), more specifically, a TCP equipped with a driver IC for driving a liquid crystal display panel. FIG. 1 is a schematic plan view of a TCP 1 according to the present embodiment. The TCP 1 includes a flexible wiring board 10 and an IC chip 11. The wiring substrate 10 has a structure in which a conductive pattern is formed of a copper foil or the like on a flexible insulating film such as a polyimide film. This conductive pattern includes an input signal wiring pattern 12, an output signal wiring pattern 13, a lead wiring pattern 14, and a heat dissipation pattern 15. A plurality of sprocket holes 100 formed at equal intervals on both ends of the wiring board 10 are used for transporting and positioning the carrier tape before the TCP 1 is cut out.

  The IC chip 11 is flip-chip mounted on the main surface of the same wiring substrate 10 on which the conductive pattern is formed. The IC chip 11 includes a plurality of first electrodes for inputting / outputting power, display data, and control signals to / from an external device (specifically, an input-side display controller, an output-side liquid crystal display panel, or the like). 111, and usually a plurality of second electrodes 112 that are not connected to an external device and are mainly used for securing connection stability and heat dissipation.

  FIG. 2 is a plan view showing a layout example of the electrodes 111 and 112 formed on the main surface of the IC chip 11. In the example of FIG. 2, a plurality of first electrodes 111 are arranged along the long side of the rectangular main surface of the IC chip 11. A plurality of second electrodes 112 are disposed along the short side of the main surface of the IC chip 11. Each of the plurality of first electrodes 111 is joined to the input signal wiring pattern 12 or the output signal wiring pattern 13 by a conductor bump (Au bump, solder bump, etc.). Further, each of the plurality of second electrodes 112 is joined to the lead-out wiring pattern 14 by a conductor bump. Note that this arrangement is merely an example, and the arrangement of the second electrode 112 is not limited to the short side, and may be arranged on the long side or both.

  Returning to FIG. The input signal wiring pattern 12 and the output signal wiring pattern 13 are a power source, display data, control signal, etc. between the IC chip 11 and an external device (specifically, an input-side display controller, an output-side liquid crystal display panel, etc.) Used to input / output Although not shown in FIG. 1, the input signal wiring pattern 12 includes a plurality of fine input wirings, and the output signal wiring pattern 13 includes a plurality of fine output wirings.

  The lead wiring pattern 14 is conductively connected to at least one of the first electrode 111 or the second electrode 112. The heat radiation pattern 15 is physically separated from all of the IC chip 11, the signal wiring patterns 12 and 13, and the lead wiring pattern 14, and has a larger surface area than the lead wiring pattern 14. Furthermore, the lead-out wiring pattern 14 and the heat radiation pattern 15 are arranged to face each other with a gap therebetween. The portions of the lead-out wiring pattern 14 and the heat radiation pattern 15 facing each other have a concavo-convex shape, and are arranged so that the concavo-convex shapes are engaged with each other through a gap. In other words, the shape of the boundary line of the portion where the lead-out wiring pattern 14 and the heat radiation pattern 15 face each other is an uneven type. The shape of this boundary line can also be called a wave shape, a zigzag shape, a meandering shape, or a star shape.

  FIG. 3 is an enlarged view showing the periphery of the lead-out wiring pattern 14 and the heat radiation pattern 15 located on the right side of the IC chip 11 shown in FIG. In the example of FIG. 3, the lead-out wiring pattern 14 is composed of five lead-out wirings 141 to 145 that are separated from each other. FIG. 4 is a schematic cross-sectional view taken along a cutting line AA in FIG. In FIG. 4, the sealing resin is not shown. As shown in FIG. 4, the lead wiring 145 is formed on the flexible insulating film 101 and joined to the electrode 112 by the conductor bump 113. Other lead wires 141 to 144 are also joined to the IC chip 11 by the conductor bumps 113 in the same manner as the lead wires 145.

  Furthermore, as shown in FIG. 3, the lead wires 141 to 145 are arranged so as to radially expand from the short side of the IC chip 11. The ends of the lead wires 141 to 145 that spread radially correspond to the convex portions of the lead wire pattern 14. Further, the heat radiation pattern 15 is disposed so as to surround the leading end portions of the lead-out wirings 141 to 145 through the gap 16. In other words, the lead-out wirings 141 to 145 are arranged so as to erode inside the heat radiation pattern 15. More specifically, the protrusions 151 to 156 of the heat radiation pattern 15 extend between the lead wires 141 to 145, between the chip 11 and the wire 141, and between the chip 11 and the wire 145. .

  In this manner, the opposing portions of the lead-out wiring pattern 14 (lead-out wirings 141 to 145) and the heat radiation pattern 15 are formed in a concavo-convex shape, and the opposing portions are arranged to mesh with each other via the gap 16, thereby The length of the portion where 14 and 15 are opposed (in other words, the length of the boundary line or the length of the gap 16) can be increased. The gap 16 that is an insulating film has a lower thermal conductivity than the patterns 14 and 15 formed of a conductor such as copper or aluminum, and thus increases the thermal resistance at the boundary between the patterns 14 and 15. However, by making the total extension of the gap 16 in the length direction sufficiently long, the thermal resistance between the lead-out wiring pattern 14 and the heat radiation pattern 15 can be lowered. It is easy to make the total extension of the gap 16 in the length direction longer than the length of the short side of the IC chip 11. In other words, when the conductor connection between the IC chip 11 and the heat radiation pattern 15 cannot be established, the heat radiation structure of the present embodiment is the heat radiation structure of Patent Document 2 (the length of the interface between the IC chip and the heat radiation conductive pattern is opposite). It can be expected that a higher heat dissipation effect is obtained compared to the length of the short side of the IC chip.

  Hereinafter, the heat radiation effect obtained by the layout of the lead-out wiring pattern 14 and the heat radiation pattern 15 described in the present embodiment will be described with reference to FIGS. FIG. 5A is a plan view illustrating the layout of the patterns 14 and 15 shown in FIG. 3 with the addition of isotherms L1 to L8. FIG. 5B is a graph showing the temperature distribution along the X axis of FIG. On the other hand, FIG.5 (c) is a top view regarding the comparative example in case the boundary line of the patterns 14 and 15 is not uneven | corrugated shape. FIG. 5D is a graph showing the temperature distribution along the X axis of FIG. In addition, the structure shown in FIG.5 (c) was devised for the comparison with TCP1 by the inventor of this application, and is not a well-known structure.

  As is clear from the comparison between FIG. 5B and FIG. 5D, according to the present embodiment, heat is efficiently extracted from the IC chip 11 to the heat radiation pattern 15, so that the temperature of the IC chip 11 is increased. Decreases, and the temperature of the heat radiation pattern 15 increases. Thereby, as shown in FIG. 5B, the temperature gradient in the vicinity of the boundary P1 of the IC chip 11 becomes gentle.

  As shown in FIGS. 5C and 5D, since the temperature gradient in the vicinity of the IC chip 11 that is a heat source is steep, it is efficient to make the temperature gradient gentler. It leads to heat dissipation. As shown in FIGS. 1 and 3, by forming the lead-out wiring pattern 14 so as to expand radially as the distance from the IC chip 11 increases, the heat dissipation effect can be improved. This is because the radial wiring layout is along the heat flow diffusion direction. By arranging the radial lead-out wiring pattern 14 along the heat flow diffusion direction in the vicinity of the IC chip 11, as shown in FIGS. 5A and 5B, the temperature gradient in the vicinity of the IC chip 11 is moderated. Thus, efficient heat dissipation can be performed.

  Further, by adopting the radial lead-out wiring pattern 14, the total area of the lead-out wiring pattern 14 can be reduced. For this reason, the radial lead-out wiring pattern 14 is particularly effective when there is a concern about the destruction of the IC chip 11 due to ESD.

  According to the present embodiment, even when the heat radiation pattern 15 cannot be conductively connected to the IC chip 11 due to ESD countermeasures or restrictions on the electrode layout of the IC chip 11, the gap between the IC chip 11 and the heat radiation pattern 15 can be reduced. The thermal resistance can be lowered and the heat dissipation effect can be enhanced. Further, by making the total extension of the gap 16 sufficiently long, it is possible to obtain a heat dissipation effect equivalent to the case where the IC chip 11 and the heat dissipation pattern 15 are conductively connected.

  In addition, the shape of the lead-out wiring pattern 14 shown in FIGS. 1, 3 and 5 is only an example. For example, as shown in FIG. 6, the lead wiring pattern 14 may be an integral conductive pattern in which lead wirings 141 to 145 are connected by a central portion 146 when electrical connection is allowed.

  Furthermore, modified examples of the lead wiring pattern 14 are shown in FIGS. 7A to 7D and FIGS. 8A to 8E. FIGS. 7A to 7D show modifications of the lead wiring pattern 14 having the lead wirings 141 to 145 extending radially. FIG. 7A shows an example in which each of the lead wires 141 to 145 shown in FIG. 3 is branched to further increase the boundary length. FIG. 7B shows an example in which each of the lead wires 141 to 145 has a shape that gradually widens toward the tip. FIGS. 7C and 7D are examples in which the leading edge of each of the lead-out wirings 141 to 145 is made thicker than the root and the boundary length is made long by making the edge corrugated.

  8A to 8E show modifications of the lead wiring pattern 14 having non-radiating lead wirings 141 to 145. FIG. The non-radiation type lead-out wiring pattern 14 is effective when the radiation-type lead-out wiring pattern 14 cannot be adopted due to layout constraints, although it may be inferior to the radiation type in terms of heat flow diffusion characteristics.

  Further, the heat radiation pattern 15 may be in an electrically floating state, or may be given any predetermined potential. For example, the heat radiation pattern 15 may be grounded. In the heat dissipation structure shown in the present embodiment, the lead-out wiring pattern 14 and the heat dissipation pattern 15 are physically separated. Therefore, the heat dissipation structure can be used even when a predetermined potential is applied to the heat dissipation pattern 15.

  Further, the heat radiation electrode 112 may be connected to a power supply potential, a ground potential, or the like in the IC chip 11. In other words, the lead-out wiring pattern 14 (lead-out wirings 141 to 145) may be electrically connected to an external device via the internal wiring of the IC chip 11. In the heat dissipation structure shown in the present embodiment, the wirings 141 to 145 constituting the lead-out wiring pattern 14 and the lead-out wiring pattern 14 and the heat dissipation pattern 15 are physically separated. Therefore, the heat dissipation structure can be used even when a predetermined potential is applied to each of the wirings 141 to 145 constituting the lead wiring pattern 14.

  In the above description, the case where the heat radiation pattern 15 is one island pattern has been described. However, the heat radiation pattern 15 may be divided into a plurality of island patterns.

  By the way, one of the features of the heat dissipation structure described in the present embodiment is that the boundary line between the lead-out wiring pattern 14 and the heat dissipation pattern 15 is an uneven type (including a wave shape, a zigzag shape, a meandering shape, or a star shape). This is the point. This layout can be applied universally to a place where the lead wiring pattern 14 and the heat radiation pattern 15 are arranged close to each other.

  That is, as shown in FIG. 9 (a), as shown in FIG. 9 (b), the boundary line (L21) between the lead-out wiring pattern 14 and the heat radiation pattern 15 facing each other with a gap is made straight. The boundary line (L22) between the patterns 14 and 15 may be an uneven type. Even when the lead-out wiring pattern 14 includes a plurality of fine wirings (FIG. 10A), by changing the length of the fine wirings into a comb-tooth shape, the boundary line between the patterns 14 and 15 ( L22) may be a concave-convex type (FIG. 10B). Further, as shown in FIG. 11 (a), even when both the lead-out wiring pattern 14 and the heat radiation pattern 15 include fine wiring, the patterns 14 are formed by engaging each other through a gap in a comb shape. And the boundary line (L22) of 15 and 15 is preferably a concave-convex type (FIG. 11B).

<Embodiment 2 of the Invention>
In this embodiment, application examples of the conductive pattern layout shown in FIGS. 9 to 11 will be described. FIG. 12 is a schematic plan view of the TCP 2 according to the present embodiment. In the example of FIG. 12, dummy wirings (dummy leads) are formed in the region 21 where the signal input / output patterns 13 and 14 are not formed. The formation of the dummy wiring in the blank portion is generally performed in a semiconductor device such as TCP using a flexible wiring board. These dummy wirings also contribute to heat dissipation of the IC chip 11.

  Further, in the example of FIG. 2, the folded wiring 24 is formed in the region 21. The folded wiring 24 is a folded connection between two electrodes 112 that are not connected to an external device among the electrodes of the IC chip 11. The folded wiring 24 is provided for power supply, for example. When such a folded wiring 24 exists, the dummy wiring is divided by the folded wiring 24. In the present embodiment, the layout of the conductive pattern shown in FIGS. 9 to 11 is used in order to improve the thermal conductivity between the divided dummy wiring and the folded wiring 24.

  FIG. 13 is an enlarged plan view schematically showing the periphery of the folded wiring 24 provided in the region 21. The folded wiring 24 is not connected to an external device but is conductively connected to the electrode 112 of the IC chip 11. That is, the folded wiring 24 corresponds to the lead wiring pattern 14. The dummy wiring group 25 is physically separated from all of the IC chip 11, the signal wiring patterns 12 and 13, and the folded wiring 24 (corresponding to the lead wiring pattern 14), and has a larger surface area than the folded wiring 24. Have That is, the dummy wiring group 25 corresponds to the heat radiation pattern 15. The dummy wiring group 26 is connected to a dummy electrode provided on the IC chip 11 via a conductor bump in order to secure connection stability with the flexible wiring board 10. The dummy wiring group 26 may not be conductively connected to the electrode of the IC chip 11 in some cases.

  As shown in FIG. 13, the opposing portions of the folded wiring 24 (corresponding to the lead-out wiring pattern 14) and the dummy wiring group 25 (corresponding to the heat radiation pattern 15) are formed in a concavo-convex shape and meshed through a gap. Thus, the thermal resistance can be reduced. Similarly, the boundary line between the dummy wiring group 26 on the IC chip 11 side and the folded wiring 24 may be an uneven type. Thereby, the thermal resistance from the IC chip 11 to the dummy wiring group 25 can be reduced.

  In the first and second embodiments of the present invention described above, the electrode 112 is provided separately from the electrode 111 connected to the external device, and is not connected to the external device, and is mainly used for ensuring connection stability and heat dissipation. The configuration in which the lead wiring pattern is conductor-connected has been described. However, at least one of the input signal wiring pattern 12 and the output signal wiring pattern 13 connected to the electrode 111 connected to the external device may be transferred to the heat radiation pattern 15 via a gap. In other words, at least one of the input signal wiring pattern 12 and the output signal wiring pattern 13 may be used also as a lead wiring pattern.

  As described above, the TCPs 1 and 2 are disposed so that the lead-out wiring pattern 14 and the heat radiation pattern 15 are engaged with each other through a gap, thereby electrically connecting the lead-out wiring pattern 14 and the heat radiation pattern 15. The thermal resistance can be lowered without any problems. Therefore, the input signal wiring pattern 12 and the output signal wiring pattern 13 that are not allowed to be electrically connected to the heat radiation pattern 15 can be used as the lead wiring pattern 14. As described above, the heat dissipation structure using the lead-out wiring pattern 14 and the heat-dissipation pattern 15 can also be used as the lead-out wiring pattern 14 because the signal wiring patterns 12 and 13 and the like connected to an external device can be used. .

  Further, the heat dissipation structure of the semiconductor device described in the first and second embodiments of the present invention is a semiconductor device using a flexible wiring board, in particular, the conductive layer formed on the insulating film is a single layer, and is conductive. This is particularly effective in a TCP having a structure in which an IC chip is flip-chip mounted on the same main surface as the layer. This mounting method is called COF (Chip On Film). The COF does not require drilling a portion of the insulating film that faces the IC chip, and does not require the use of flying leads. The COF, in which the conductive layer is formed only on the main surface of the film and the IC chip is mounted on this main surface, is easy to cope with fine pitch, and also secures its flexibility to reduce the manufacturing cost of TCP. Therefore, it is a commonly used package form. On the other hand, the TCP having such a structure has severe restrictions on the layout of the conductive pattern and easily causes an increase in IC chip temperature. However, by using the heat dissipation structure shown in the first and second embodiments, the heat dissipation effect when the conductor connection between the IC chip 11 and the heat dissipation pattern 15 cannot be made can be enhanced.

  However, the heat dissipation structure of the semiconductor device described in the first and second embodiments can be applied to a semiconductor device using a flexible wiring board other than TCP. The wiring layer (conductor layer) of the flexible wiring board may be a plurality of layers. Moreover, a conductor layer may be formed on both main surfaces of the flexible wiring board. Further, the method of mounting the IC chip 11 on the wiring board 10 is not limited to the above-described flip chip mounting. For example, it can be applied to TAB (Tape Automated Bonding) mounting. Further, the present invention is not limited to a flexible wiring board, and can be applied to a semiconductor device using a rigid wiring board.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

1, 2 Tape carrier package (TCP)
10 Wiring board 11 IC chip (Driver IC)
12 Input signal wiring pattern 13 Output signal wiring patterns 14, 24 Drawer wiring patterns 15, 25 Heat radiation pattern 21 Dummy wiring region 24 Folded wiring (leading wiring pattern)
25 Dummy wiring group (Pattern for heat dissipation)
26 Dummy wiring group 16 Gap 100 Sprocket hole 101 Insulating film 111 Electrode (for signal input / output)
112 electrodes (for heat dissipation)
113 Conductor bumps 141-145 Lead-out wiring 151-156 Protrusions L21, L22 Pattern boundary lines L1-L8 Isotherm

Claims (12)

A rectangular semiconductor chip;
A wiring board on which the semiconductor chip is mounted,
The semiconductor chip includes a surface, a first long side, a second long side opposite to the first long side, a first short side intersecting the first and second long sides, and the first short side. A plurality of bump electrodes formed on the surface, and a second short side that intersects the first and second long sides,
The plurality of bump electrodes are arranged closer to the first short side than the plurality of first bump electrodes, the plurality of first bump electrodes arranged along the first long side, and the first length. A plurality of second bump electrodes arranged along a side, a plurality of third bump electrodes arranged closer to the second short side than the plurality of first bump electrodes and arranged along the first long side Including bump electrodes,
The wiring board includes a main surface on which the semiconductor chip is mounted, a first side that is disposed outside the semiconductor chip and extends substantially parallel to the first long side of the semiconductor chip, A second side disposed outside and extending substantially parallel to the second long side of the semiconductor chip, and a plurality of wiring groups,
Each of the plurality of wiring groups is formed on the main surface,
In the semiconductor chip, the front surface of the semiconductor chip and the main surface of the wiring board are opposed to each other, and the first long side of the semiconductor chip and the first side of the wiring board are in plan view. Mounted on the wiring board so as to be disposed between the second long side,
The plurality of wiring groups include a first wiring group, a second wiring group, and a third wiring group,
The first wiring group includes a plurality of first wirings for heat dissipation, and one end of the plurality of first wirings is electrically and mechanically connected to each of the plurality of first bump electrodes. And
The second wiring group includes a plurality of second wirings for signals, and one end portions of the plurality of second wirings are electrically connected to the plurality of second bump electrodes,
The third wiring group includes a plurality of third wirings for signals, and one end of the plurality of third wirings is electrically connected to each of the plurality of third bump electrodes,
In a plan view, the plurality of first wirings extend from the first long side of the semiconductor chip toward the first side of the wiring substrate, and the other ends of the plurality of first wirings. Each is terminated between the first long side of the semiconductor chip and the first side of the wiring board,
In plan view, the plurality of second and third wirings extend from the first long side of the semiconductor chip toward the first side of the wiring board,
In plan view, each of the other ends of the plurality of first wirings is closer to the first long side of the semiconductor chip than the first side of the wiring board,
In plan view, each of the plurality of second ends of the plurality of second and third wirings is closer to the first side of the wiring board than the first long side of the semiconductor chip,
Each of the plurality of first wirings is shorter than each of the plurality of second and third wirings,
The semiconductor device, wherein the second and third wiring groups are arranged so as to surround the plurality of first wirings in plan view. The semiconductor device according to claim 1,
The first wiring group further includes a plurality of dummy wirings for heat dissipation,
In plan view, the second and third wiring groups are arranged so as to surround the plurality of dummy wirings,
The semiconductor device, wherein the plurality of dummy wirings are electrically separated from the semiconductor chip and the plurality of first, second, and third wirings. The semiconductor device according to claim 2,
In plan view, a plurality of one end portions of the plurality of dummy wires are opposed to the other end portions of the plurality of first wires,
In plan view, the other ends of the plurality of second and third wirings are different from the other ends of the plurality of dummy wirings to a region near the first side of the wiring board. An extended semiconductor device. The semiconductor device according to claim 1,
The second wiring group has a second group wiring closest to the third wiring group,
The third wiring group has a third group wiring closest to the second wiring group,
The distance between the second group wiring and the third group wiring in the vicinity of the first long side of the semiconductor chip is the second group wiring and the third group wiring in the vicinity of the first side of the wiring board. A semiconductor device wider than the interval. The semiconductor device according to claim 1,
The second wiring group has a second group wiring closest to the third wiring group,
The third wiring group has a third group wiring closest to the second wiring group,
Each of the second and third group wirings extends from the first long side of the semiconductor chip so as to approach each other from the first long side of the semiconductor chip toward the first side of the wiring board. Existing semiconductor device. The semiconductor device according to claim 1,
The plurality of bump electrodes includes a plurality of fourth bump electrodes arranged along the second long side,
The plurality of wiring groups includes a fourth wiring group;
The fourth wiring group includes a plurality of fourth wirings for signals, and one end portions of the plurality of fourth wirings are electrically connected to the plurality of fourth bump electrodes,
The plurality of fourth wirings extend from the second long side of the semiconductor chip toward the second side of the wiring substrate, and the other ends of the plurality of fourth wirings are connected to the wirings A semiconductor device located in the vicinity of the second side of the substrate. The semiconductor device according to claim 6.
The wiring board includes a third side intersecting with the first side and the second side, and a side opposite to the third side.
And has a fourth side intersecting the first side and the second side,
The plurality of bump electrodes are arranged along the second long side and are arranged closer to the first short side than the plurality of fourth bump electrodes, and the fifth bump electrodes, Including a plurality of sixth bump electrodes disposed along two long sides and disposed closer to the second short side than the plurality of fourth bump electrodes;
The plurality of wiring groups include a fifth wiring group for signals in which a plurality of one end portions are electrically connected to the plurality of fifth bump electrodes, and a plurality of one end portions of the plurality of wiring groups. A sixth wiring group for signals electrically connected to the six bump electrodes,
The fifth and sixth wiring groups extend from the second long side of the semiconductor chip toward the second side of the wiring board, and further extend toward the first side of the wiring board. Bend like
In plan view, the plurality of other ends of the fifth and sixth wiring groups are located in a region in the vicinity of the first side of the wiring board different from the plurality of other ends of the plurality of first wirings. A semiconductor device that is positioned and located closer to the third side and the fourth side than the other ends of the plurality of first wirings . The semiconductor device according to claim 7,
The semiconductor device, wherein the second, third, fifth, and sixth wiring groups are a plurality of wirings for output signals, and the fourth wiring group is a plurality of wirings for input signals.

The semiconductor device according to claim 2,
The semiconductor device, wherein the semiconductor chip does not overlap the plurality of dummy wirings in plan view. The semiconductor device according to claim 2,
The semiconductor device, wherein the plurality of dummy wirings are electrically floating. The semiconductor device according to claim 1,
The wiring substrate is a semiconductor device comprising a tape substrate made of an insulating film. The semiconductor device according to claim 1,
In plan view, the second and third wiring groups are each surrounded by the second wiring group, the third wiring group, and the semiconductor chip at the other ends of the plurality of first wirings. A semiconductor device that surrounds the plurality of first wirings so as to be disposed in the region.

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