JP5650072B2 - Frequency / time synchronization method and frequency / time synchronization apparatus - Google Patents

Description

  The present invention relates to a technique for realizing frequency synchronization and time synchronization between devices connected via a packet network.

  In order to provide high-quality communications and services in a communication system connected via a packet network, time synchronization that matches the absolute time between node devices and frequency synchronization that matches the operating speed in each device are important technologies. It is. In general, PTP (Precision Time Protocol) is known as a protocol for performing highly accurate time synchronization between node devices connected via a packet network (see, for example, Non-Patent Document 1).

  However, in the PTP technology, if the frequency of the operation clock of the receiving device and the operation clock of the transmitting device is not synchronized, there is a possibility that the clock frequency may shift during the period when the reference PTP packet is not received. There was a problem that the accuracy of time synchronization between the transmission-side device and the reception-side device deteriorated. On the other hand, Synchronous Ethernet (registered trademark) is known as a technique for realizing frequency synchronization on a packet network (see, for example, Non-Patent Documents 2, 3, and 4).

IEEE Std 1588TM-2008 IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems) ITU-T G.8261 Timing and synchronization aspects in packetnetworks ITU-T G.8262 Timing characteristics of synchronous Ethernet equipment slave clock (EEC) ITU-T G.8264 Distribution of timing information through packet networks

  However, since the PTP technology and the synchronous Ethernet technology are independent technologies, there is a problem that the overhead of each device increases when both are realized.

  In view of the above problems, the object of the present invention is to superimpose a packet of time information used in PTP on a clock signal of Synchronous Ethernet (registered trademark) that realizes frequency synchronization. To provide a frequency / time synchronization method and a frequency / time synchronization apparatus capable of simultaneously realizing frequency synchronization and time synchronization.

The frequency / time synchronization method according to the present invention is a frequency / time synchronization method in which frequency synchronization and time synchronization are performed between devices connected via a packet network. A time synchronization packet including time information synchronized with the standard time is superimposed on a signal including the signal and transmitted through two paths of the active system and the standby system, and frequency information and time are transmitted from the two paths of the active system and the standby system. Each lower-level device that receives information has a frequency-synchronized oscillation unit for each path, and the frequency-synchronized oscillation unit of each path refers to the input time information, and the pulse of the clock signal is set at the set time. The phase of the input clock signal is adjusted so that the frequency of the standby system is changed, and the frequency synchronization generation of the standby system is performed at the time when the clock signal output by the frequency synchronization oscillator of the active system changes. And switches the part.

  Thereby, the phase of the clock which a some frequency synchronous transmission part outputs can be synchronized. And when one of the frequency synchronization transmitters breaks down, the occurrence of a phase jump when switching to another frequency synchronization transmitter can be prevented, so that switching without interruption is possible.

  Further, when transmitting the signal from a plurality of lower-level devices to the same service node, delaying the timing of transmitting the signal according to the delay time from the lower-level device to the service node. Features.

  As a result, frequency synchronization can be achieved at the service node that receives signals from a plurality of devices at different locations, so that it is possible to perform uninterruptible switching when redundancy is established between the plurality of devices.

The frequency / time synchronization apparatus according to the present invention is a frequency / time synchronization apparatus that performs frequency synchronization and time synchronization between apparatuses connected via a packet network, and includes a packet including time information on a signal including frequency information. Superimposed and transmitted through two paths of the active system and the standby system, and the signal including the frequency information and the packet including the time information are transmitted from the communication destination apparatus from the two paths of the active system and the standby system A network connection unit for receiving, and two frequency-synchronized oscillation units that are arranged for each path of the active system and the standby system and generate a clock signal synchronized with the frequency information received by the network connection unit, and each path The frequency-synchronized oscillation unit refers to the input time information, adjusts the phase of the input clock signal so that the pulse of the clock signal changes at the set time, and The number locked oscillation unit, and switches to the frequency locked oscillation of a standby system at time a clock signal to be output is changed.

  Thereby, the phase of the clock which a some frequency synchronous transmission part outputs can be synchronized. And when one of the frequency synchronization transmitters breaks down, the occurrence of a phase jump when switching to another frequency synchronization transmitter can be prevented, so that switching without interruption is possible.

  In addition, when transmitting the signal from a plurality of the frequency / time synchronizers to the same service node, the timing for transmitting the signal according to the delay time from each frequency / time synchronizer to the service node is set. Further, a delay unit for delaying is provided.

  As a result, frequency synchronization can be achieved at the service node that receives signals from a plurality of devices at different locations, so that it is possible to perform uninterruptible switching when redundancy is established between the plurality of devices.

  The frequency / time synchronization method and the frequency / time synchronization apparatus according to the present invention can realize time synchronization and frequency synchronization with a single device. Compared to the case where time synchronization packets are periodically received and time synchronization is performed by superimposing and transmitting and receiving packets including time information on signals including frequency information distributed from standard frequency devices. Highly accurate time synchronization can be realized.

  Furthermore, it is possible to monitor the quality of time accuracy by accumulating past time information that is periodically received and performing statistical analysis.

  In addition, by providing redundancy to the frequency synchronization / oscillation unit and synchronizing the phase of the clock signal, switching without instantaneous interruption can be realized.

  Alternatively, instantaneous switching can be realized by combining delay times for service nodes that receive signals from a plurality of frequency / time synchronizers at different locations.

It is a figure which shows an example of a time synchronous sequence. It is a figure which shows the structural example which implement | achieves frequency synchronization. It is a figure which shows the example of whole structure of the frequency / time synchronizing method and frequency / time synchronizing apparatus which concern on this embodiment. 3 is a diagram illustrating a basic configuration example of a frequency / time synchronization apparatus 172. FIG. 3 is a diagram illustrating a basic configuration example of a frequency / time synchronization apparatus 201. FIG. 3 is a diagram illustrating a basic configuration example of a frequency / time synchronization apparatus 301. FIG. It is a figure which shows the example of monitoring of the time precision by a statistical process. It is a figure which shows the structural example of the frequency and time synchronizer 401 corresponding to uninterruptible switching. It is a figure which shows the system configuration example in the case of respond | corresponding to uninterruptible switching with a some apparatus.

  Embodiments of a frequency / time synchronization method and a frequency / time synchronization apparatus according to the present invention will be described below with reference to the drawings. The frequency / time synchronization method according to the present embodiment can achieve frequency synchronization and time synchronization between node devices connected via a packet network. In the present embodiment, a case where the slave device synchronizes with the standard frequency and standard time of the master device will be described.

  First, a time synchronization protocol (PTP) known as a method for synchronizing time between a master device and a slave device will be described. FIG. 1 is a diagram illustrating a time synchronization sequence when time synchronization is performed between the master device 101 and the slave device 102.

  In FIG. 1, four types of time stamps (T 1, T 2, T 3, T 4) of Sync message, Follow Up message, Delay Req message, and Delay Resp message are transmitted and received between the master device 101 and the slave device 102. Here, time T1 indicates the time when the master device 101 transmits the Sync message to the slave device 102, and time T2 indicates the time when the slave device 102 receives the Sync message from the master device 101. Time T3 indicates the time when the slave device 102 transmits the Delay Request message to the master device 101, and time T4 indicates the time when the master device 101 receives the Delay Request message from the slave device 102.

  In the time synchronization sequence of FIG. 1, first, a delay time when transmitting / receiving a message from the master device 101 to the slave device 102 is obtained. First, the master device 101 transmits a Sync message, and the slave device 102 records the reception time (T2) of the Sync message. Thereafter, the master device 101 sets the time (T1) at which the Sync message is transmitted as a Follow_up message and transmits it to the slave device 102. Then, the slave device 102 uses the transmission time T1 set in the Follow Up message and the previously recorded reception time T2, and the delay time (T2−T2) when the master device 101 transmits / receives the Sync message to the slave device 102. T1) can be obtained.

  Next, a delay time when transmitting / receiving a message from the slave device 102 to the master device 101 is obtained. First, a Delay Request message is transmitted from the slave device 102 to the master device 101. At the time of transmission, the slave device 102 records the time (T3) at which the Delay Request message is transmitted. On the other hand, the master device 101 acquires the time (T4) at which the Delay Request is received, sets the time (T4) in the Delay Response message, and returns it to the slave device 102. The slave device 102 receives the Delay Response message and transmits it from the slave device 102 to the master device 101 using the reception time (T4) set in the Delay Response message and the previously recorded transmission time (T3). The delay time (T4-T3) of the Delay Request message can be obtained.

Using the four pieces of time information (T1, T2, T3, T4) acquired in this way, the offset time Offset (average of delay times during transmission / reception) is calculated by Equation (1).
Offset = ((T2-T1) + (T4-T3)) / 2 ... Equation (1)
Here, the time synchronization sequence is a sequence performed between the master device 101 and the slave device 102 periodically or during a specific period set in advance, and the time stamp information received from the master device 101 thereafter is expressed by equation (1). By adding the obtained offset time Offset, time synchronization between the master device 101 and the slave device 102 can be corrected and time synchronization can be performed. For example, the time obtained by adding the offset time Offset obtained by Expression (1) to the transmission time included in the message received from the master device 101 is set in the device clock of the slave device 102.

  The time synchronization method using PTP is as described above. Since the slave device 102 does not receive the PTP packet, the slave device 102 counts the time of the internal clock with the free-running clock held by the slave device 102 itself. There is a problem that the count-up speeds of the time on the device 101 side and on the slave device 102 side are different, and the time synchronization accuracy deteriorates due to the time difference between the two. In order to prevent this, it is necessary to synchronize the clock frequency for counting up the time between the master device 101 and the slave device 102.

  Synchronous Ethernet (registered trademark) is known as a technique for realizing such frequency synchronization in a packet network. Here, in the following description, Synchronous Ethernet (registered trademark) is referred to as SyncE. SyncE can achieve frequency synchronization between the transmission side and the reception side by using a clock component of an Ethernet (registered trademark) signal (hereinafter referred to as an E signal). For example, the SyncE signal transmitted from the transmitting device includes a clock component, and the receiving device extracts the clock component from the received signal and synchronizes the frequency of the clock signal between the devices.

  FIG. 2 is a block diagram showing an overview of SyncE. In FIG. 2, the master device 151 inputs a reference clock signal from the master clock 152 to the local oscillator 153. The local oscillator 153 includes a G.8262EEC 154 and an oscillator 155. A clock signal with high accuracy (for example, about ± 4.6 ppm) synchronized with the reference clock signal is supplied to the SyncE timing device 156 of the SyncE interface circuit (SyncE Line Card). Output. Here, G.8262 is a standard for the clock characteristics of SyncE, and G.8262EEC154 synchronizes the clock signal output from the oscillator 155 with the reference clock signal input from the master clock 152 based on the G.8262 standard. The clock signal output from the G.8262EEC 154 is frequency-multiplied to the drive frequency of the E signal by the SyncE timing device 156, and is supplied to the PHY unit 157 that provides an Ethernet (registered trademark) physical interface. The PHY unit 157 transmits the Ethernet (registered trademark) frame output from the MAC unit 158 by the slave device 152 using the SyncE signal output from the SyncE timing device 156. The MAC unit 158 is a block that performs normal communication using Ethernet (registered trademark), and is connected to a user device or the like.

  On the other hand, in the opposing slave device 152, the PHY unit 159 that provides an Ethernet (registered trademark) physical interface extracts the clock component from the SyncE signal received from the master device 151, and outputs it to the SyncE timing device 160. The MAC unit 161 is a block that performs normal communication using Ethernet (registered trademark), and is connected to a user device or the like.

  The SyncE timing device 160 divides the clock extracted by the PHY unit 159 to a frequency that can be output as the slave clock 165, and then inputs the frequency to the local oscillator 162. The local oscillator 162 includes a G.8262EEC 163 and an oscillator 164, and outputs a high-accuracy (for example, about ± 4.6 ppm) clock signal synchronized with the clock signal output from the SyncE timing device 160 to the outside as a slave clock 165.

  Here, in the case of the existing Ethernet (registered trademark), as shown in FIG. 2 as a conventional example, the local oscillators 154 and 162 of the master device 151 a and the slave device 152 a are like the master device 151 and the slave device 152. In addition, since it is not synchronized with the reference frequency, the frequency accuracy is about ± 100 ppm, and the clock for internal operation of each device is generated. Therefore, the clock frequency cannot be synchronized between the devices.

  Therefore, in this embodiment, in order to achieve highly accurate time synchronization, the time synchronization PTP packet described in FIG. 1 is used, and this PTP packet is superimposed on the frequency synchronization SyncE signal described in FIG. Thus, it is possible to realize high-precision frequency synchronization and time synchronization with a single device by reducing overlapping circuits.

  Next, an outline of a network configuration using the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present embodiment will be described with reference to FIG. In the example of the network 170 in FIG. 3, frequency synchronization of four frequencies / time synchronizers of a frequency / time synchronizer 171, a frequency / time synchronizer 172, a frequency / time synchronizer 173, and a frequency / time synchronizer 174. And time synchronization.

  In FIG. 3, the highest frequency / time synchronizer 171 receives an external time generator PRTC (Primary Reference Time) that receives a standard frequency clock from an external master clock 175 and is traced to the international standard time (UTC). Standard time is acquired from (Clock) 176. The frequency / time synchronizer 171 holds the standard frequency and standard time inside the device, and then sends the frequency information and time information synchronized with the master clock 175 and PRTC 176 to the lower device (slave side) with the SyncE signal and PTP. Use and transfer. Here, in the example of FIG. 3, the direct lower side device of the frequency / time synchronizer 171 (master side) is the frequency / time synchronizer 172 (slave side).

  The lower-level device (frequency / time synchronization device 172) processes the SyncE signal and the PTP packet acquired from the higher-level device, and holds frequency information and time information. Then, the frequency information and time information are transferred to the lower side devices (frequency / time synchronization devices 173 and 174) of the own device (frequency / time synchronization device 172) using the SyncE signal and PTP, and the entire network 170 is transferred. Realizes frequency synchronization and time synchronization.

For time synchronization by PTP, a transmission delay error between the master and the slave can be corrected by having a transmission delay correction function based on the IEEE Std 1588 ^TM -2008 standard.

  Next, an outline of the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present embodiment will be described. FIG. 4 is a diagram showing an outline of the frequency / time synchronizer 172 described in FIG. In FIG. 4, an Ether unit 191 that terminates the Ethernet connection of the frequency / time synchronizer 172 includes a high-precision frequency signal 181 based on the Sync-E signal transmitted from the frequency / time synchronizer 171 of FIG. The PTP packet 182 superimposed on the frequency signal 181 is received. The Ether unit 191 extracts the clock frequency from the Sync-E signal, synchronizes the oscillator 192 to the internal frequency, acquires the time information of the PTP packet superimposed on the Sync-E signal, and acquires the clock 193 device. Synchronize the internal time. Since the clock 193 counts the time based on the clock output from the oscillator 192, the time can be counted up by the clock frequency that is synchronized with the host device even during the period when the PTP packet is not received. . As a result, the frequency / time synchronizer 172 can maintain time synchronization with the frequency / time synchronizer 171 even in a steady state.

  Thereafter, in the Ether unit 194 connected to the lower-level device of the frequency / time synchronization device 172, the PTP in which the device time information output by the clock 193 is added to the Sync-E signal synchronized with the device frequency output by the oscillator 192. A packet is generated, superimposed, and transferred to the lower device side (frequency / time synchronizers 173 and 174 in the example of FIG. 3).

[Configuration example of top-level device]
Next, a configuration example of the highest-level device will be described. FIG. 5 is a block diagram illustrating a configuration example of the highest-level device 201, and corresponds to, for example, the frequency / time synchronization device 171 described in FIG. In FIG. 5, the highest-level device 201 inputs a standard frequency from the working master clock 202 and the standby master clock 203 and receives a standard time from the working PRTC 204 and the standby PRTC 205.

  First, frequency synchronization in the highest device 201 will be described. The active master clock 202 is converted to a required frequency by frequency multiplication unit 206 and the standby master clock 203 is converted to a necessary frequency by frequency multiplication or division in frequency conversion unit 207, and then frequency synchronization / Input to the oscillation unit 209.

  The frequency selection unit 208 selects an active or standby master clock according to a switching command output from the frequency synchronization / oscillation unit 209. The switching command is output, for example, when a failure occurs or when switching from the active master clock 202 to the standby master clock 203 due to maintenance or inspection.

  The frequency synchronization / oscillation unit 209 has a free-running clock 220 such as Rb or a crystal resonator, and generates a clock having a frequency synchronized with the frequency input via the frequency selection unit 208 by feedback control. Output to each part. At this time, the frequency tracking speed with respect to the change of the control data for performing the feedback control is slowed down, and the jitter component of the generated frequency is suppressed. Then, the frequency of the clock output from the frequency synchronization / oscillation unit 209 is multiplied or divided by the frequency conversion units 212 and 213 to a necessary frequency, and then the Ether units 214 and 215 connected to the lower side apparatus. Are supplied respectively.

  On the other hand, for the time information, the standard time is acquired from the working PRTC 204 and the standby PRTC 205, accumulated in the time information accumulation / accuracy monitoring unit 210, and the distribution time oscillation unit 211 having the clock 221 is monitored. For example, the time information accumulation / accuracy monitoring unit 210 sets the accumulated standard time in the clock 221 of the distribution time oscillation unit 211 and supplies the clock frequency output by the frequency synchronization / oscillation unit 209 to the distribution time oscillation unit 211. To do. The distribution time oscillation unit 211 counts the time of the clock 221 set by the time information accumulation / accuracy monitoring unit 210 with the clock frequency output by the frequency synchronization / oscillation unit 209 that is input via the time information accumulation / accuracy monitoring unit 210. The time information of the clock 221 is output to the Ether units 214 and 215.

  The Ether units 214 and 215 operate at the frequency output from the frequency conversion units 212 and 213, store the time information output from the distribution time oscillation unit 211 in the PTP packet, and transmit it to the lower-level device. At this time, the Ether units 214 and 215 superimpose and transmit the PTP packet on the SyncE signal synchronized with the frequency output from the frequency conversion units 212 and 213. The Ether units 214 and 215 include a PTP processing unit 251 that stores time information in the PTP packet and a SyncE processing unit 252 that superimposes the PTP packet on the SyncE signal, as shown in the dotted frame.

  In consideration of a device that wants to acquire a clock signal such as 64 kHz, the frequency converter 216 converts the clock signal to the clock frequency output from the frequency synchronization / oscillation unit 209, and the necessary frequency via the frequency distributor 217. Output to the device.

[Lower device]
Next, a configuration example of the lower-level device will be described. FIG. 6 is a block diagram illustrating a configuration example of the lower-level device 301, which corresponds to, for example, the frequency / time synchronization device 172 described with reference to FIG. In FIG. 6, the lower apparatus 301 receives the PTP packet superimposed on the SyncE signal transmitted from the upper apparatus (frequency / time synchronization apparatus 171) by the Ether unit 302 or the Ether unit 303. The Ether units 302 and 303 include a PTP processing unit 351 that extracts time information from the PTP packet and a SyncE processing unit 352 that extracts the frequency of the SyncE signal, as shown in the dotted frame.

  First, frequency synchronization in the lower apparatus 301 will be described. The SyncE processing unit 352 of the Ether units 302 and 303 extracts the frequency of the SyncE signal, and the frequency conversion units 304 and 305 convert the frequency to a frequency that can be input to the frequency synchronization / oscillation unit 308 by multiplication or division. Here, extraction of the frequency from the SyncE signal uses a method performed by a general apparatus corresponding to SyncE.

  Similar to the frequency selection unit 208 in FIG. 5, the frequency selection unit 307 selects the clock frequency output from the Ether unit 302 or the Ether unit 303 according to the switching command output from the frequency synchronization / oscillation unit 308.

  Similar to the frequency synchronization / oscillation unit 209 in FIG. 5, the frequency synchronization / oscillation unit 308 has a free-running clock 320 such as Rb or a crystal resonator, and has a frequency input via the frequency selection unit 307 by feedback control. A clock having a synchronized frequency is generated and output to each unit in the device itself. At this time, similarly to the frequency synchronization / oscillation unit 209, the frequency tracking speed with respect to the change of the control data for performing the feedback control is slowed down, and the jitter component of the generated frequency is suppressed. Then, the frequency of the clock output from the frequency synchronization / oscillation unit 308 is multiplied or divided by the frequency conversion units 310 and 311 to a necessary frequency, and then the Ether units 312 and 313 connected to the lower apparatus. Are supplied respectively.

On the other hand, with respect to time information, the Ether sections 302 and 303 receive PTP packets (time information corrected for transmission delays based on the IEEE Std 1588 ^TM- 2008 standard) received from the higher-level device. The time information extracted from the PTP packet by the PTP processing unit 351 in the Ether units 302 and 303 is output to the time information accumulation / accuracy monitoring unit 306, and the time information is accumulated in the time information accumulation / accuracy monitoring unit 306.

  The time information accumulation / accuracy monitoring unit 306 monitors the accuracy of the time information and sets the time of the clock 321 of the distribution time oscillation unit 309 and outputs the clock output from the frequency synchronization / oscillation unit 308 to the distribution time oscillation unit 309.

  The distribution time oscillating unit 309 counts up the time of the clock 321 set by the time information accumulation / accuracy monitoring unit 306 with the clock frequency output from the frequency synchronization / oscillation unit 308, and the time information of the clock 321 is transferred to the Ether unit 312, It outputs to 313. Here, it may be possible to select whether to use the time information obtained by counting up the clock 321 by the clock synchronized with the frequency extracted from the SyncE signal or the time information of the latest PTP packet. In the present embodiment, time information of the clock 321 that operates in synchronization with the frequency extracted from the SyncE signal is output to the Ether units 312 and 313.

  The Ether units 310 and 311 superimpose the PTP packet storing the time information output from the distribution time oscillation unit 309 on the SyncE signal synchronized with the frequency output from the frequency conversion units 310 and 311 and transmit it to the lower-level device. To do. The Ether units 310 and 311 include a PTP processing unit 353 that stores time information in a PTP packet and a SyncE processing unit 354 that superimposes the PTP packet on the SyncE signal, as shown in the dotted frame.

  Further, in consideration of a device that wants to acquire a clock signal such as 64 kHz, the frequency converter 314 converts the clock signal to the clock frequency output from the frequency synchronization / oscillator 308, and the necessary frequency via the frequency distributor 315. Output to the device.

  Here, the time information accumulating / accuracy monitoring unit 306 holds the past time information received by the PTP packet, and uses the frequency input from the frequency synchronization / oscillation unit 308 of the distribution time oscillation unit 309. It controls the time setting of the clock 321 and the time counting up. Further, the time information accumulation / accuracy monitoring unit 306 calculates the average value and variance of the time information itself using the time information of the PTP packets received in the past, and sets the time accuracy deterioration threshold. For example, FIG. 7 is a diagram showing an example of the variation characteristic 351 of past time information, where the vertical axis represents the time information value and the horizontal axis represents the number of times. In FIG. 7, when the average value of the past time information is T, and the time accuracy degradation thresholds 352 and 353 are set in the range of three times the variance σ, the positive time accuracy degradation threshold 352 is (T + 3σ). The negative time accuracy degradation threshold value 353 is (T −3σ).

  Then, it is determined whether or not the newly received time information is within the range of the time accuracy deterioration threshold. For example, the number of times that the time information of the PTP packet received in the past certain period (for example, the range 356 in FIG. 7) falls outside the range of the time accuracy degradation threshold (time accuracy degradation range 354, 355) is set in advance (for example, (N times), the time accuracy deterioration alarm is issued to a monitoring control device that monitors the entire network system. In this way, the time accuracy is determined by comparing whether the average value and dispersion value obtained from past time information are within a certain dispersion range by comparing the time information obtained from the PTP packet. Can be monitored with high accuracy. In addition, considering a device that wants to acquire a specific clock signal (64 kHz, etc.), the frequency conversion unit 314 converts the clock frequency output from the frequency synchronization / oscillation unit 308 into a frequency corresponding to the connected device, and the frequency distribution. A necessary clock signal can be output from the unit 315. When the Sync-E signal input from the Ether units 302 and 303 is disconnected, the frequency synchronization / oscillation unit 308 generates an internal frequency by the free-running clock 320.

  As described above, the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present embodiment superimpose and send a PTP packet on a high-accuracy frequency signal synchronously controlled by the synchronous Ethernet (registered trademark), Frequency synchronization and time synchronization can be realized by a single device, and there is no need to provide a device that performs frequency synchronization corresponding to SyncE and a device that performs time synchronization by PTP as in the past. .

[Non-instantaneous switching using time information (Example 1)]
Next, in the frequency / time synchronization method and frequency / time synchronization apparatus according to the present invention, an embodiment for performing uninterruptible switching using time information will be described. FIG. 8 is a block diagram illustrating a configuration example of the frequency / time synchronization apparatus 401 according to the present embodiment. In FIG. 8, a frequency / time synchronizer 401 has two systems of an active frequency synchronization / oscillation unit 402 and a standby frequency synchronization / oscillation unit 403, both of which are synchronized with each other. Each piece of information is entered. Then, while the active frequency synchronization / oscillation unit 402 is in operation, a clock signal is supplied from the active frequency / time synchronization device 402 to the frequency conversion unit 404 and the frequency conversion unit 405 as shown in FIG. To do. Further, when the active frequency synchronization / oscillation unit 402 is switched from the active frequency synchronization / oscillation unit 402 to the standby frequency / time synchronization device 403 due to a failure or maintenance / inspection of the active frequency synchronization / oscillation unit 402, FIG. As shown in FIG. 4, a clock signal is supplied from the standby frequency / time synchronizer 403 to the frequency converter 404 and the frequency converter 405.

  Here, the frequency / time synchronization apparatus 401 according to the present embodiment is characterized in that a clock signal and time information are input, and the frequency synchronization / oscillation unit 402 of the active system is synchronized with the time at which the clock signal changes. By switching to the standby frequency synchronization / oscillation unit 403, occurrence of instantaneous interruption due to phase jumping or the like can be prevented, and non-instantaneous switching without affecting the current service can be realized.

  A specific operation of the frequency / time synchronization apparatus 401 will be described with reference to FIG. First, a synchronized clock signal and time information are input to the active frequency synchronization / oscillation unit 402 and the standby frequency synchronization / oscillation unit 403. In the frequency synchronization / oscillation units 402 and 403, the rising time of the clock signal is set in advance as the timing for matching the phases of the active and standby clock signals. Then, referring to the time information input to the frequency synchronization / oscillation units 402 and 403, the clock signal input from the outside in the frequency synchronization / oscillation units 402 and 403 so that the pulse of the clock signal rises at the set time. Adjust the phase. For example, in the example of FIG. 8A, the active frequency / time synchronizer 402 outputs the clock signal rise time at 0:00 (actually set to the time with the highest resolution of the circuit operation). The phase adjustment is performed so that the clock signal and the clock signal output from the standby frequency / time synchronizer 403 rise simultaneously.

  As a result, the phase of the clock signal output from the active frequency synchronization / oscillation unit 402 and the phase of the clock signal output from the standby frequency synchronization / oscillation unit 403 can be matched, and a failure occurs and the current operation is performed. When switching the system and standby system clock signals, the clock signals of both systems are synchronized in phase, so there is no phase jump of the clock signal at the time of switching. It is possible to switch over.

[Uninterrupted switching using time information (Example 2)]
Next, in the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present invention, an embodiment in which uninterrupted switching is performed using time information among a plurality of apparatuses will be described. In addition, in the non-instantaneous switching (example 1) described in FIG. 8, the switching is performed within one apparatus. However, in this embodiment, there is no instantaneous interruption between a plurality of apparatuses that are synchronized in frequency and time. Switching can be performed.

  FIG. 9 shows an example in which two systems of clock signals are supplied to various service nodes 503 by being made redundant by the two devices of the frequency / time synchronization device 501 and the frequency / time synchronization device 502 according to the present embodiment. . In FIG. 9, the operating frequency / time synchronization apparatus 501 includes a frequency synchronization / oscillation unit 504, a frequency conversion unit 506, and a delay circuit 508. Similarly, the replacement-target frequency / time synchronization apparatus 502 includes a frequency synchronization / oscillation unit 505, a frequency conversion unit 507, and a delay circuit 509.

  Here, the frequency synchronization / oscillation unit 504 and the frequency conversion unit 506 in FIG. 9 correspond to the frequency synchronization / oscillation unit 402 and the frequency conversion unit 404 in FIG. The frequency conversion unit 507 corresponds to the standby frequency synchronization / oscillation unit 403 and the frequency conversion unit 405 of FIG. The phase of the clock signal output from the frequency synchronization / oscillation unit 504 to the frequency conversion unit 506 and the phase of the clock signal output from the frequency synchronization / oscillation unit 505 to the frequency conversion unit 507 are obtained from the PRTC 500. Synchronized by information.

  Specifically, in FIG. 9, first, an external or Sync-E signal clock signal and standard time information from the PRTC 500 are input to the frequency synchronization / oscillation unit 504 of the operating frequency / time synchronization apparatus 501. In FIG. 9, the time information is drawn directly from the PRTC 500, but as described in the previous embodiment, the standard time ( PRTC) may be obtained. Also, as described in the previous embodiment, also in this embodiment, the rising time of the clock signal is set, and the phase of the clock signal is set between the frequency / time synchronizer 501 and the frequency / time synchronizer 502. Can be synchronized.

  Here, the difference from FIG. 8 is that the frequency / time synchronization apparatus 501 and the frequency / time synchronization apparatus 502 are independent devices, so that the arrangement locations are different, and routes to various service nodes 503 are different. May be different. In this case, even if the clock signals are phase-synchronized between the two devices, the phase of the received clock signal is different due to the difference in delay time until the clock signals transmitted from both devices arrive at the various service nodes 503. It may shift.

  Therefore, in the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present embodiment, the delay circuit 508 and the delay circuit 509 for performing phase adjustment by delaying the clock signal are provided in the respective apparatuses and acquired in advance. Correct the deviation of delay time between devices. For example, the transmission delay between the operating frequency / time synchronizer 501 and the various service nodes 503 and the transmission delay between the replacement frequency / time synchronizer 502 and the various service nodes 503 are grasped in advance. Thus, it is possible to calculate the delay amount necessary for synchronizing the phases of the two systems of clock signals input to the various service nodes 503. The transmission delay to the various service nodes 503 can be grasped by transmitting / receiving a specific packet by the same method as PTP, for example.

  Then, by delaying the clock signal by the delay circuit by the calculated delay amount, phase synchronization of the clock signal can be realized, so that the frequency / time synchronizer 501 and the frequency It is possible to prevent the occurrence of a phase jump when switching between the time synchronization device 502 and the two devices can be replaced without interruption without affecting the current service.

  As described above, the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present embodiment affect the current service being used by various service nodes 503 by using time information as in the example of FIG. It is possible to switch without instantaneous interruption without giving

  As described above, as described in each embodiment, the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present invention can realize time synchronization and frequency synchronization with one apparatus. In particular, by using the SyncE signal, it is possible to perform highly accurate time synchronization even during a period in which a PTP packet is not received by time synchronization using a general PTP packet.

  In addition, the frequency / time synchronization method and frequency / time synchronization apparatus according to the present invention can perform quality monitoring of time synchronization accuracy by accumulating past time information and statistically analyzing it, thereby reducing the quality. An alarm can be issued in the event of a failure.

  Furthermore, the frequency synchronization / oscillation unit is made redundant in one frequency / time synchronization unit, and the clock signal is phase-synchronized according to the time information, so that even if one of the frequency synchronization / oscillation units fails, the active system Switching from the standby system to the standby system can be performed without interruption.

  Similarly, by synchronizing the phase of the clock signal output from multiple frequency / time synchronizers with the time information, switching from the active frequency / time synchronizer to the standby frequency / time synchronizer without interruption Can be done. In particular, even when the delay time from each frequency / time synchronizer to the service node is different, the delay time is corrected by the delay circuit so that there is no instantaneous effect on the current service being used in various service nodes. Switching can be realized.

  As described above, the frequency / time synchronization method and the frequency / time synchronization apparatus according to the present invention have been described by way of example in each embodiment, but in various other forms without departing from the spirit or main features thereof. Can be implemented. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner. The present invention is defined by the claims, and the present invention is not limited to the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

101, 151 ... Master device 102 ... Slave device 152, 175 ... Master clock 153, 162 ... Local oscillator 154, 163 ... G.8262EEC
155, 164 ... oscillators 156, 160 ... SyncE timing devices 157, 159 ... PHY units 158, 161 ... MAC unit 165 ... slave clock 170 ... networks 171, 172, 173, 174 , 401, 501, 502... Frequency / time synchronizer 176... PRTC
191, 194, 214, 215, 302, 303, 312, 313... Ether unit 192... Oscillator 193, 221, 321. ... Preliminary master clock 204 ... Active PRTC
205 ... Preliminary PRTC
206, 207, 212, 213, 216, 304, 305, 310, 311, 314, 404, 405, 506, 507... Frequency conversion unit 208, 307... Frequency selection unit 209, 308, 504. Frequency synchronization / oscillation units 220, 320 ... free-running clocks 210, 306 ... time information accumulation / accuracy monitoring units 211, 309 ... distribution time oscillation units 217, 315 ... frequency distribution units 251, 351, 353... PTP processing units 252, 352, 354... SyncE processing unit 301... Lower device 402... Active frequency synchronization / oscillation unit 403. ... Various service nodes 508, 509 ... Delay circuits

Claims (4)

In a frequency / time synchronization method for performing frequency synchronization and time synchronization between devices connected via a packet network,
The upper apparatus superimposes a time synchronization packet including time information synchronized with the standard time on a signal including frequency information synchronized with the standard frequency, and transmits the signal through two paths of the active system and the standby system ,
Lower side of the apparatus for receiving from each of the two paths and a frequency information and time information of the active system and a standby system includes a frequency synchronization oscillating section for each path, the frequency synchronization oscillating section of each path is input Adjust the phase of the input clock signal so that the pulse of the clock signal changes at the set time.
A frequency / time synchronization method characterized by switching to the frequency synchronization oscillator of the standby system at the time when the clock signal output from the frequency synchronization oscillator of the active system changes . The frequency / time synchronization method according to claim 1 ,
When transmitting the signal from a plurality of lower devices to the same service node, the timing of transmitting the signal is delayed according to a delay time from the lower device to the service node. Frequency / time synchronization method. In a frequency / time synchronization device that performs frequency synchronization and time synchronization between devices connected via a packet network,
A packet including time information is superimposed on a signal including frequency information and transmitted through two paths of an active system and a standby system, and the signal including the frequency information and the packet including the time information are transmitted from a communication destination device. And a network connection unit that receives the two routes of the active system and the standby system ,
Two frequency-synchronized oscillation units that are arranged for each path of the active system and the standby system and generate a clock signal synchronized with the frequency information received by the network connection unit;
The frequency synchronous oscillator of each path refers to the input time information, adjusts the phase of the input clock signal so that the pulse of the clock signal changes at the set time,
The frequency / time synchronization apparatus according to claim 1 , wherein the frequency synchronization oscillator of the active system is switched to the frequency synchronization oscillator of the standby system at a time when the output clock signal changes . The frequency / time synchronization apparatus according to claim 3 ,
When transmitting the signal from a plurality of the frequency / time synchronizers to the same service node, a delay for delaying the timing of transmitting the signals according to the delay time from each frequency / time synchronizer to the service node A frequency / time synchronizer characterized by further comprising a section.

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