JP5636269B2 - Group III nitride semiconductor device - Google Patents

Description

The present invention relates to a group III nitride semiconductor represented by the general formula: Al _x Ga _y In _z N _{1- (x + y + z)} (0 ≦ x <1, 0 ≦ y <1, 0 ≦ z <1, x + y + z <1) It is related with the semiconductor device comprised by these.

  A group III nitride semiconductor represented by GaN is highly expected as a promising material for realizing a power semiconductor device with high breakdown voltage and low loss. In order to put the group III nitride semiconductor device into practical use, a technique for preventing leakage current from flowing is required.

  FIG. 1 shows a process of manufacturing a plurality of vertical diodes using a wafer 10 in which a p-type group III nitride semiconductor 2 is stacked on an upper surface of an n-type group III nitride semiconductor 4. As shown in (d), it is also possible to dice directly from the state of (a) and separate into a plurality of diodes, but in that case, each diode must be inspected after separation, The inspection process becomes complicated. Therefore, normally, as shown in (b), element isolation trenches 14a and 14b reaching the n-type group III nitride semiconductor 4 from the upper surface of the p-type group III nitride semiconductor 2 are formed, and a plurality of elements are electrically connected. Separate into diodes. By inspecting at this stage, it is possible to inspect each diode corresponding to the anode electrodes 6a, 6b, 6c in a state where the diode groups corresponding to the anode electrodes 6a, 6b, 6c are aligned on the wafer. As shown in (c), if dicing is performed thereafter, the inspection process can be made more efficient. In addition, 12a and 12b are dicing lines, 8a, 8b and 8c are cathode electrodes, and 2a, 2b and 2c are anode regions separated by element isolation grooves 14a and 14b.

  In order to form the element isolation trenches 14a and 14b, dry etching is usually performed from the upper surface of the p-type group III nitride semiconductor 2. In this case, the surfaces defining the element isolation trenches 14a and 14b, that is, the exposed surfaces resulting from the dry etching of the p-type group III nitride semiconductor 2 (hereinafter sometimes abbreviated as dry etching surfaces) are dry. The ions for etching give an impact, and many defects are generated on the exposed surface of the p-type group III nitride semiconductor 2. In particular, many defects from which nitrogen has been released have occurred. Defects from which nitrogen has escaped indicate the nature of the donor. As a result, the dry etching surface of the p-type group III nitride semiconductor 2 is likely to be n-type.

  When the exposed surface of the p-type group III nitride semiconductor 2 defining the element isolation trenches 14a and 14b formed by dry etching becomes n-type, the n-type group III nitride is formed between the anode electrode 6 and the cathode electrode 8. The surface of the physical semiconductor 2 is connected to the n-type group III nitride semiconductor 4, and a leak current flows between the anode electrode 6 and the cathode electrode 8 as indicated by an arrow 16 in FIG. Here, items that are described with the subscripts such as a, b, and c omitted are common items that are indicated by the subscripts such as a, b, and c. Even if the exposed surface of group III nitride semiconductor 2 is covered with an insulating film, if the exposed surface of group III nitride semiconductor 2 becomes n-type, it is not possible to prevent leakage current from flowing. There is a need for a technique for preventing an exposed surface resulting from dry etching of a p-type group III nitride semiconductor from becoming n-type.

FIG. 2 is a schematic diagram in which the structure of a lateral transistor composed of a group III nitride semiconductor is stereoscopically viewed, 22 indicates a p-type GaN layer, 24 indicates an n-type GaN layer, and 26 indicates an insulating film. , 28 indicates a drain electrode, 30 indicates a gate electrode, 32 indicates a source electrode, and 34 indicates a ground electrode. A lateral transistor structure (not shown) is formed on the n-type GaN layer. The ground electrode 34 extracts holes.
FIG. 2 shows a state where the p-type GaN layer 22 and the n-type GaN layer 24 are dry-etched, and the side surfaces of the p-type GaN layer 22 and the n-type GaN layer 24 are exposed in the element isolation trench. Actually, the side surface of the p-type GaN layer 22 and the side surface of the n-type GaN layer 24 are covered with an insulating film, but the illustration of the insulating film is omitted in FIG. Even if the side surface of the p-type GaN layer 22 and the side surface of the n-type GaN layer 24 are covered with an insulating film, when the side surface of the p-type GaN layer 22 exposed by dry etching becomes n-type by dry etching, a broken line 36 indicates As described above, a leak current flows along the side surface of the n-type GaN layer 22, and a leak current flows between the drain electrode 28 and the ground electrode 34. Also in this example, a technique for preventing the dry etching surface of the p-type group III nitride semiconductor from becoming n-type is required.

FIG. 3 is a schematic view of a vertical transistor made of a group III nitride semiconductor, and a similar structure is disclosed in Patent Document 1. In FIG. 48 is a drain electrode, 46 is an n-type GaN region, 44 is an n-type GaN region, 42a and 42b are p-type GaN regions, 52 is an n-type GaN region, 54 is an i-type AlGaN region, 58 is a gate insulating film, 60 is a gate electrode, 50a and 50b are ground electrodes, 54a and 54b are source regions, and 56a and 56b are source electrodes.
In the case of FIG. 3, if no gate-on voltage is applied to the gate electrode 60, a depletion layer extending from the interface between the p-type GaN region 42a and the n-type GaN region 44 into the n-type GaN region 44, and the p-type GaN region 42b and the n-type A depletion layer extending in the n-type GaN region 44 from the interface of the GaN region 44 continues, and the n-type GaN region 44 existing between the p-type GaN region 42a and the p-type GaN region 42b is depleted to increase the breakdown voltage. . However, when the p-type GaN region 42a and the p-type GaN region 42b are dry-etched to form the element isolation trench, if the side surface of the p-type GaN region 42a and the side surface of the p-type GaN region 42b become n-type, Leakage current flows between the ground electrode 50 a and the drain electrode 48 and between the ground electrode 50 b and the drain electrode 48. There is still a need for a technique that prevents the dry etching surface of a p-type group III nitride semiconductor from becoming n-type.

JP 2004-260140 A

  As described above, when a semiconductor device is formed of a group III nitride semiconductor, a technique for preventing the dry etching surface of the p-type group III nitride semiconductor from becoming n-type is required.

  In the present invention, when the p-type group III nitride semiconductor is dry-etched, the p-type group III-nitride is accepted when the semiconductor device actually operates while accepting the phenomenon that the dry-etched surface becomes n-type. A technique for preventing the dry etching surface of the semiconductor from becoming n-type is employed.

In the group III nitride semiconductor device of the present invention, the p-type group III nitride semiconductor and the n-type group III nitride semiconductor are dry-etched to form element isolation grooves. As a result, the p-type group III nitride semiconductor and the n-type group III nitride semiconductor are exposed on the wall surface of the element isolation trench. The term “exposed” as used herein refers to exposure when an element isolation trench is formed by dry etching. Actually, since the insulating film is formed on the exposed surface after that, it is not exposed even after the insulating film is formed. P-type group III nitride semiconductor and the n-type Group III nitride semiconductor surface which has been exposed in the isolation trench when forming an isolation trench by dry etching Ru covered with an insulating film. The group III nitride semiconductor device of the present invention includes hole inducing means for inducing holes existing in the p-type group III nitride semiconductor to the surface of the p-type group III nitride semiconductor in contact with the insulating film. The hole guiding means is formed at a position facing the n-type dry etching surface of the p-type group III nitride semiconductor, and at least during the actual operation of the semiconductor device, the n-type dry etching is always performed. It induces holes that make the surface p-type.
As long as the hole inducing means is provided, the p-type group III nitride semiconductor is always operated when the semiconductor device actually operates, even if the surface of the p-type group III nitride semiconductor immediately after processing is n-type. Holes are induced to the p-type by being induced on the surface, and leakage current can be prevented from flowing along the n-type surface.

For example if the negative charges in the insulating film is always charged, can be a hole leading means an insulating film negative charge is always charged.
Or may be a p-type group III if added always connected to the electrode to the negative potential while facing the nitride semiconductor, hole guide means always connected Ru electrode to a negative potential through the insulating film.
Furthermore, if a metal film facing the p-type group III nitride semiconductor and having a work function larger than the work function of the p-type group III nitride semiconductor is added via the insulating film, the metal film is used as the hole inducing means. can do.
In any configuration, at least during the actual operation of the semiconductor device , holes are induced on the surface of the p-type group III nitride semiconductor to be p-type. Leakage current can be prevented from flowing along the n-type surface.

The present invention, p-type group III nitride on the upper surface of the n-type Group III nitride semiconductor semiconductor is laminated, on its p-type group III dry etching to the n-type Group III nitride semiconductor of a nitride semiconductor of the upper surface This is particularly useful when forming a reaching element isolation trench. The side surface of the p-type group III nitride semiconductor that provides the side surface of the element isolation trench is covered with an insulating film. The negative charge is always charged on the insulating film, or an electrode that faces the p-type group III nitride semiconductor and is always connected to the negative potential is added via the insulating film, or p is connected through the insulating film. A metal film facing the type III nitride semiconductor and having a work function larger than that of the p type group III nitride semiconductor is added.
In the group III nitride semiconductor device having the above-described configuration, the side surface of the p-type group III nitride semiconductor defining the element isolation groove formed by dry etching of the p-type group III nitride semiconductor is n-type. At least during the actual operation of the semiconductor device , the semiconductor device operates in a p-type state with holes induced on its side surfaces. Leakage current can be prevented from flowing along the side surface that defines the element isolation trench.

  According to the technology disclosed in this specification, even when the surface of the p-type group III nitride semiconductor is changed to n-type, the surface of the p-type group III nitride semiconductor is not positively aligned when the semiconductor device actually operates. It operates in a state where the holes are induced to become p-type. Leakage current can be prevented from flowing along the n-type surface. It is possible to prevent deterioration in characteristics of a semiconductor device manufactured by dry etching a p-type group III nitride semiconductor.

The figure which shows the process in which several vertical type diodes are manufactured using the wafer by which the p-type group III nitride semiconductor is laminated | stacked on the upper surface of an n-type group III nitride semiconductor. The figure which shows the horizontal transistor manufactured with the group III nitride semiconductor three-dimensionally and typically. The figure which shows typically the cross section of the vertical transistor manufactured with the group III nitride semiconductor. Sectional drawing of the part which faces the p-type group III nitride semiconductor of 1st Example. Sectional drawing of the part which faces the p-type group III nitride semiconductor of 2nd Example. Sectional drawing of the part which faces the p-type group III nitride semiconductor of 3rd Example. Sectional drawing of the part which faces the p-type group III nitride semiconductor of 4th Example. Sectional drawing of the part which faces the p-type group III nitride semiconductor of 5th Example.

The main features of the embodiments described below are exemplified below.
(Feature 1) The hole guiding means faces the entire dry etching surface of the p-type group III nitride semiconductor.
(Feature 2) The hole inducing means extends over a wider range than the dry etching surface of the p-type group III nitride semiconductor.
(Feature 3) The hole inducing means faces a part of the dry etching surface of the p-type group III nitride semiconductor.

  First, events common to the first to fifth embodiments described with reference to FIGS. 4 to 8 will be described. As shown in FIGS. 4 to 8, a p-type group III nitride semiconductor (p-type GaN in this embodiment) 62 is formed on an upper surface of an n-type group III nitride semiconductor (n-type GaN in this embodiment) 64. Is manufactured, a p-type group III nitride semiconductor 62 is exposed by dry etching from the upper surface of the p-type group III nitride semiconductor 62, and an element isolation groove is formed. An insulating film covering 62a was formed. The side surface 62a of the p-type group III nitride semiconductor 62 when exposed by dry etching is n-type. In each example described later, when the semiconductor device is actually operated by the layer facing the exposed side surface 62 a of the p-type group III nitride semiconductor 62, holes are formed on the side surface 62 a of the p-type group III nitride semiconductor 62. Is operated in a p-type state. According to each example described later, it is possible to prevent leakage current from flowing along the n-type exposed surface. It is possible to prevent the characteristics of a semiconductor device manufactured by dry etching the p-type group III nitride semiconductor 62 from being deteriorated.

Example 1 As shown in FIG. 4, negatively charged particles are injected into an insulating film 66 (SiO _{2 in} this example) covering the side surface 62 a of the p-type group III nitride semiconductor 62. In this embodiment, negatively charged particles are injected into a region 68 of the insulating film 66 that is the central portion of the film thickness and faces the entire side surface 62a. Electrons or negative ions can be used for the negatively charged particles. When the region 68 facing the side surface 62a is negatively charged, holes that are majority carriers existing in the p-type group III nitride semiconductor 62 are induced in a range along the side surface 62a, and along the side surface 62a. A hole accumulation layer is formed. The hole accumulation layer makes the side surface 62a p-type. At the stage of dry etching, the side surface 62a of the p-type group III nitride semiconductor 62 is n-type. However, when actually operating, a hole accumulation layer is formed along the side surface 62a and the side surface 62a is formed as a p-type. It operates in the state that By injecting negatively charged particles into the insulating layer 66, leakage current can be prevented from flowing along the n-type side surface.

Example 2 As shown in FIG. 5, the insulating film covering the side surface 62 a of the p-type group III nitride semiconductor 62 is composed of an inner insulating film 70 and an outer insulating film 72. In this embodiment, all are made of SiO ₂ . Negatively charged particles are injected from the outside of the outer insulating film 72. In this embodiment, negatively charged particles are injected into the region 74 facing the entire side surface 62a. Electrons or negative ions can be used for the negatively charged particles. A large number of traps are formed at the interface between the inner insulating film 70 and the outer insulating film 72. The injected charged particles are captured by traps formed along the interface between the inner insulating film 70 and the outer insulating film 72, and the position thereof is fixed. According to Example 2, a more stable negative charge charging region can be formed than in Example 1.

  Example 3 As shown in FIG. 6, an electrode 78 is formed in an insulating film 76 that covers the side surface 62 a of the p-type group III nitride semiconductor 62. The electrode 78 is insulated from the surroundings by an insulating film 76 and is a floating electrode. The floating electrode 78 is formed in a range facing the entire side surface 62a. Negatively charged particles 80 are injected into the floating electrode 78. Electrons or negative ions can be used for the negatively charged particles. When the floating electrode 78 is used, a larger amount of negative charge than in the first and second embodiments can be injected. According to Example 3, a stable hole accumulation layer is formed.

  Example 4 As shown in FIG. 7, an electrode 84 is formed on the outer surface of the insulating film 82 that covers the side surface 62 a of the p-type group III nitride semiconductor 62. The electrode 84 is formed in a range facing the entire side surface 62a. The electrode 84 is used by being connected to the negative potential of the DC power source 86. The hole accumulation layer can be provided along the side surface 62a by the negatively charged electrode 84. Also in Example 4, a stable hole accumulation layer is formed.

  Example 5 As shown in FIG. 8, a metal film 90 is formed on the outer surface of the insulating film 88 that covers the side surface 62 a of the p-type group III nitride semiconductor 62. As the metal used for the metal film 90, a metal having a work function larger than that of the p-type group III nitride semiconductor 62 is used. For example, Au, Pt, Pd, Ni, Se, Co, Ir, Rh, Te, alloys thereof, or ITO can be used. When the metal film 90 made of a metal having a work function larger than the work function of the p-type group III nitride semiconductor 62 is provided facing the side face 62a through the insulating film 88, a hole accumulation layer is formed along the side face 62a. Can be provided. Also in Example 5, a stable hole accumulation layer is formed.

  In the above, the embodiment in the case where the groove having a depth penetrating the p-type group III nitride semiconductor 62 has been shown. In this case, the layer for inducing the hole accumulation layer may be extended to a range facing the side surface of the n-type group III nitride semiconductor 64 or extended to a range facing the upper surface of the p-type group III nitride semiconductor 62. Also good. Further, the hole accumulation layer may be formed only in a range facing a part of the side surface of the p-type group III nitride semiconductor 64. For example, when the leak current can be blocked by the hole accumulation layer formed only at a part of the depth of the side surface of the p-type group III nitride semiconductor, the p-type group III nitride semiconductor 64 Hole inducing means may be formed in a range facing a part of the exposed surface. This is also effective when the groove formed from the upper surface of the p-type group III nitride semiconductor 62 ends at an intermediate depth of the p-type group III nitride semiconductor 62. In this case, the bottom surface of the groove is defined by the upper surface of the p-type group III nitride semiconductor 62, and the side surface of the groove is defined by the side surface of the p-type group III nitride semiconductor 62. By providing a layer for inducing a hole accumulation layer in a range facing the exposed surface of the p-type group III nitride semiconductor 62 that defines the bottom and side surfaces of the groove, along the exposed surface of the group III nitride semiconductor 62 Leakage current can be prevented from flowing.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
The technical scope of the claims described below is not limited to the examples. The examples are merely illustrative.

2: p-type group III nitride semiconductor 4: n-type group III nitride semiconductor 6: anode electrode 8: cathode electrode 10: wafer 12: dicing line 14: element isolation groove 22: p-type group III nitride semiconductor 24: n Type III nitride semiconductor 26: insulating film 28: drain electrode 30: gate electrode 32: source electrode 34: ground electrode 48: drain electrode 46: n-type GaN region 44: n-type GaN region,
42a and 42b: p-type GaN region,
52: n-type GaN region 54: i-type AlGaN region 58: gate insulating film 60: gate electrodes 50a and 50b: ground electrodes 54a and 54b: source regions 56a and 56b: source electrode 62: p-type group III nitride semiconductor 64 : N-type group III nitride semiconductor 66: insulating film 68: negative charge storage region 70: inner insulating film 72: outer insulating film 78: floating electrode 80: negative charge charged particles 84: electrode 90: metal film

Claims (5)

The p-type group III nitride semiconductor and the n-type group III nitride semiconductor are exposed on the wall surface of the element isolation groove formed by dry etching,
The surfaces of the p-type group III nitride semiconductor and the n-type group III nitride semiconductor exposed on the wall surface are covered with an insulating film,
The p-type group III are added hole guide means for guiding the holes existing in the p-type group III nitride semiconductor of the surface in contact with the insulating film to the nitride in semiconductor,
The hole inducing means is formed at a position facing the n-type dry etching surface of the p-type group III nitride semiconductor, and is always at least during the actual operation of the semiconductor device. A III-nitride semiconductor device characterized by inducing holes that make the dry etching surface p-type . Wherein the insulating film has negative charges are always charged, III-nitride semiconductor device of claim 1, wherein the insulating film whose negative charge is always charged is the hole inducing means. The always connected to the electrode to a negative potential with an insulating film over the face and the p-type group III nitride semiconductor is formed, claims wherein the electrode that will be constantly connected to the negative potential becomes positive hole guide means 1 Group III nitride semiconductor device. The insulating film being a metal film having a large work function than the both the work function of the p-type group III nitride semiconductor which faces the p-type group III nitride semiconductor through, the metal layer is the positive The group III nitride semiconductor device according to claim 1, which serves as a hole guiding means. The p-type group III nitride semiconductor on the upper surface of the n-type Group III nitride semiconductor are stacked,
III according to one of any of the 4 claims 1, characterized in that the isolation trench reaching the n-type Group III nitride semiconductor from the top surface of the p-type group III nitride semiconductor is formed Group nitride semiconductor device.

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