JP5633135B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a trench gate type semiconductor device.

  Patent Document 1 discloses an example of a trench gate type semiconductor device. In the semiconductor device of Patent Document 1, an active region and an inactive region are provided in a semiconductor substrate. In the active region, an element region and a termination region surrounding the element region are formed. An element structure such as a trench gate electrode is formed in the element region. A gate pad is formed in the inactive region. The gate pad is electrically connected to the trench gate electrode through the gate wiring. The other end of the wire having one end connected to an external circuit is bonded to the gate pad. When an on potential is applied to the gate pad by an external circuit, the on potential is applied to the trench gate electrode in the element region, and the semiconductor device is turned on. When the application of the on potential to the gate pad is stopped, the semiconductor device is turned off.

JP 2007-173411 A

  In this type of semiconductor device, since the element region functions as a semiconductor element, there is a demand to make the element region (active region) as wide as possible. That is, there is a desire to make the inactive region where the gate pad is formed as small as possible. On the other hand, since a wire must be bonded to the gate pad, an area required for wire bonding must be secured. Therefore, how to arrange the element region (active region) and the gate pad (inactive region) on the semiconductor substrate becomes a problem.

  Consider a case where an element region and a gate pad are arranged on the semiconductor substrate 80 shown in FIG. As described above, since a wire must be bonded to the gate pad, the short side of the gate pad must be a predetermined length (La in FIG. 4) or more. Here, as shown in FIG. 4B, when the short side of the gate pad 88 is arranged so as to be parallel to the short side of the semiconductor substrate 80, the gate pad 88 is formed along the long side of the semiconductor substrate 80. The On the other hand, as shown in FIG. 4A, when the short side of the gate pad 82 is arranged so as to be parallel to the long side of the semiconductor substrate 80, the gate pad 82 is formed along the short side of the semiconductor substrate 80. . For this reason, the area of the gate pad 82 of FIG. 4A is smaller than that of the gate pad 88 of FIG. That is, the area of the element region 84 in FIG. 4A is larger than that of the element region 86 in FIG. Therefore, for the semiconductor substrate 80 shown in FIG. 4, the gate pad 82 is normally arranged so that the short side of the gate pad 82 is parallel to the long side of the semiconductor substrate 80 as shown in FIG. An element region 84 is disposed. That is, the gate pad 82 is arranged in a direction (x direction in the drawing) in which the long side of the element region 84 extends with respect to the element region 84 so that the long side of the gate pad 82 is substantially equal to the short side of the element region 84. The

  However, in the layout shown in FIG. 4A, the long side of the gate pad 82 (the length in the y direction in the figure) exceeds the length required for wire bonding, and the gate pad 82 becomes unnecessarily large. . Therefore, it is conceivable to arrange the gate pad 104 and the element region 102 on the semiconductor substrate 100 as shown in FIG. By adopting the layout shown in FIG. 5, the gate pad 104 does not become unnecessarily large, and the area of the element region 102 can be increased accordingly.

  However, when the layout as shown in FIG. 5 is adopted, the breakdown voltage of the semiconductor device may be reduced. That is, in this type of semiconductor device, in order to improve the breakdown voltage, a termination trench that makes a round of the element region is formed in the termination region, and a floating diffusion region having the same conductivity type as the body region is formed at the bottom of the gate trench and termination trench. There is a case. When the layout shown in FIG. 5 is adopted in a semiconductor device in which such a floating diffusion region is formed, a portion 106 surrounded by a dotted line in FIG. 5 (a portion where the termination region is curved toward the element region (inner side) (hereinafter referred to as inner radius). ))), The breakdown voltage of the semiconductor device is likely to decrease. Therefore, in the semiconductor device disclosed in Patent Document 1, a decrease in breakdown voltage is suppressed by defining the shape and arrangement of the inner radius portion 106 and the distance between the termination trench and the gate trench in the inner radius portion 106. However, in the technique of Patent Document 1, the inner round portion (terminal trench) and the gate trench must be formed with high accuracy. For this reason, there exists a problem that a pressure | voltage resistance falls easily by the dispersion | variation in the shape of an inner round part (terminal trench) or a gate trench.

  As described above, in the layout shown in FIG. 4A, although the breakdown voltage is unlikely to decrease, there is a problem that the area of the element region is reduced by the increase in the area of the gate pad. On the other hand, in the layout shown in FIG. 5, although the area of the element region can be increased, there is a problem that the breakdown voltage tends to decrease.

  The present application has been created in view of the above-described circumstances, and provides a semiconductor device in which the breakdown voltage is unlikely to decrease and the area of the element region can be increased by reducing the area of the gate pad. With the goal.

A semiconductor device disclosed in this specification includes a first active region formed in a semiconductor substrate, a second active region formed in the semiconductor substrate, an inactive region formed in the semiconductor substrate, and an inactivity A gate pad is formed on the region. Each of the first active region and the second active region has an element region and a termination region surrounding the element region. Each element region of the first active region and the second active region has a first conductivity type body region formed in a range facing the upper surface in the semiconductor substrate, and a second conductivity type in contact with the lower surface of the body region. And a gate electrode facing the body region and an insulation disposed between the gate electrode and the wall surface of the gate trench. A floating region of the first conductivity type that surrounds the body and the bottom of the gate trench and is surrounded by a drift region. In each of the termination regions of the first active region and the second active region, a termination trench that makes a circuit around the outside of the element region is formed, and the periphery of the termination trench is surrounded by a drift region. A floating region of the first conductivity type is formed. The gate pad is electrically connected to the respective gate electrodes of the first active region and the second active region. The first active region, the second active region, and the gate pad are arranged so as to satisfy the following conditions when the semiconductor substrate is viewed in plan.
(1) The first active region has a rectangular shape in which one side is a long side while the other side is a short side.
(2) The second active region has a rectangular shape and is arranged side by side in a direction in which the long side of the first active region extends with respect to the first active region.
(3) The gate pad has a rectangular shape and is arranged side by side in the direction in which the long side of the first active region extends with respect to the first active region.
(4) The second active region and the gate pad are arranged side by side in the direction in which the short side of the first active region extends.
(5) The length of the side of the second active region that is parallel to the short side of the first active region is shorter than the length of the short side of the first active region.
(6) The length of the side parallel to the short side of the first active region of the gate pad is shorter than the length of the short side of the first active region.
(7) The length of the side parallel to the long side of the first active region of the gate pad is shorter than the length of the long side of the first active region.
(8) The length of the side of the second active region that is parallel to the long side of the first active region is a length corresponding to the length of the side of the gate pad that is parallel to the long side of the first active region. is less the length of the side parallel to the long sides of the first active region of the gate pad.
(9) The sum of the length of the side of the second active region that is parallel to the short side of the first active region and the length of the side of the gate pad that is parallel to the short side of the first active region is The length corresponds to the length of the side parallel to the short side.

The “rectangular shape” referred to here includes not only a rectangular shape having a right corner, but also a rectangular shape having a chamfered corner. Similarly, the “rectangular shape” includes not only a quadrangle (rectangle or square) whose corners are perpendicular, but also a quadrangle whose corners are chamfered.
Further, “first conductivity type” and “second conductivity type” mean either n-type or p-type. That is, when the “first conductivity type” is p-type, the “second conductivity type” is n-type, and when the “first conductivity type” is n-type, the “second conductivity type” is p-type. It is a type.

  In the semiconductor device, when the semiconductor substrate is viewed in plan, both the first active region and the second active region are rectangular. For this reason, the above-mentioned inner round portion is not formed in the first active region and the second active region. As a result, it is possible to make it difficult for the breakdown voltage of the semiconductor device to decrease.

  In this semiconductor device, the areas of the second active region and the gate pad are made smaller than the area of the first active region. The second active region and the gate pad are arranged side by side in the direction in which the short side of the first active region extends, and the long side of the first active region extends with respect to the first active region. Arrange them side by side. That is, the length of the side parallel to the short side of the first active region of the gate pad is made shorter than the length of the short side of the first active region, and the second active region is arranged in the space formed thereby. Therefore, the area of the active region can be increased as compared with the layout shown in FIG. For example, in the example of the semiconductor device according to claim 1 shown in FIG. 1, the second active region 16 and the gate pad 18 are arranged side by side in the y direction, while the second active region 16 and the gate pad 18 are arranged in the first active region. 14 are arranged side by side in the x direction. As is apparent from FIG. 1, the length of the gate pad 18 in the y direction is shortened, and the second active region 16 is formed in the space formed thereby. As a result, the area of the element region (active region) can be increased as compared with the layout shown in FIG. Note that the layout of FIG. 1 is illustrated for easy understanding of the layout of the semiconductor device of claim 1, and the semiconductor device of claim 1 is not limited to the layout shown in FIG.

  In the above semiconductor device, each element region of the first active region and the second active region has a plurality of gate electrodes, and the plurality of gate electrodes in each element region are obtained when the semiconductor substrate is viewed in plan view. In addition, it is preferable that the short sides of the first active region extend in a direction in which the first active region extends and that the long sides of the first active region extend in a direction in which the long side extends. According to such a configuration, since the longitudinal direction of the gate electrode is the direction in which the short side of the first active region extends, the length of the longitudinal direction of the gate electrode can be shortened in the first active region having a large area. . As a result, the semiconductor device can be turned on in a short time when an on potential is applied to the gate electrode.

  In the above semiconductor device, a gate wiring that is conductive to the gate pad and to the gate electrode is formed on the inactive region. The gate wiring is first when the semiconductor substrate is viewed in plan view. It is preferably provided along the two long sides of the active region, and no gate wiring is provided between the first active region and the second active region. According to such a configuration, the area of the active region can be increased by the amount that the gate wiring is not provided between the first active region and the second active region.

  Further, in the above semiconductor device, the gate wiring is provided along the side of the second active region that is not adjacent to the gate pad among the two sides parallel to the long side of the first active region. It is preferable that no gate wiring extending along the second active region is provided between the active region and the gate pad. According to such a configuration, the area of the second active region can be increased by the amount that the gate wiring extending along the second active region is not provided between the second active region and the gate pad.

  Further, in the above semiconductor device, the element region of the first active region further includes a first surface electrode provided on the surface of the semiconductor substrate, and the element region of the second active region is formed on the surface of the semiconductor substrate. It is preferable that a second surface electrode is further provided, and the first surface electrode and the second surface electrode are connected by a metal layer. According to such a configuration, it is possible to eliminate the need for wire bonding to each of the first surface electrode and the second surface electrode.

It is a top view of the semiconductor device of the 1st example. It is the II-II sectional view taken on the line of FIG. It is a top view of the semiconductor device which concerns on another Example. It is a figure for demonstrating the layout of the conventional semiconductor device. It is a figure for demonstrating the other layout of the conventional semiconductor device.

First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device 10 is formed on a semiconductor substrate 12. In the semiconductor substrate 12, a first active region 14, a second active region 16, and an inactive region 21 are formed. As the semiconductor substrate 12, a known semiconductor substrate (for example, a silicon substrate (Si substrate), a silicon carbide substrate (SiC substrate), etc.) can be used.

  First, the first active region 14 will be described. As shown in FIG. 1, the first active region 14 is formed in a rectangular shape when the semiconductor substrate 12 is viewed in plan. The long side of the first active region 14 (side extending in the x direction in the drawing) is parallel to the long side of the semiconductor substrate 12 and extends along the long side of the semiconductor substrate 12. The long side of the first active region 14 is shorter than the long side of the semiconductor substrate 12. Therefore, a relatively large space is formed in the semiconductor substrate 12 below the first active region 14.

  On the other hand, the short side (side extending in the y direction) of the first active region 14 is parallel to the short side of the semiconductor substrate 12. One of the two short sides of the first active region 14 extends along the short side of the semiconductor substrate 12, and the other extends at a position away from the short side of the semiconductor substrate 12 by a predetermined distance. The short side of the first active region 14 is slightly shorter than the short side of the semiconductor substrate 12. Therefore, a small space is formed in the semiconductor substrate 12 on the side of the first active region 14 (in the direction in which the short side of the first active region 14 extends).

  The first active region 14 has a cell region 14a where a semiconductor element is formed and a termination region 14b surrounding the cell region 14a. A plurality of gate electrodes 36 are formed in the cell region 14a. The plurality of gate electrodes 36 extend in the y direction of FIG. 1 (that is, the direction in which the short side of the first active region 14 extends), and the x direction in FIG. 1 (that is, the long side of the first active region 14 extends). In the direction). Three termination trenches 46 are formed in the termination region 14b. The termination trench 46 makes a round around the cell region 14a.

  Here, the configuration of the cell region 14a will be described. As shown in FIG. 2, a vertical field effect transistor (MOSFET) is formed in the cell region 14a. That is, the gate trench 30 is formed in the upper surface of the semiconductor substrate 12 in the cell region 14a. The gate trench 30 penetrates a source region 42 and a body region 32 described later, and its lower end extends to the drift region 26. A gate electrode 36 is formed in the gate trench 30. The gate electrode 36 is formed so that the lower end thereof is slightly deeper than the lower surface of the body region 32. An insulator 34 is filled between the wall surface of the gate trench 30 and the gate electrode 36 (that is, laterally and below the gate electrode 36). For this reason, the gate electrode 36 faces the body region 32 and the source region 42 with the insulator 34 interposed therebetween. A cap insulating film 40 is formed on the gate electrode 36.

  In the cell region 14 a, an n + type source region 42 and a p + type body contact region 46 are formed in a region facing the upper surface of the semiconductor substrate 12. The source region 42 is formed in contact with the insulator 34. Body contact region 46 is formed in contact with source region 42.

  A p − type body region 32 is formed below the source region 42 and the body contact region 46. The impurity concentration of the body region 32 is set lower than the impurity concentration of the body contact region 46. The body region 32 is in contact with the source region 42 and the body contact region 46, and is in contact with the insulator 34 below the source region 42. For this reason, the source region 42 is surrounded by the body region 32 and the body contact region 46. The body region 32 is formed to the inside of the termination trench 46 located on the outermost periphery of the termination region 14b, and the outer edge thereof reaches the inner wall surface of the termination trench 46 located on the outermost periphery.

  An n − type drift region 26 is formed below the body region 32. The drift region 26 is formed on the entire surface of the semiconductor substrate 12. The drift region 26 is in contact with the lower surface of the body region 32. The drift region 26 is separated from the source region 42 by the body region 32. A p − type diffusion region 28 is formed in the drift region 26 in a range surrounding the bottom of the gate trench 30. The diffusion region 28 is in contact with the insulator 34 below the gate electrode 36 (that is, the bottom of the gate trench 30). The periphery of the diffusion region 28 is surrounded by the drift region 26. Thereby, the diffusion region 28 is separated from the body region 32.

  An n + type drain region 24 is formed in a region facing the lower surface of the semiconductor substrate 12. The drain region 24 is formed on the entire surface of the semiconductor substrate 12. The impurity concentration in the drain region 24 is set higher than the impurity concentration in the drift region 26. The drain region 24 is in contact with the lower surface of the drift region 26. The drain region 24 is separated from the body region 20 by the drift region 26.

  A drain electrode 22 is formed on the lower surface of the semiconductor substrate 12. The drain electrode 22 is formed on the entire surface of the semiconductor substrate 12. The drain electrode 22 is in ohmic contact with the drain region 24. A source electrode 38 is formed on the upper surface of the semiconductor substrate 12. The source electrode 38 is formed in the element region 14a. The source electrode 38 is formed so as to cover the cap insulating film 40 and is insulated from the gate electrode 36. The source electrode 38 is in ohmic contact with the source region 42 and the body contact region 46.

  Next, the termination region 14b of the first active region 14 will be described. As shown in FIG. 2, three termination trenches 46 are formed in the termination region 14b. The termination trench 46 passes through the body region 32, and its lower end extends to the drift region 26. The lower end of the termination trench 46 has the same depth as the lower end of the gate trench 30. An insulator 48 is filled in the termination trench 46. A p− type diffusion region 52 is formed in a range surrounding the bottom of the termination trench 46. The periphery of the diffusion region 52 is surrounded by the drift region 26. An insulating film 50 is formed on the surface of the semiconductor substrate 12 in the termination region 14b. The insulating film 50 is formed up to the surface of the inactive region 21.

  Next, the second active region 16 will be described. As shown in FIG. 1, the second active region 16 is formed in a rectangular shape (substantially square shape) when the semiconductor substrate 12 is viewed in plan. The second active region 16 is disposed in the lower right corner of the semiconductor substrate 12. As is clear from FIG. 1, the second active region 16 is arranged side by side with respect to the first active region 14 in the x direction of the first active region 14. One side of the second active region 16 extending in the x direction is parallel to the long side of the semiconductor substrate 12 and extends along the long side of the semiconductor substrate 12. The other side of the second active region 14 extending in the x direction extends a position away from the long side of the semiconductor substrate 12 by a predetermined distance. The “length of the side extending in the x direction of the second active region” is shorter than the “length of the long side of the first active region 14”. Further, the sum of “the length of the long side of the first active region 14” and “the length of the side of the second active region extending in the x direction” is slightly shorter than the long side of the semiconductor substrate 12.

  On the other hand, one of the sides extending in the y direction of the second active region 16 is parallel to the short side of the semiconductor substrate 12 and extends along the short side of the semiconductor substrate 12. The other side of the second active region 16 extending in the y direction extends at a position away from the short side of the semiconductor substrate 12 by a predetermined distance. The “length of the side extending in the y direction of the second active region 16” is shorter than the “length of the short side of the first active region 14”.

  Note that, like the first active region 14, the second active region 16 has a cell region 16a and a termination region 16b that surrounds the cell region 16a. A plurality of gate electrodes 17 are formed in the cell region 16a. The plurality of gate electrodes 17 extend in the y direction in FIG. 1 and are arranged at intervals in the x direction in FIG. 1, similarly to the gate electrode 36 in the first active region 14. In addition, three termination trenches 19 are formed in the termination region 16b, and the termination trench 19 makes a round around the cell region 16a. Since the cell region 16a and the termination region 16b have the same structure as that of the first active region 14, the description thereof is omitted here. The source electrode 38 formed in the first active region 14 and the source electrode formed in the second active region 16 are connected by a metal layer (not shown). Therefore, by simply bonding a wire to one of the source electrode of the first active region 14 and the source electrode of the second active region 16, each source electrode of the first active region 14 and the second active region 16 is connected to an external circuit. can do.

  Next, the inactive region 21 will be described. As shown in FIGS. 1 and 2, the inactive region 21 is formed in a region of the semiconductor substrate 12 other than the first active region 14 and the second active region 16. An insulating film 50 (see FIG. 2) is formed on the surface of the inactive region 21, and a gate pad 18 and gate wirings 20a, b, c, and d are formed on the insulating film 50. One end of a wire (not shown) is bonded to the gate pad 18 and connected to an external circuit by this wire. The gate wirings 20a, b, c, and d are wirings for electrically connecting the gate pad 18 and the gate electrodes 17 and 36. In FIG. 1, the gate wirings 20a, b, c, and d are hatched with diagonal lines in consideration of easy viewing.

  As shown in FIG. 1, the gate pad 18 is formed in a rectangular shape (substantially square shape) when the semiconductor substrate 12 is viewed in plan. The gate pad 18 is disposed at the lower left corner of the semiconductor substrate 12. As is clear from FIG. 1, the gate pad 18 is arranged side by side in the direction (x direction) in which the long side of the first active region 14 extends with respect to the first active region 14. The gate pad 18 is arranged side by side in the direction (y direction) in which the short side of the first active region 14 extends with respect to the second active region 16. One side of the gate pad 18 extending in the x direction is parallel to the long side of the semiconductor substrate 12 and extends along the long side of the semiconductor substrate 12. The other side of the gate pad 18 extending in the x direction extends at a position away from the long side of the semiconductor substrate 12 by a predetermined distance. “The length of the side extending in the x direction of the gate pad 18” is shorter than “the length of the long side of the first active region 14”, and “the length of the side extending in the x direction of the second active region”. Has been slightly longer than the length of. Further, the sum of “the length of the long side of the first active region 14” and “the length of the side of the gate pad 18 extending in the x direction” is slightly shorter than the long side of the semiconductor substrate 12.

  On the other hand, one of the sides of the gate pad 18 extending in the y direction is parallel to the short side of the semiconductor substrate 12 and extends along the short side of the semiconductor substrate 12. The other side of the gate pad 18 extending in the y direction extends a position away from the short side of the semiconductor substrate 12 by a predetermined distance. The “length of the side extending in the y direction of the gate pad 18” is shorter than the “length of the side extending in the y direction of the first active region 14”. Further, the sum of “the length of the side extending in the y direction of the second active region 16” and “the length of the side extending in the y direction of the gate pad 18” is slightly shorter than the short side of the semiconductor substrate 12; The length of the side of one active region 14 extending in the y direction is substantially equal.

  Note that one end portion (left end portion in the figure) of each gate electrode 17 in the second active region 16 is connected to the gate pad 18 by a wiring (not shown). Therefore, the potential applied to the gate pad 18 is directly applied to the left end portion of each gate electrode 17 via a wiring (not shown). Since the gate pad 18 and each gate electrode 17 are directly connected by wiring, no gate wiring extending along the outer periphery of the second active region 16 is provided between the second active region 16 and the gate pad 18. This prevents an increase in the area of the inactive region.

  The gate wirings 20a, 20b, 20c, and 20d are formed along the outer periphery of the semiconductor substrate 12 when the semiconductor substrate 12 is viewed in plan view. The gate wiring 20 a is formed along the long side of the semiconductor substrate 12. One end of the gate wiring 20 a is connected to the gate pad 18. One end portion (left end portion in the figure) of each gate electrode 36 in the first active region 14 is connected to the gate wire 20a by a wire (not shown). Therefore, the potential applied to the gate pad 18 is applied to the left end portion of each gate electrode 36 in the first active region 14 via the gate wiring 20a.

  The gate wiring 20 b is formed along the short side of the semiconductor substrate 12. One end of the gate wiring 20b is connected to the other end of the gate wiring 20a. The gate wiring 20 b is not directly connected to the gate electrodes 17 and 36 in the active regions 14 and 16.

  The gate wiring 20 c is formed along the long side of the semiconductor substrate 12. One end of the gate line 20c is connected to the other end of the gate line 20b. The gate wiring 20c is connected to the other end (the right end in the figure) of each gate electrode 36 in the first active region 14 and the other end (the other end of each gate electrode 17 in the second active region 16) by a wiring (not shown). The right end of the figure) is connected. Accordingly, the potential applied to the gate pad 18 is applied to the left end portions of the gate electrodes 17 and 36 in the active regions 14 and 16 through the gate wiring 20c.

  The gate wiring 20 d is formed along the short side of the semiconductor substrate 12. One end of the gate line 20d is connected to the other end of the gate line 20c, and the other end of the gate line 20d is connected to the gate pad 18. The gate wiring 20 d is not directly connected to the gate electrodes 17 and 36 in the active regions 14 and 16.

  As is clear from FIG. 1, no gate wiring is provided between the first active region 14 and the second active region 16. The space between the first active region 14 and the second active region 16 can be reduced by the amount that the gate wiring is not provided, and the areas of the active regions 14 and 16 can be increased.

  When the semiconductor device 10 described above is used, the drain electrode 22 is connected to the power supply potential, and the source electrode 38 is connected to the ground potential. When the potential applied to the gate pad 18 is less than the threshold potential, the semiconductor device 10 is off. In a state where the semiconductor device 10 is turned off, a depletion layer spreads from the interface between the body region 32 and the drift region 26 and from the interface between the diffusion regions 28 and 52 and the drift region 26. By forming the depletion layer in a wide range, the breakdown voltage of the semiconductor device 10 is improved. Moreover, the 1st active region 14 and the 2nd active region 16 are exhibiting the rectangular shape when planarly viewed, and the inner radius part is not formed. For this reason, the breakdown voltage of the semiconductor device 10 is prevented from decreasing.

  When the potential applied to the gate pad 18 is equal to or higher than the threshold potential, the semiconductor device 10 is turned on. That is, in the first active region 14, the potential applied to the gate pad 18 is applied from the gate wirings 20 a and 20 c to both ends (both ends in the longitudinal direction) of the gate electrode 36. When the potential applied to the gate electrode 36 is equal to or higher than the threshold potential, a channel is formed in the body region 32 in the range in contact with the insulator 34. As a result, electrons flow from the source electrode 38 to the drain electrode 22 through the source region 42, the channel of the body region 32, the drift region 26, and the drain region 24. That is, a current flows from the drain electrode 22 to the source electrode 38. In this embodiment, the gate electrode 36 extends in the direction of the short side of the first active region 14, thereby suppressing the length of the gate electrode 36 in the longitudinal direction. A gate potential is applied to both ends of the gate electrode 36 from the gate wirings 20a and 20c. Therefore, the potential applied to the gate electrode 36 in a short time after the threshold potential is applied to the gate pad 18 becomes equal to or higher than the threshold potential, and the switching speed of the semiconductor device 10 is improved.

  In the second active region 16, the potential applied to the gate pad 18 is directly applied to one end (one end in the longitudinal direction) of the gate electrode 17 from the gate pad 18 via a wiring (not shown). It is applied to the other end (the other end in the longitudinal direction) of the gate electrode 17 through 20c. When the potential applied to the gate electrode 17 becomes equal to or higher than the threshold potential, a current flows through the semiconductor device 10 as in the first active region 14. In this embodiment, since the gate potential is applied to both ends of the gate electrode 17, the potential applied to the gate electrode 17 in a short time after the threshold potential is applied to the gate pad 18 becomes equal to or higher than the threshold potential. The switching speed is improved.

  As is clear from the above description, in the semiconductor device 10 of this example, the inner radius portion is not formed in the first active region 14 and the second active region 16. This prevents the breakdown voltage of the semiconductor device 10 from decreasing. In addition, the gate pad 18 and the second active region 16 are arranged along the short side of the first active region 14, and the gate pad 18 and the second active region 14 are disposed within the approximate width of the short side of the first active region 14. . Therefore, the area of the gate pad 18 is reduced by the amount of the second active region 16 as compared with the conventional layout (see FIG. 4A). That is, the active region can be expanded by the amount of the second active region 16. As a result, the effective area of the semiconductor substrate 12 is increased, and the on-resistance of the semiconductor device 10 can be reduced.

  In the semiconductor device 10 described above, the gate wiring is not formed between the first active region 14 and the second active region 16, and the second active region 16 and the gate pad 18 are also connected to the second active region 16. No gate wiring is formed along the outer periphery of the active region 16. The space between the first active region 14 and the second active region 16 can be narrowed by the amount that the gate wiring is not formed, and the space between the second active region 16 and the gate pad 18 can be narrowed. This also increases the area of the active region and increases the effective area of the semiconductor substrate 12.

  Although the semiconductor device 10 according to the embodiment of the present specification has been described above, the technology disclosed in the present specification is not limited to the embodiment described above. For example, in the embodiment described above, the gate pad 18 has a substantially square shape, but the shape of the gate pad can take various shapes (for example, a rectangular shape or the like) within a range where wire bonding is possible. In order to increase the area of the active region of the semiconductor substrate, it is preferable that the gate pad has a minimum area that allows wire bonding.

  Further, the technology disclosed in this specification is not limited to the layout shown in the above-described embodiments, and various layouts can be adopted. For example, a layout as shown in FIG. 3 can be adopted. The layout shown in FIG. 3 differs from the above-described embodiment in that a third active region is formed on the left side of the gate pad.

  In the semiconductor device 60 shown in FIG. 3, a first active region 64, a second active region 66, a third active region 68, and a gate pad 70 are disposed on a semiconductor substrate 62. Each active region 64, 66, 68 has the same structure as the active regions 14, 16 of the above-described embodiment. In the semiconductor device 60, by forming the plurality of active regions 64, 66, 68 on the semiconductor substrate 62, the area of each active region 64, 66, 68 is prevented from becoming too large. This prevents an increase in the time until each active region 64, 66, 68 is turned on. The gate electrodes 65, 67, 69 of the active regions 64, 66, 68 extend in the direction (y direction) in which the short sides of the active regions 64, 66, 68 extend. This also suppresses the length in the longitudinal direction of the gate electrodes 65, 67, and 69, and prevents the time until each active region 64, 66, and 68 is turned on from being increased.

  As in the above-described embodiment, the gate pad 70 and the second active region 66 are arranged side by side in the y direction, and the short side of the first active region 64 is below the first active region 64 (x direction). It is arranged within the approximate width. The length of the gate pad 70 in the y direction is shorter than the length of the short side of the first active region 64, and the second active region 66 is disposed in a space that can be formed by shortening the length of the gate pad 70 in the y direction. ing. The length of the second active region 66 in the x direction is slightly shorter than the length of the gate pad 70 in the x direction. The third active region 68 is disposed on the left side of the first active region 64 and the gate pad 70. The first active region 64 and the gate pad 70 are disposed within the approximate width of the long side (side in the x direction) of the third active region 68.

  Gate wirings 72 a, 72 b, 72 c, 72 d, 72 e, 72 f are formed on the surface of the inactive region 74 of the semiconductor substrate 62. Gate wirings 72 a, 72 c, 72 d, 72 e, 72 f are formed along the outer periphery of the semiconductor substrate 62. The gate wiring 72 b is formed between the first active region 64 and the third active region 68. A potential is applied to each end portion of the gate electrode 65 in the first active region 64 from the gate wirings 72b and 72f. In addition, a potential is applied to each end portion of the gate electrode 67 in the second active region 66 from the gate wiring 72 f and directly from the gate pad 70. Further, a potential is applied to each end portion of the gate electrode 69 in the third active region 68 from the gate wirings 72 c and 72 b and a potential is directly applied from the gate pad 70.

Also in the semiconductor device 60 shown in FIG. 3, since the inner radius portion is not formed in the active regions 64, 66, and 68, the breakdown voltage of the semiconductor device 60 is prevented from being lowered. In the semiconductor device 60, the second active region 66 is disposed in a space that can be reduced by reducing the area of the gate pad 70, thereby increasing the area of the active region.
Further, by forming the gate wiring 72b between the first active region 64 and the third active region 68, the potential of the gate pad 70 is applied to the gate electrodes 65 and 69 through the gate wiring 72b. As a result, the switching speed of the semiconductor device 60 is improved. On the other hand, the area of the active region is increased by not forming a gate wiring between the first active region 64 and the second active region 66.

  In each of the above-described embodiments, the MOSFET is formed on the semiconductor substrate. However, other semiconductor elements (for example, IGBT) can be formed on the semiconductor substrate.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Semiconductor substrate 14: First active region 14a: Cell region 14b: Termination region 16: Second active region 16a: Cell region 16b: Termination region 17: Gate electrode 18: Gate pads 20a, 20b, 20c, 20d: Gate wiring 36: Gate electrode

Claims (2)

A first active region formed in a semiconductor substrate;
A second active region formed in the semiconductor substrate;
A non-active region formed in a region other than the first active region and the second active region in the semiconductor substrate;
Having a gate pad formed on an insulating film formed on the surface of the inactive region ;
Each of the first active region and the second active region has an element region and a termination region surrounding the element region.
The element regions of the first active region and the second active region are
A body region of a first conductivity type formed in a range facing the upper surface in the semiconductor substrate;
A second conductivity type drift region in contact with the lower surface of the body region;
A gate electrode disposed in a gate trench extending through the body region to the drift region and facing the body region;
An insulator disposed between the gate electrode and the wall surface of the gate trench;
A floating region of a first conductivity type surrounding the bottom of the gate trench and surrounded by a drift region;
In each of the termination regions of the first active region and the second active region, a termination trench that makes a circuit around the outside of the element region is formed, and the periphery of the termination trench is surrounded by a drift region. A floating region of the first conductivity type is formed,
The gate pad is electrically connected to the respective gate electrodes of the first active region and the second active region,
When the semiconductor substrate is viewed in plan,
(1) The semiconductor substrate has a rectangular shape in which one side is a long side while the other side is a short side,
( 2 ) The first active region has a rectangular shape in which one side is a long side while the other side is a short side,
( 3 ) The second active region has a rectangular shape and is arranged side by side in a direction in which the long side of the first active region extends with respect to the first active region,
( 4 ) The gate pad has a rectangular shape and is arranged side by side in a direction in which the long side of the first active region extends with respect to the first active region,
( 5 ) The second active region and the gate pad are arranged side by side in the direction in which the short side of the first active region extends,
( 6 ) The length of the side of the second active region extending in the direction parallel to the short side of the first active region is shorter than the length of the short side of the first active region,
( 7 ) The length of the side extending in the direction parallel to the short side of the first active region of the gate pad is shorter than the length of the short side of the first active region,
( 8 ) The length of the side extending in the direction parallel to the long side of the first active region of the gate pad is shorter than the length of the long side of the first active region,
( 9 ) The length of the side of the second active region extending in the direction parallel to the long side of the first active region is slightly shorter than the length of the side of the gate pad extending in the direction parallel to the long side of the first active region. Has been
( 10 ) The sum of the length of the side of the second active region extending in the direction parallel to the short side of the first active region and the length of the side of the gate pad extending in the direction parallel to the short side of the first active region is The length is substantially equal to the length of the side extending in the direction parallel to the short side of the first active region, and is slightly shorter than the short side of the semiconductor substrate,
(11) The sum of the long side length of the first active region and the length of the side extending in the direction parallel to the long side of the first active region of the gate pad is slightly shorter than the long side of the semiconductor substrate. ,
Each element region of the first active region and the second active region has a plurality of gate electrodes,
The plurality of gate electrodes in each element region extend in the direction in which the short side of the first active region extends when the semiconductor substrate is viewed in plan, and are spaced in the direction in which the long side of the first active region extends. Arranged side by side,
On the insulating film formed on the surface of the inactive region , a gate wiring that is conductive to the gate pad and conductive to the gate electrode is formed.
The gate wiring is provided along two long sides of the first active region when the semiconductor substrate is viewed in plan, and no gate wiring is provided between the first active region and the second active region. And provided along the side of the second active region that is not adjacent to the gate pad, of the two sides parallel to the long side of the first active region, and between the second active region and the gate pad. Is provided with no gate wiring extending along the second active region.   The element region of the first active region further includes a first surface electrode provided on the surface of the semiconductor substrate, and the element region of the second active region includes a second surface electrode provided on the surface of the semiconductor substrate. The semiconductor device according to claim 1, further comprising: a first surface electrode and a second surface electrode connected by a metal layer.

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