JP5621357B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including a capacitor.

  A semiconductor element provided with a MIM (Metal Insulator Metal) capacitive element is known. As the MIM capacitor element, a wiring formed above the semiconductor substrate and extending in parallel is used. A capacitance is formed between the wirings extending in parallel.

JP 2004-247659 A JP 2006-120883 A

  When designing a semiconductor device, there is a method of forming a chip having a large function by combining macros having a small circuit function. As described above, when a circuit is designed by combining macros, the macro may be rotated 90 degrees in consideration of arrangement efficiency. When the macro including the MIM capacitor element is rotated 90 degrees, the extending direction of the wiring is rotated 90 degrees. In the manufacturing process of a semiconductor device, for example, due to the characteristics of a manufacturing apparatus such as a lithography apparatus, the width of the wiring may differ depending on the extending direction of the wiring. When the wiring width is different, the capacitance value of the MIM capacitor element is different. As a result, the capacitance value planned as the design value of the MIM capacitance element is different from the actual capacitance value.

  As described above, if the capacitance value differs when the MIM capacitive element is rotated 90 degrees, there is a possibility that the circuit design may be hindered.

  An object of the present semiconductor device is to suppress a difference in capacitance value due to the arrangement of capacitive elements.

For example, a plurality of second wirings provided a plurality of first wiring, the opposed alternately with the plurality of first wiring through the plurality of first wirings and the insulating body extends in a first direction, said plurality A plurality of first capacitors that are connected to each of the first wirings and extend in a second direction perpendicular to the first direction, and electrically connected to the plurality of first wirings a plurality of fourth wirings provided extending in the second direction are connected to the second wiring and the fifth face and a plurality of which are provided via an electrically connected to said plurality of fourth wiring and insulators comprising a wiring, and a plurality of second capacitive element and a sixth wirings extending respectively and connected to the third wiring the first direction of the plurality of fourth wirings, the third When the origin is the point where the wiring and the sixth wiring are connected, the first capacitive element is placed in the second quadrant and the fourth quadrant. A plurality of second capacitive elements arranged in the first quadrant and the third quadrant, and connected to the second wiring in the second quadrant and the fourth quadrant and extending in the second direction. A seventh wiring, a plurality of eighth wirings connected to each of the fifth wirings in the first quadrant and the third quadrant and extending in the first direction, and the first wiring located farthest from the origin Including the second wiring in the second quadrant and the fourth quadrant, and the fifth wiring in the first quadrant and the third quadrant farthest from the origin, and the plurality of first wirings and the plurality of wirings 4 comprises an outer wires surrounding the wires, the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, the sixth wiring and the outer peripheral wirings first wiring layer provided, the length of the first wiring and the second wiring are opposed, the fourth distribution in The semiconductor device is characterized in that equal to the length of the fifth wiring facing the use.

  According to this semiconductor device, a difference in capacitance value due to the arrangement of the capacitive elements can be suppressed.

FIGS. 1A to 1D are top views of the MIM capacitor elements A to D, respectively. FIG. 2 is a schematic cross-sectional view of FIG. FIG. 3 is a diagram showing the results of calculating the capacitance values of the capacitive elements A to D. FIG. 4A is a plan view of the capacitive element according to the second embodiment, and FIG. 4B is a plan view of the capacitive element rotated 90 degrees. FIG. 5A is a plan view of the capacitive element according to the third embodiment, and FIG. 5B is a plan view of the capacitive element rotated 90 degrees. FIG. 6A is a plan view of the capacitive element according to the fourth embodiment, and FIG. 6B is a plan view of the capacitive element rotated 90 degrees. FIG. 7A is a plan view of the capacitive element according to the fifth embodiment, and FIG. 7B is a plan view of the capacitive element rotated 90 degrees. FIG. 8A is a plan view of the capacitive element according to the sixth embodiment, and FIG. 8B is a plan view of the capacitive element rotated 90 degrees. FIG. 9 is a diagram in which the capacitor element and the wiring layer in Example 6 are overlapped. FIG. 10A is a plan view of the capacitive element according to the seventh embodiment, and FIG. 10B is a plan view of the capacitive element rotated 90 degrees. FIG. 11A is a plan view of the capacitive element according to the eighth embodiment, and FIG. 11B is a plan view of the capacitive element rotated 90 degrees. 12A is a plan view of the capacitive element according to the ninth embodiment, and FIG. 12B is a cross-sectional view taken along the line AA. FIG. 13A is a plan view of the capacitor according to Example 10, and FIG. 13B is a cross-sectional view taken along the line AA. FIG. 14 is a cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device including the capacitive element. FIG. 15 is a cross-sectional view (No. 2) illustrating the method for manufacturing the semiconductor device including the capacitor. FIG. 16 is a cross-sectional view (No. 3) illustrating the method for manufacturing the semiconductor device including the capacitive element. FIG. 17 is a cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device including the capacitor. FIG. 18 is a cross-sectional view (No. 5) illustrating the method for manufacturing the semiconductor device including the capacitor.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIGS. 1A to 1D are top views of the MIM capacitor elements A to D, respectively. FIG. 1A is an example in which the width of the wiring does not change from the design dimension in the X direction and the Y direction. FIG. 2 is a schematic cross-sectional view of FIG. As shown in FIG. 2, a wiring layer 48 is formed on the insulating layer 40 above the semiconductor substrate. An insulating layer 42 is provided between the wiring layers 48. An insulating layer 44 is provided on the wiring layer 48 and the insulating layer 42. The insulating layers 40, 42, and 44 are, for example, silicon oxide. Alternatively, a dielectric film having a low dielectric constant may be used. The wiring layer 48 is a metal such as Cu, Al, or W, for example.

  As shown in FIG. 1A, the comb wirings 12 and 14 face each other so as to mesh with each other. The comb wiring 12 includes a first wiring 12a extending in the Y direction. The comb wiring 14 includes a second wiring 14a extending in the Y direction. The wiring layer 48 in FIG. 2 corresponds to the first wiring 12a and the second wiring 14a. The first wiring 12a and the second wiring 14a are provided to face each other with the insulating layer 42 interposed therebetween. The first wiring 12a and the second wiring 14a are provided in parallel. The length of the first wiring 12a and the second wiring 14a facing each other is La. The interval between the first wiring 12a and the second wiring 14a is Wa. In the example of FIG. 1A, the capacitive element A has a length of 8 × La and a wiring interval Wa.

  FIG. 1B shows a case in which, in the capacitive element shown in FIG. 1A, the width of the wiring becomes thicker in the X direction and thinner in the Y direction due to the characteristics of the manufacturing apparatus. As shown in FIG. 1B, the first wiring 12a and the second wiring 14a of the capacitive element B are thicker than the capacitive element A of FIG. For this reason, the interval Wb between the first wiring 12a and the second wiring 14a is smaller than Wa. If the length La is sufficiently long, the change of the length La can be ignored. Therefore, the capacitive element B is a capacitive element having a length of 8 × La and a wiring interval of Wb.

  FIG. 1C shows a case in which the width of the wiring becomes thicker in the X direction and thinner in the Y direction due to the characteristics of the manufacturing device in the capacitive element in which the capacitive element A of FIG. Show. The comb-shaped wirings 16 and 18 each include a third wiring 16a and a fourth wiring 18a extending in the X direction. The third wiring 16a and the fourth wiring 18a are provided to face each other through the insulating layer 42 (see FIG. 2). The third wiring 16a and the fourth wiring 18a are provided in parallel. As shown in FIG. 1C, the third wiring 16a and the fourth wiring 18a of the capacitive element C are thinner than the capacitive element A of FIG. For this reason, the interval Wc between the third wiring 16a and the fourth wiring 18a is larger than Wa. If the length La is sufficiently long, the change of the length La can be ignored. Therefore, the capacitive element C is a capacitive element having a length of 8 × La and a wiring interval Wc.

  FIG. 1D illustrates the capacitive element D according to the first embodiment. The capacitive element D includes a first capacitive element 22 including comb-shaped wirings 12 and 14 and a second capacitive element 24 including comb-shaped wirings 16 and 18. The first wiring 12a and the second wiring 14a extend in the Y direction, and the third wiring 16a and the fourth wiring 18a extend in the X direction. The first wiring 12a, the second wiring 14a, the third wiring 16a, and the fourth wiring 18a are provided in the same wiring layer. For example, the first wiring 12a, the second wiring 14a, the third wiring 16a, and the fourth wiring 18a are formed in the same Z plane. The first wiring 12a and the third wiring 16a are electrically connected, and the second wiring 14a and the fourth wiring 18a are electrically connected. Therefore, the capacitive element D has a capacitance in which a first capacitive element 22 having a length of 4 × La and a wiring interval Wb and a second capacitive element 24 having a length of 4 × La and a wiring interval Wc are connected in parallel. It is an element.

  FIG. 3 is a diagram showing the results of calculating the capacitance values of the capacitive elements A to D. The length La was 100 μm, the design value of the wiring interval was 100 nm, the film thickness of the wiring layer 48 was 300 nm, and the relative dielectric constant of the insulating layers 40, 42, and 44 was 3.0. The width of the wiring layer 48 is 5% thicker in the X direction and 5% thinner in the Y direction. As shown in FIG. 3, the capacitance value (design value) of the capacitive element A is 63.7 fF. On the other hand, in the capacitive element B, the capacitance value increases by 5.3% compared to the capacitive element A. On the other hand, in the capacitive element C, the capacitance value is reduced by 4.8% compared to the capacitive element A. As described above, the capacitance value greatly varies as the capacitance element rotates 90 degrees.

  As shown in FIG. 3, the capacitance value of the capacitive element D is only increased by 0.3% with respect to the capacitive element A. This is because the increase in the capacitance value in the first capacitance element 22 and the decrease in the capacitance value in the second capacitance element 24 are offset.

  According to the first embodiment, the length 4 × La in which the first wiring 12a and the second wiring 14a face each other, and the third wiring 16a and the fourth wiring 18a that extend perpendicular to the first wiring 12a and the second wiring 14a. Is equal to the length 4 × La facing each other. Thereby, as shown in FIG. 3, the capacitance value can be made substantially the same as the design value. Thus, the difference in capacitance value due to the arrangement of the capacitive elements can be suppressed.

  In addition, the comb wiring 12 and the comb wiring 14 are divided into a plurality of first wirings 12a and a plurality of second wirings 14a, respectively. The plurality of first wirings 12a and the plurality of second wirings 14a each form, for example, a comb-type wiring structure. The plurality of divided first wires 12a and the plurality of second wires 14a are provided alternately. Similarly, the comb wiring 16 and the comb wiring 18 are divided into a plurality of third wirings 16a and a plurality of fourth wirings 18a, respectively, and the plurality of divided third wirings 16a and the plurality of fourth wirings 18a are alternately arranged. Is provided. Thereby, the shape of the capacitive element can be arbitrarily designed to be, for example, a square or a rectangle.

  Further, the length La in which the plurality of divided first wires 12a and the plurality of divided second wires 14a face each other is the same, and the plurality of fourth wires divided from the plurality of divided third wires 16a. The length La of which the wiring 18a and a are opposed to each other can be the same. This facilitates the design.

  Further, the number of divided first wires 12a and the number of divided third wires 16a are the same, and the number of divided second wires 14a and the number of divided fourth wires 18a are: The same can be done. This facilitates the design.

  The second embodiment is an example in which the first capacitor element and the second capacitor element are arranged in the Y direction. FIG. 4A is a plan view of the capacitive element according to the second embodiment, and FIG. 4B is a plan view of the capacitive element rotated 90 degrees. There are seven places where the first wiring 12a and the second wiring 14a face each other in the first capacitive element 22, and there are seven places where the third wiring 16a and the fourth wiring 18a face each other in the second capacitive element 24. Therefore, the length of the first wiring 12a and the second wiring 14a facing each other is 7 × La, and the length of the third wiring 16a and the fourth wiring 18a facing each other is equal to 7 × La. The first wiring 12 a and the third wiring 16 a are connected to the electrode pad 32 by the wiring 15. The second wiring 14 a and the fourth wiring 18 a are connected to the electrode pad 30 by the wiring 17. The capacitance between the electrode pad 30 and the electrode pad 32 is almost the same between FIG. 4A and FIG. 4B even if the thickness of the wiring is different in the X direction and the Y direction due to the characteristics of the manufacturing apparatus. Will be equal.

  Further, in the first embodiment, since the comb-shaped wiring 14 shares one of the plurality of third wirings 16a and the wiring 14d that connects the second wirings 14a, the chip area can be reduced. Thus, one of the wiring connecting the plurality of first wirings 12a and the wiring connecting the plurality of second wirings 14a is one of the plurality of third wirings 16a or one of the plurality of fourth wirings 18a. You may use as one.

  The third embodiment is an example in which the first capacitor element 22 and the second capacitor element 24 are arranged in an oblique direction. FIG. 5A is a plan view of the capacitive element according to the third embodiment, and FIG. 5B is a plan view of the capacitive element rotated 90 degrees. In the third embodiment, the first capacitive element 22 and the second capacitive element 24 are arranged in the XY direction. The comb wirings 12 and 16 are directly connected to the electrode pads 32, respectively, and the comb wirings 14 and 18 are respectively connected directly to the electrode pads 30. Other configurations are the same as those of the second embodiment, and the description thereof is omitted.

  FIG. 6A is a plan view of the capacitive element according to the fourth embodiment, and FIG. 6B is a plan view of the capacitive element rotated 90 degrees. In the fourth embodiment, the first capacitive element 22 and the second capacitive element 24 are arranged in the XY direction. In the fourth embodiment, the comb wirings 12 and 16 are directly connected and connected to the electrode pad 32 by the wiring 15. Comb wirings 14 and 18 are directly connected and connected to the electrode pad 30 by the wiring 17. Other configurations are the same as those of the third embodiment, and the description thereof is omitted.

Example 5 is an example in which two first capacitive elements and two second capacitive elements are provided.
FIG. 7A is a plan view of the capacitive element according to the fifth embodiment, and FIG. 7B is a plan view of the capacitive element rotated 90 degrees. In the fifth embodiment, the center of the capacitive element is the origin, the first capacitive element 22 is arranged in the second and fourth quadrants, and the second capacitive element 24 is arranged in the first and third quadrants.

  The outermost periphery is formed by the wiring 14d, the wiring 18d, the second wiring 14a, the fourth wiring 18a, the extended second wiring 14b, and the extended fourth wiring 18b. The wiring 14 d connects the second wiring 14 a in the comb wiring 14. The wiring 18 d connects the fourth wiring 18 a in the comb wiring 18. The extended second wiring 14b is opposed to the first wiring 12a except for the second wiring 14a. The extended fourth wiring 18b is opposed to the third wiring 16a except for the fourth wiring 18a.

  In the fifth embodiment, the length of the first wirings 12a and 12b and the second wirings 14a and 14b facing each other is 14 × La + 2 × Lb. The lengths of the third wirings 16a and 16b and the fourth wirings 18a and 18b are the same. Therefore, also in Example 5, even if the capacitive element is rotated 90 degrees, the change in the capacitance value can be suppressed.

  Further, the wiring 12d connecting the plurality of first wirings 12a in each of the second quadrant and the fourth quadrant is also used as one of the plurality of third wirings 16a in the first quadrant and the third quadrant. Further, the wiring 16d connecting the plurality of third wirings 16a in each of the first quadrant and the third quadrant is also used as one of the plurality of first wirings 12a in the second quadrant and the fourth quadrant, respectively. Thereby, the chip size can be reduced.

  Further, the outer peripheral wiring is formed by the wiring 14d, the wiring 18d, the second wiring 14a, the fourth wiring 18a, the extended second wiring 14b, and the extended fourth wiring 18b. The outer peripheral wiring surrounds the first wiring 12a and the third wiring 16a. Therefore, the capacitance value of the extended second wiring 14b and the extended fourth wiring 18b can be increased.

  Since the outermost periphery is surrounded by the comb wirings 14 and 18 as described above, the comb wirings 12 and 16 are connected to the upper or lower wiring layer using the contacts 34. In FIG. 7A and FIG. 7B, the comb wirings 14 and 18 are also connected to other wiring layers using the contacts 36, but are drawn out using the same wiring layer as the comb wirings 14 and 18. Also good.

  FIG. 8A is a plan view of the capacitive element according to the sixth embodiment, and FIG. 8B is a plan view of the capacitive element rotated 90 degrees. As shown in FIGS. 8A and 8B, in the sixth embodiment, five contacts 34 connected to the comb-shaped wirings 12 and 16 and four contacts 36 connected to the comb-shaped wirings 14 and 18 are used. It is said. As described above, by using a plurality of contacts 34 and 36, it is possible to suppress external disturbance factors to the capacitive element due to the parasitic resistance. In order to equalize the parasitic resistance, the contacts 34 and 36 are preferably arranged symmetrically.

  FIG. 9 is a diagram in which the capacitive elements 22 and 24 and the wiring layer 38 in Example 6 are overlapped. The wiring layer 38 is formed above or below the wiring layer in which the capacitive elements 22 and 24 are formed, and is electrically connected to the contact 34. The wiring layer 38 is preferably thickened to reduce parasitic resistance. For example, the wiring layer 38 is preferably thicker than the first wiring 12a, the second wiring 14a, the third wiring 16a, and the fourth wiring 18a.

  Example 7 is an example in which there is no extended wiring. FIG. 10A is a plan view of the capacitive element according to the seventh embodiment, and FIG. 10B is a plan view of the capacitive element rotated 90 degrees. As shown in FIGS. 10A and 10B, the extended second wiring 14b and fourth wiring 18b are not provided as compared with the fifth embodiment. For this reason, the comb wirings 14 and 18 in each quadrant are isolated from each other. For this reason, contacts 36 connected to the comb wirings 14 and 18 in each quadrant are provided, and the comb wirings 14 and 18 are electrically connected in the upper or lower wiring layer. The length of the first wiring 12a and the second wiring 14a facing each other is 14 × La. The lengths of the third wiring 16a and the fourth wiring 18a facing each other are the same. Other configurations are the same as those of the fifth embodiment, and the description thereof is omitted.

  FIG. 11A is a plan view of the capacitive element according to the eighth embodiment, and FIG. 11B is a plan view of the capacitive element rotated 90 degrees. As shown in FIGS. 11A and 11B, in the eighth embodiment, five contacts 34 connected to the comb wirings 12 and 16 and four contacts 36 connected to the comb wirings 14 and 18 are used. It is said. As described above, by using a plurality of contacts 34 and 36, it is possible to suppress external disturbance factors to the capacitive element due to the parasitic resistance. In order to equalize the parasitic resistance, the contacts 34 and 36 are preferably arranged symmetrically.

  Example 9 is an example in which the first capacitor 22 and the second capacitor 24 are formed in a plurality of layers. 12A is a plan view of the capacitive element according to the ninth embodiment, and FIG. 12B is a cross-sectional view taken along the line AA. As shown in FIGS. 12A and 12B, the first wiring 12c, the second wiring 14c, the second wiring 14a, the first wiring 12c, the second wiring 14a, A third wiring 16c and a fourth wiring 18c are formed. The first wiring 12a, the second wiring 14a, the third wiring 16a and the fourth wiring 18a and the first wiring 12c, the second wiring 14c, the third wiring 16c and the fourth wiring 18c have the same pattern.

  As shown in FIG. 12B, the lower wiring layer 48 is formed on the insulating layer 40. An insulating layer 42 is formed between the lower wiring layers 48. An insulating layer 44 is formed on the lower wiring layer 48 and the insulating layer 42. A metal contact 52 penetrating in the vertical direction is formed in the insulating layer 44. Metal contact 52 corresponds to contacts 34 and 36. An upper wiring layer 50 is formed on the insulating layer 44. An insulating layer 46 is formed between the upper wiring layers 50. In FIG. 12B, the wirings 12 a to 18 a are formed by the upper wiring layer 50, and the wirings 12 c to 18 c are formed by the lower wiring layer 48.

  As in the ninth embodiment, the first wiring, the second wiring, the third wiring, and the fourth wiring are formed in a plurality of stacked wiring layers, respectively. The first wiring, the second wiring, the third wiring, and the fourth wiring formed in the plurality of wiring layers are respectively connected by contacts penetrating vertically through an insulating layer provided between the plurality of stacked wiring layers. Yes. Thereby, the capacitance value per unit area can be increased. Although the example in which the first wiring, the second wiring, the third wiring, and the fourth wiring are formed in two layers has been described in the ninth embodiment, the first wiring, the second wiring, and the third wiring are formed in three or more layers. A wiring and a fourth wiring may be formed.

  FIG. 13A is a plan view of the capacitor according to Example 10, and FIG. 13B is a cross-sectional view taken along the line AA. FIG. 13A illustrates a wiring layer 39 and an intermediate wiring layer 37 connected to the capacitive elements 22 and 24 in an overlapping manner. As shown in FIG. 13B, the lower wiring layer 48 is formed on the insulating layer 40. An insulating layer 42 is formed between the lower wiring layers 48. An insulating layer 44 is formed on the lower wiring layer 48 and the insulating layer 42. A metal contact 56 penetrating in the vertical direction is formed in the insulating layer 44. An intermediate wiring layer 57 is formed on the insulating layer 44. An insulating layer 43 is formed between the intermediate wiring layers 57. An insulating layer 45 is formed on the intermediate wiring layer 57 and the insulating layer 43. A metal contact 52 penetrating in the vertical direction is formed in the insulating layer 45. An upper wiring layer 50 is formed on the insulating layer 45. An insulating layer 46 is formed between the upper wiring layers 50.

  The capacitive elements 22 and 24 in FIG. 13A are formed by the lower wiring layer 48 in FIG. The contact 34 in FIG. 13A is formed by the metal contacts 52 and 56 in FIG. 13B. The intermediate wiring layer 37 in FIG. 13A is formed by the intermediate wiring layer 57 in FIG. The wiring layer 39 in FIG. 13A is formed by the upper wiring layer 50 in FIG. As described above, the comb wirings 12 and 16 of the capacitive elements 22 and 24 are electrically connected to the wiring layer 39 through the metal contact 56, the intermediate wiring layer 37, and the metal contact 52.

  With this structure, as shown in FIG. 9 of the sixth embodiment, compared to the case where the wiring immediately above or directly below the wiring layer on which the capacitive elements 22 and 24 are formed is used as the lead-out wiring layer 38, the capacitive elements 22 and 24 and The distance from the lead wiring layer 39 can be increased. Therefore, parasitic capacitance between the capacitive elements 22 and 24 and the lead-out wiring layer 39 can be suppressed. In FIG. 13B, the upper wiring layer 50 is used as the lead-out wiring layer 39 and the lower wiring layer 48 is used as the wiring layer for forming the capacitive elements 22 and 24. However, the wiring layer 39 is formed by the lower wiring layer 48. The upper wiring layer 50 may form a wiring layer for forming the capacitive elements 22 and 24. As described above, the lead-out wiring layer 39 may be provided below the wiring layer forming the capacitive elements 22 and 24.

  According to the tenth embodiment, at least one of the first wiring 12 a and the third wiring 16 a is connected to the lead-out wiring layer 39 through the intermediate wiring layer 37. Thereby, it is possible to suppress the parasitic capacitance formed between the second wiring 14 a and the fourth wiring 18 a and the lead-out wiring layer 39. In the tenth embodiment, the case where at least one of the first wiring 12a and the third wiring 16a is connected to the lead-out wiring layer 39 through the intermediate wiring layer 37 has been described as an example. For this purpose, at least one of the first wiring 12a, the second wiring 14a, the third wiring 16a, and the fourth wiring 18a can be connected to the lead-out wiring layer 39 through the intermediate wiring layer 37.

  According to the first to tenth embodiments, the planar shape of the first wiring 12a in the first capacitor 22 and the planar shape of the third wiring 16a in the second capacitor 24 are the same. In addition, the planar shape of the third wiring 16 a in the first capacitive element 22 and the planar shape of the fourth wiring 18 a in the second capacitive element 24 are the same. Therefore, a difference in capacitance value due to the arrangement of the capacitive elements can be suppressed.

  A method for manufacturing a semiconductor device including the capacitive elements according to the second to tenth embodiments will be described with reference to FIGS. An element isolation insulating layer 102 is formed in a well of a semiconductor substrate 100 such as silicon. A channel is formed in the semiconductor substrate 100 using an ion implantation method. For example, a polysilicon gate electrode 104 is formed on the channel of the semiconductor substrate 10 via a gate insulating film 103. Sidewalls 105 are formed on both sides of the gate electrode 104, and source and drain regions are formed using an ion implantation method. Silicide is formed on the gate electrode 104 and the source and drain regions. A protective film 106 such as silicon nitride is formed on the entire surface. For example, the insulating film 108 such as a silicon oxide film is formed using a TEOS (Tetra Ethoxy Silane) method. After the insulating film 108 is planarized using a CMP (Chemical Mechanical Polish) method, for example, a TiN film 109 and a W film 110 are formed on the insulating film 108 and planarized using the CMP method, thereby forming a contact.

  For example, an etching stopper film 112a such as a SiCN film is formed. On the etching stopper film 112a, an insulating film 114a, for example, a silicon oxide film is formed. An opening is provided in the insulating film 114a, and a barrier layer 116a such as Ta is formed in the opening by a sputtering method. A wiring layer 118a such as Cu is formed on the barrier layer 116a using a sputtering method and a plating method. Thereafter, planarization is performed using a CMP method to form a barrier layer 116a and a wiring layer 118a in the opening of the insulating film 114a. Similarly, an etching stopper film 112b having a thickness of 30 nm and an insulating film 114b having a thickness of 350 nm are formed. Further, an etching stopper film 112c having a film thickness of 70 nm and an insulating film 114c having a film thickness of 300 nm are formed, and the contact hole 117 is formed up to just above the etching stopper film 112b.

  Referring to FIG. 15, the insulating film 114c and the etching stopper film 112c in the region where the wiring layer is to be formed are anisotropically etched using a CF-based gas. At this time, the etching stopper film 112b at the bottom of the contact hole 117 is also etched. Referring to FIG. 16, for example, a Ta film barrier layer 116c having a thickness of 30 nm is formed by sputtering. For example, a Cu film having a film thickness of 60 nm is formed by sputtering, and for example, Cu having a film thickness of 1000 nm is formed by electrolytic plating. Thereafter, planarization is performed using a CMP method. Thereby, the barrier layer 116c and the wiring layer 118c embedded in the opening formed in the insulating film 114c are formed. A barrier layer 116b and a contact 118b are formed in the insulating film 114b. The capacitive element 20 is formed by the wiring layer 118c.

  Referring to FIG. 17, similarly to FIGS. 15 and 16, an etching stopper film 112d, an insulating film 114d, an etching stopper film 112e, and an insulating film 114e are formed. A barrier layer 116d and a contact 118d are formed in the opening formed in the insulating film 114d, and a barrier layer 116e and a wiring layer 118e are formed in the opening formed in the insulating film 114e.

  Referring to FIG. 18, an etching stopper film 112f, an insulating film 114f, an etching stopper film 112g, and an insulating film 114g are formed. Further, a barrier layer 116f, a contact 118f, a barrier layer 116g, and a wiring layer 118g are formed. An etching stopper layer 112h and an insulating film 114h are formed. In the insulating film 114h, for example, a TiN film barrier layer 116h, for example, a W film contact 118h is formed. For example, a wiring layer 118i of TiN film / Al film / TiN film is formed as a wiring layer connected to the contact 116h. For example, a cover insulating film 114i made of a silicon oxide film is formed. A protective film 120 of silicon nitride film is formed. The protective film 120 and the cover insulating film 114i in the pad portion are removed. As a result, transistors and the like are formed in the circuit portion, and the capacitive element 20 is formed in the MIM capacitor portion.

  Although an example of the manufacturing method of the semiconductor device including the capacitive elements according to the second to tenth embodiments has been described with reference to FIGS. 14 to 18, it goes without saying that the other methods are used to change the second to the tenth embodiments. Such a capacitor element may be formed.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

The following appendices are further disclosed with respect to the embodiments including Examples 1 to 10.
(Supplementary Note 1) A first capacitor element including a first wiring extending in a first direction, and a second wiring provided to face the first wiring with an insulator interposed therebetween, and the first wiring and the electrical A third wiring extending in a second direction perpendicular to the first direction and a fourth wiring electrically connected to the second wiring and opposed to the third wiring through an insulator. A first capacitor, a second capacitor, and the first wiring, the second wiring, the third wiring, and the fourth wiring are provided in the same wiring layer, and the first wiring and the second wiring The semiconductor device according to claim 1, wherein a length facing the wiring is equal to a length facing the third wiring and the fourth wiring.
(Supplementary Note 2) The first wiring and the second wiring are respectively divided into a plurality of first wirings and a plurality of second wirings, and the plurality of divided first wirings and the plurality of second wirings are provided alternately. The third wiring and the fourth wiring are respectively divided into a plurality of third wirings and a plurality of fourth wirings, and the plurality of divided third wirings and the plurality of fourth wirings are provided alternately. The semiconductor device according to appendix 1, wherein:
(Supplementary note 3) The semiconductor according to supplementary note 2, wherein one of the wiring connecting the plurality of first wirings and the wiring connecting the plurality of second wirings is used as one of the third wiring and the fourth wiring. apparatus.
(Supplementary Note 4) The planar shape of the first wiring in the first capacitive element is the same as the planar shape of the third wiring in the second capacitive element, and the planar shape of the second wiring in the first capacitive element. 4. The semiconductor device according to claim 1, wherein a planar shape of the fourth wiring in the second capacitor element is the same. 5.
(Supplementary Note 5) The first wiring, the second wiring, the third wiring, and the fourth wiring are formed in a plurality of stacked wiring layers, and the first wiring formed in the plurality of wiring layers, Note that the second wiring, the third wiring, and the fourth wiring are connected to each other by a contact that vertically penetrates an insulating layer provided between the plurality of stacked wiring layers. 5. The semiconductor device according to claim 1.
(Appendix 6) The lengths of the plurality of divided first wires and the plurality of divided second wires facing each other are the same, and the plurality of divided third wires and the plurality of divided plurality of wires are the same. The semiconductor device according to appendix 2, wherein the lengths facing the fourth wiring are the same.
(Supplementary note 7) At least one of the first wiring, the second wiring, the third wiring, and the fourth wiring is connected to a lead-out wiring layer through an intermediate wiring layer. 7. The semiconductor device according to any one of items 1 to 6.
(Supplementary Note 8) The first capacitive element is disposed in the second quadrant and the fourth quadrant, the second capacitive element is disposed in the first quadrant and the third quadrant, and the plurality of the second quadrant and the fourth quadrant A wiring connecting between the plurality of third wirings in the first quadrant and the third quadrant using a wiring connecting the first wirings as one of the third wirings in the first quadrant and the third quadrant, respectively. 3 is used as one of the first wirings in the second quadrant and the fourth quadrant, respectively.
(Supplementary Note 9) An outer peripheral wiring is formed by the wiring connecting the plurality of second wirings, the wiring connecting the plurality of fourth wirings, the second wiring, and the fourth wiring, and the outer peripheral wiring is the first wiring The semiconductor device according to appendix 8, wherein the semiconductor device surrounds the third wiring.

12a First wiring 14a Second wiring 16a Third wiring 18a Fourth wiring 22 First capacitance element 24 Second capacitance element 37 Intermediate wiring layer 39 Wiring layer 40, 42, 44 Insulating layer

Claims (5)

A plurality of first wirings extending in a first direction, and a plurality of second wiring provided opposed alternately with the plurality of first wiring through the plurality of first wiring and insulators, the plurality first A plurality of first capacitance elements each including a third wiring connected to each of the one wiring and extending in a second direction perpendicular to the first direction ;
A plurality of fourth wirings said a plurality of first wiring electrically connected is provided extending in the second direction, the second wiring electrically connected to said plurality of fourth wiring and insulators opposing a plurality of fifth wirings provided, a plurality of second capacitor comprising a sixth wiring, a extending in the first direction to connect each of the plurality of fourth wirings and the third wirings via Elements,
Comprising
When the origin is a point where the third wiring and the sixth wiring are connected, the first capacitive element is disposed in the second quadrant and the fourth quadrant, and the second capacitance is disposed in the first quadrant and the third quadrant. The elements are arranged,
A plurality of seventh wirings connected to each of the second wirings in the second quadrant and the fourth quadrant and extending in the second direction; and the fifth wirings in the first quadrant and the third quadrant A plurality of eighth wires connected to each other and extending in the first direction, the second wires in the second quadrant and the fourth quadrant located farthest from the origin, and the farthest away from the origin Including the first quadrant and the fifth quadrant in the third quadrant, and including outer peripheral wirings surrounding the plurality of first wirings and the plurality of fourth wirings,
The first wiring, the second wiring, the third wiring , the fourth wiring , the fifth wiring, the sixth wiring, and the outer peripheral wiring are provided in a first wiring layer, and the first wiring and the second wiring A semiconductor device, wherein a length facing a wiring is equal to a length facing the fourth wiring and the fifth wiring. The third had use a wire as one of the plurality of fourth wirings, the semiconductor device according to claim 1, characterized by using the sixth wiring as one of the plurality of first wirings. The planar shape of the plurality of first wirings in the first capacitive element is the same as the planar shape of the plurality of fourth wirings in the second capacitive element, and the plurality of second wirings in the first capacitive element are the same. 3. The semiconductor device according to claim 1, wherein the planar shape is the same as the planar shape of the plurality of fifth wirings in the second capacitor element. The first wiring, the second wiring, the third wiring , the fourth wiring , the fifth wiring, and the sixth wiring are formed in a plurality of stacked wiring layers, and are formed in the plurality of wiring layers. In addition, the first wiring, the second wiring, the third wiring , the fourth wiring , the fifth wiring, and the sixth wiring are formed by vertically moving an insulating layer provided between the plurality of stacked wiring layers. the semiconductor device as described in any one of claims 1 to 3, characterized in that it is connected by a contact penetrating. A second wiring layer provided above or below the first wiring layer via a first insulating layer;
A contact that is provided on the opposite side of the second wiring layer from the first wiring layer via a second insulating layer, and that penetrates the first insulating layer to the plurality of first wirings and the plurality of fourth wirings And a third wiring layer that is connected to the second wiring layer and a contract that penetrates the second insulating layer and extends outward from the outer peripheral wiring;
The semiconductor device according to claim 1, further comprising:

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