JP5614242B2 - Pixel circuit, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a pixel circuit, an electro-optical device, an electronic apparatus, and the like.

  As a conventional technique of a pixel circuit for driving a pixel of an electro-optical device such as a liquid crystal device (LCD), techniques disclosed in Patent Documents 1 and 2 are known.

  In the prior art of Patent Document 1, a plurality of pixel circuits are provided corresponding to a plurality of pixels, and each pixel circuit is provided with a static RAM (static random access memory) type latch circuit. Then, drive data signals based on the data signal (image data) held in the static RAM type latch circuit are transferred from all the pixel circuits to all the pixels at a predetermined timing.

  In the prior art of Patent Document 2, each pixel circuit is provided with a capacitance hold type latch circuit composed of a single-channel N-type transistor and a capacitor. In this capacitance hold type latch circuit, a data signal is latched by holding electric charge in the capacitor.

JP 2004-4216 A JP 2005-352457 A

  However, it has been found that in such a pixel circuit, a voltage exceeding the withstand voltage may be applied to the transistors constituting the output circuit that outputs the drive data signal. If a voltage exceeding such a withstand voltage is applied to the drain of the transistor of the output circuit, the characteristics of the transistor may be deteriorated. However, the prior arts of Patent Documents 1 and 2 have not proposed a circuit configuration or layout method considering such deterioration of transistor characteristics.

  According to some embodiments of the present invention, it is possible to provide a pixel circuit, an electro-optical device, an electronic device, and the like that can drive a pixel while suppressing deterioration of a transistor of an output circuit.

  One embodiment of the present invention is a pixel circuit that drives a pixel of an electro-optical device, and includes a latch unit that latches a data signal and a buffer circuit, and a drive data signal based on the latch data signal from the latch unit. An output circuit for buffering and outputting to the pixel, the output circuit including a resistor provided between an output node of the buffer circuit and a pixel circuit output node, a high-potential-side power supply node, and the pixel circuit output node A first diode having a forward direction from the pixel circuit output node toward the high-potential side power supply node, and between the pixel circuit output node and the low-potential side power supply node. , And a second diode having a forward direction from the low-potential-side power supply node toward the pixel circuit output node.

  In one embodiment of the present invention, the pixel circuit includes a latch portion and an output circuit, and the output circuit includes a resistor and first and second diodes. The resistor is provided between the output node of the buffer circuit included in the output circuit and the pixel circuit output node. The first diode is provided between the high-potential side power supply node and the pixel circuit output node, and the second diode is provided between the pixel circuit output node and the low-potential side power supply node. If the resistor having the connection structure and the first and second diodes are provided, the charge from the pixel is efficiently transferred to the high potential side power source side and the low potential side power source side via the first and second diodes. It becomes possible to escape, and deterioration of the transistors of the output circuit can be suppressed.

  In one aspect of the present invention, the buffer circuit of the output circuit includes a P-type transistor and an N-type transistor connected in series, and the resistor is a P-type impurity region formed by extending a drain of the P-type transistor. And an N-type impurity region formed by extending the drain of the N-type transistor.

  In this way, a resistor can be formed at the output node of the buffer circuit by extending the drain of the P-type transistor and the N-type transistor of the buffer circuit. Therefore, it is possible to form a resistor without increasing the layout area so much.

  Also, in one aspect of the present invention, the first diode has an N-type impurity region for potential stabilization that has the P-type impurity region as an anode and is opposed to the P-type impurity region and connected to the high-potential side power supply node. And a diode having an N-type well in which the N-type impurity region for potential stabilization is formed as a cathode, and the second diode has the N-type impurity region as a cathode and is opposed to the N-type impurity region and has the low A diode having a P-type impurity region for potential stabilization connected to a potential-side power supply node and a P-type well in which the P-type impurity region for potential stabilization is formed as an anode may be used.

  In this way, the first diode is formed by the P-type impurity region in which the drain of the P-type transistor of the buffer circuit is extended and the N-type impurity region for stabilizing the potential, etc., and the N-type transistor of the buffer circuit is formed. The second diode can be formed by the N-type impurity region having the drain extended and the P-type impurity region for stabilizing the potential.

  In one embodiment of the present invention, the P-type impurity region includes a first P-type impurity region formed to extend along the first extending direction and an end portion of the first P-type impurity region. A second P-type impurity region extending along a second extending direction that intersects the first extending direction, and the N-type impurity region extends in the first extending direction. A first N-type impurity region extending along the first extension region, and a third extension direction extending from the end of the first N-type impurity region and intersecting with the first extension direction. And the potential stabilizing N-type impurity region is on the first extending direction side of the second P-type impurity region, and the second P-type impurity region is formed on the second P-type impurity region. The potential stabilizing P-type impurity region is disposed at a location facing the type impurity region, and the potential stabilization P-type impurity region is located on the first extending direction side of the second N-type impurity region. What may be disposed in a location facing the second N-type impurity regions.

  According to such a layout arrangement, the length of the extended P-type impurity region and N-type impurity region can be increased without significantly increasing the width of the pixel circuit. The resistance value of the formed resistor can be increased. The first diode is formed by the second P-type impurity region and the N-type impurity region for stabilizing the potential formed along the second extending direction while facing each other, and the third diode while facing each other. The second diode can be formed by the second N-type impurity region and the potential stabilizing P-type impurity region formed along the extending direction. Thereby, the area of the PN junction surface of the first and second diodes can be further increased. Therefore, it becomes possible to make it easy for the charge from the pixel to flow to the first and second diodes, and to suppress deterioration of the transistor of the buffer circuit of the output circuit.

  In one embodiment of the present invention, the output circuit includes a first P-type transistor that is provided between a signal node to which a given signal is input or output and the output node of the output circuit, and is connected in parallel. And a transfer gate composed of a first N-type transistor and a clocked inverter circuit as the buffer circuit, wherein the clocked inverter circuit includes a second P-type transistor and a third P-type connected in series. A transistor, a third N-type transistor, and a second N-type transistor, wherein the P-type transistor is the third P-type transistor of the clocked inverter circuit, and the N-type transistor is the clocked transistor. The third N-type transistor of the inverter circuit may be used.

  According to this configuration, the resistor and the first and second diodes efficiently release the charge from the pixel to the high potential side power supply side or the low potential side power supply side, so that the clocked inverter circuit of the output circuit It is possible to suppress the deterioration of the third P-type transistor and the third N-type transistor.

  In one embodiment of the present invention, the second P-type transistor and the third P-type transistor constituting the clocked inverter circuit, and the first P-type transistor constituting the transfer gate are the first The second N-type transistor and the third N-type transistor that are arranged along the direction and constitute the clocked inverter circuit, and the first N-type transistor that constitutes the transfer gate is the first N-type transistor. You may arrange | position along a direction.

  With such a layout arrangement, the clocked inverter circuit and the transistors constituting the transfer gate can be arranged efficiently and compactly. As a result, the width of the pixel circuit in the second direction can be reduced, and the layout area of the pixel circuit can be reduced.

  In one embodiment of the present invention, the drain of the second P-type transistor and the source of the third P-type transistor are formed by a common impurity region, and the drain of the third P-type transistor and the first P-type transistor The source of the P-type transistor is formed by a common impurity region, the drain of the second N-type transistor and the source of the third N-type transistor are formed by a common impurity region, and the source of the third N-type transistor The drain and the source of the first N-type transistor may be formed by a common impurity region.

  If the layout arrangement sharing the drain and source of adjacent transistors is used in this way, for example, the width of the pixel circuit in the first direction can be reduced, and the layout area of the pixel circuit can be reduced.

  In one embodiment of the present invention, during a test, a test signal is input as the given signal to the signal node of the transfer gate, or an inspection result signal of the pixel from the signal node of the transfer gate. May be output as the given signal.

  In this way, for example, at the time of testing, a test signal is input as a given signal to the signal node of the transfer gate, or a pixel inspection result signal is given as a given signal from the signal node of the transfer gate. It becomes possible to output.

  In one aspect of the present invention, during normal operation, the first P-type transistor and the first N-type transistor of the transfer gate are turned off, and the second P-type transistor of the clocked inverter circuit and The second N-type transistor is turned on, and during the test, the first P-type transistor and the first N-type transistor of the transfer gate are turned on, and the second P-type of the clocked inverter circuit is turned on. The type transistor and the second N-type transistor may be turned off.

  In this way, at the time of the test, the clocked inverter circuit is set to the high impedance output state, and the test signal is input via the transfer gate, or the pixel inspection result signal is output via the transfer gate. Is possible.

  In one embodiment of the present invention, the latch unit latches a first latch circuit that latches and stores a data signal for driving the pixel, and latches the data signal transferred from the first latch circuit. And a second latch circuit for storing the data.

  In this way, after the data signal is taken into the first latch circuit, it can be transferred to the second latch circuit, and a drive data signal based on the latch data signal of the second latch circuit can be supplied to the pixel. It becomes like this.

  In one embodiment of the present invention, a selector that is controlled based on the latch data signal from the second latch circuit and selects and outputs either the on-drive waveform signal or the off-drive waveform signal may be included. Good.

  In this way, either the on-drive waveform signal or the off-drive waveform signal can be selected based on the latch data signal from the second latch circuit and supplied to the pixel as the drive data signal. become.

  According to an aspect of the present invention, when one frame is divided into a plurality of subframes, and each scanning line of the plurality of scanning lines of the electro-optical device is sequentially selected in each subframe of the plurality of subframes. The first latch circuit latches the data signal based on a scan signal that becomes active when a scan line corresponding to a pixel circuit of the plurality of scan lines is selected, and the second latch circuit The latch circuit may latch the data signal transferred from the first latch circuit based on a subframe synchronization signal that becomes active in synchronization with each subframe.

  In this way, the electro-optical device can be driven by the subframe driving method.

  Another aspect of the invention relates to an electro-optical device including a plurality of pixels and a plurality of pixel circuits each of which is a pixel circuit described above.

  Another aspect of the invention relates to an electronic apparatus including the electro-optical device described above.

2 is a configuration example of a pixel circuit of the present embodiment. 2 is a detailed configuration example of a pixel circuit of the present embodiment. 4 is a more detailed configuration example of a pixel circuit of the present embodiment. Explanatory drawing about deterioration of the characteristic of the transistor of the output circuit of a pixel circuit. 6 is a layout arrangement example of a pixel circuit. FIGS. 6A and 6B are detailed explanatory views of the layout arrangement of the resistors and the first and second diodes. FIG. 7A and FIG. 7B are also detailed explanatory views of the layout arrangement of the resistors and the first and second diodes. 4 is a layout wiring example of a first metal layer of a pixel circuit. 9 is a layout wiring example of a second metal layer of a pixel circuit. 9 is a layout wiring example of a third metal layer of a pixel circuit. Explanatory drawing about the sub-frame drive of equal intervals. 2 is a configuration example of a circuit device of an electro-optical device. 2 is a configuration example of an electro-optical device. The signal waveform example for demonstrating operation | movement of this embodiment. Configuration example of electronic equipment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Pixel Circuit FIG. 1 shows a configuration example of the pixel circuit of this embodiment. The pixel circuit of the present embodiment is a circuit that drives a pixel of the electro-optical device, and includes a latch unit 10 and an output circuit 30.

  Each pixel of an electro-optical device such as a liquid crystal device or an organic EL device includes, for example, an electro-optical element CEL such as a liquid crystal element and a pixel electrode EPX. The pixel electrode EPX is opposed to a counter electrode ECM (common electrode) that is a common electrode for a plurality of pixels. An electro-optical element such as a liquid crystal element is provided between the pixel electrode EPX and the counter electrode ECM, for example, and the pixel circuit outputs a drive data signal to the pixel electrode EPX to drive the pixel.

  The latch unit 10 includes a first latch circuit 11 and a second latch circuit 12. The first latch circuit 11 latches and stores a data signal (image data) for driving the pixel. The second latch circuit 12 is connected to the first latch circuit 11 and latches and stores the data signal transferred from the first latch circuit 11 (image data latched by the first latch circuit 11). .

  The output circuit 30 outputs a drive data signal for driving the pixel to the pixel. Specifically, a drive data signal based on the latch data signal from the second latch circuit 12 is output to the pixel (pixel electrode).

  FIG. 2 shows a detailed configuration example of the pixel circuit of this embodiment. In FIG. 2, in addition to the latch unit 10 and the output circuit 30 of FIG. A detailed configuration example of the output circuit 30 is also shown. Note that the pixel circuit of the present embodiment is not limited to the configuration of FIG. 2, and various modifications such as omitting some of the components (for example, a selector) or adding other components are possible.

  The output circuit 30 includes a resistor RP, a first diode DI1, and a second diode DI2. Further, it includes a transfer gate TGQ and a clocked inverter circuit CIVQ (buffer circuit in a broad sense).

  The resistor RP is provided between the output node NCQ of the clocked inverter circuit CIVQ that is a buffer circuit and the pixel circuit output node NQ. The resistor RP can be formed by, for example, an impurity region (diffusion region) as will be described later. Specifically, when the buffer circuit of the output circuit 30 includes a P-type transistor and an N-type transistor connected in series, the resistor RP has a P-type impurity region formed by extending the drain of the P-type transistor, The N-type transistor can be formed by an N-type impurity region extending from the drain. In this case, the P-type transistor of the buffer circuit of the output circuit 30 is, for example, the P-type transistor TPQ3 of the clocked inverter circuit CIVQ in FIG. 2, and the N-type transistor is the N-type transistor TNQ3 of the clocked inverter circuit CIVQ. It is also possible to form the resistor RP by using a region other than the impurity region (for example, a polysilicon layer).

  The first diode DI1 is provided between a node of VDD which is a high potential side power supply and the pixel circuit output node NQ. The first diode DI1 is a diode whose forward direction is from the node NQ toward the VDD node. More specifically, the diode DI1 has, for example, a P-type impurity region (P-type diffusion region) as an anode, a potential stabilization N-type impurity region (N-type diffusion region, N-type stopper region), and a potential stabilization N-type. A diode having an N-type well (N-type substrate) in which an impurity region is formed as a cathode.

  The second diode DI2 is provided between the node NQ and the VSS node that is the low potential side power supply. The second diode DI2 is a diode whose forward direction is from the VSS node to the node NQ. More specifically, the diode DI2 has, for example, an N-type impurity region (N-type diffusion region) as a cathode, a potential stabilization P-type impurity region (P-type diffusion region, P-type stopper region), and a potential stabilization P-type. This is a diode having a P-type well (P-type substrate) in which an impurity region is formed as an anode.

  By providing such a resistor RP and diodes DI1 and DI2, it is possible to efficiently release charges from the pixel electrode to the power supply VDD side or VSS side as will be described later. As a result, the deterioration of the characteristics of the transistors TPQ3, TNQ3, etc. of the output circuit 30 can be suppressed.

  The transfer gate TGQ is provided between a signal node to which a given signal TIN is input (or a signal node to which a given signal TQ is output) and an output node NCQ of the clocked inverter circuit CIVQ (buffer circuit). It is done. The transfer gate TGQ includes a first P-type transistor TPQ1 and a first N-type transistor TNQ1 connected in parallel. These transistors TPQ1 and TNQ1 have their sources connected in common and their drains connected in common. A negative logic test signal XST is input to the gate of the P-type transistor TPQ1, and a positive logic test signal ST is input to the gate of the N-type transistor TNQ1. “X” added to the signal name means a negative logic signal.

  The clocked inverter circuit CIVQ includes a second P-type transistor TPQ2, a third P-type transistor TPQ3, a third N-type transistor TNQ3, and a second N-type transistor TNQ2 connected in series. Then, drive data signal SDR is output to output node NCQ. For example, the P-type transistors TPQ2 and TPQ3 are provided between the VDD node and the output node NCQ, and the N-type transistors TNQ3 and TNQ2 are provided between the output node NCQ and the VSS node. The output signal SLQ of the selector 20 is input to the gates of the P-type transistor TPQ3 and the N-type transistor TNQ3. A negative logic high impedance control signal XSHZ and a positive logic high impedance control signal SHZ are input to the gates of the P-type transistor TPQ2 and the N-type transistor TNQ2, respectively.

  Note that the clocked inverter circuit is not limited to the configuration shown in FIG. 2, and various modifications such as making the connection relation and number of transistors different from those in FIG. 3 are possible. The clocked inverter circuit CIVQ may be an inverter circuit having a normal configuration. In this case, for example, a P-type impurity region in which the drain of the P-type transistor constituting the normal configuration inverter circuit is formed to extend, and an N-type impurity in which the drain of the N-type transistor of the normal configuration inverter circuit is formed to extend. A resistor RP may be formed depending on the region.

  The selector 20 is controlled based on the latch data signal LTQ from the latch unit 10. Then, either the on-drive waveform signal SON or the off-drive waveform signal SOFF is selected and output. That is, one of the waveform signals SON and SOFF is selected based on the latch data signal LTQ and is output to the output circuit 30 as the signal SLQ. The output circuit 30 receives this signal SLQ and outputs a drive data signal SDR based on the latch data signal LTQ from the latch unit 10 to the pixel (pixel electrode).

  FIG. 3 shows a more detailed configuration example of the pixel circuit of this embodiment. FIG. 3 shows a detailed configuration example of the first and second latch circuits 11 and 12 and the selector 20 of the latch unit 10. Note that the configurations of the latch unit 10 and the selector 20 are not limited to the configurations shown in FIG. 3, and various modifications such as omitting some of the components or adding other components are possible.

  The first latch circuit 11 includes a first transfer gate TG1, a feedback first clocked inverter circuit CIV1, and a first inverter circuit IV1.

  The transfer gate TG1 is provided between the input node ND of the data signal SDA and the first node N1. The transfer gate TG1 includes a first P-type transistor TP1 and a first N-type transistor TN1 connected in parallel. For example, the P-type transistor TP1 and the N-type transistor TN1 have their sources connected in common and their drains connected in common. A negative logic scanning signal XSG (negative logic gate signal) is input to the gate of the P-type transistor TP1, and a positive logic scanning signal SG (positive logic gate signal) is input to the gate of the N-type transistor TN1. Entered.

  The clocked inverter circuit CIV1 uses the second node N2 as an input node and the first node N1 as an output node. The clocked inverter circuit CIV1 includes a second P-type transistor TP2, a third P-type transistor TP3, a third N-type transistor TN3, and a second N-type transistor TN2 connected in series. A second node N2 is connected to the gates of the transistors TP3 and TN3, and scanning signals SG and XSG are input to the gates of the transistors TP2 and TN2, respectively.

  The inverter circuit IV1 uses the first node N1 as an input node and the second node N2 as an output node. The inverter circuit IV1 includes a fourth P-type transistor TP4 and a fourth N-type transistor TN4 connected in series. Note that the inverter circuit IV1 may have a configuration of a clocked inverter circuit.

  The second latch circuit 12 includes a second transfer gate TG2, a feedback second clocked inverter circuit CIV2, and a second inverter circuit IV2.

  The transfer gate TG2 is provided between the second node N2 and the third node N3. The transfer gate TG2 includes a fifth P-type transistor TP5 and a fifth N-type transistor TN5 connected in parallel. A negative logic subframe synchronization signal XSF is input to the gate of the P-type transistor TP5, and a positive logic subframe synchronization signal SF is input to the gate of the N-type transistor TN5. The details of the scanning signals SG and XSG and the subframe synchronization signals SF and XSF will be described later.

  The clocked inverter circuit CIV2 uses the fourth node N4 as an input node and the third node N3 as an output node. The clocked inverter circuit CIV2 includes a sixth P-type transistor TP6, a seventh P-type transistor TP7, a seventh N-type transistor TN7, and an eighth N-type transistor TN8 connected in series. A fourth node N4 is connected to the gates of the transistors TP7 and TN7, and subframe synchronization signals SF and XSF are input to the gates of the transistors TP6 and TN6, respectively.

  The inverter circuit IV2 uses the third node N3 as an input node and the fourth node N4 as an output node. The inverter circuit IV2 includes an eighth P-type transistor TP8 and an eighth N-type transistor TN8 connected in series. Note that the inverter circuit IV2 may have a configuration of a clocked inverter circuit.

  The selector 20 includes a transfer gate TGS1 and a transfer gate TGS2 for the selector.

  The transfer gate TGS1 is provided between the input node of the ON drive waveform signal SON (ON drive voltage) and the output node NS of the selector 20, and is ON / OFF controlled based on the latch data signals LTQ and XLTQ. Specifically, the transfer gate TGS1 is turned on when the latch data signals LTQ and XLTQ are H level and L level, respectively, and is turned off when the LTQ and XLTQ are L level and H level, respectively.

  The transfer gate TGS2 is provided between the input node of the off-drive waveform signal SOFF and the output node NS of the selector 20, and is on / off controlled based on the latch data signals LTQ and XLTQ. Specifically, the transfer gate TGS2 is turned on when the latch data signals LTQ and XLTQ are L level and H level, respectively, and is turned off when the LTQ and XLTQ are H level and L level, respectively. Thus, the transfer gates TGS1 and TGS2 are turned on or off exclusively.

  Next, the operation of the pixel circuit of this embodiment shown in FIG.

  First, when the scanning signal SG (first latch signal in a broad sense) becomes H level (XSG is L level), the transfer gate TG1 is turned on, and the data signal SDA is latched by the first latch circuit 11. For example, when the data signal SDA is at the H level (logic “1”), the nodes N1 and N2 are set to the H level and the L level, respectively, and the data signal SDA is at the L level (logic “0”). In this case, the nodes N1 and N2 are set to the L level and the H level, respectively. At this time, since the transistors TP2 and TN2 of the clocked inverter circuit CIV1 are turned off by the signals SG and XSG, CIV1 is set to a high impedance output state. Therefore, it is possible to prevent a situation where the data signal SDA via the transfer gate TG1 and the output signal of the clocked inverter circuit CIV1 collide and the node N1 and the like are set to an unstable intermediate potential level.

  Next, when the scanning signal SG becomes L level (XSG is H level), the transfer gate TG1 is turned off, the transistors TP2 and TN2 of the clocked inverter circuit CIV1 are turned on, and CIV1 is a normal feedback inverter. Functions as a circuit. As a result, the voltage level of the data signal SDA is statically held in the first latch circuit 11. For example, when the data signal SDA is at the H level, the voltage levels of the H level and the L level are statically held at the nodes N1 and N2, respectively. When the data signal SDA is at the L level, the nodes N1 and N2, The voltage levels of L level and H level are statically held in N2, respectively.

  Next, when the subframe synchronization signal SF (second latch signal in a broad sense) becomes H level (XSF is L level), the transfer gate TG2 is turned on, and the data held in the first latch circuit 11 The signal is transferred to and held in the second latch circuit 12. At this time, the transistors TP6 and TN6 of the clocked inverter circuit CIV2 are turned off by the signals SF and XSF, so that the CIV2 is set to a high impedance output state. Therefore, it is possible to prevent a situation in which the data signal via the transfer gate TG2 and the output signal of the clocked inverter circuit CIV2 collide and the node N3 and the like are set to an unstable intermediate potential level.

  Next, when the subframe synchronization signal SF becomes L level (XSF is H level), the transfer gate TG2 is turned off, the transistors TP6 and TN6 of the clocked inverter circuit CIV2 are turned on, and CIV2 is used for normal feedback. Functions as an inverter circuit. As a result, the voltage level of the data signal transferred from the first latch circuit 11 is statically held in the second latch circuit 12. For example, when the data signal SDA input to the first latch circuit 11 is at the H level, the voltage levels of the H level and the L level are statically held at the nodes N4 and N3, respectively. As a result, the latch data signals LTQ and XLTQ become H level and L level, respectively. When the data signal SDA input to the first latch circuit 11 is at the L level, the voltage levels of the L level and the H level are statically held at the nodes N4 and N3, respectively. As a result, the latch data signals LTQ and XLTQ become L level and H level, respectively.

  The transfer gates TGS1 and TGS2 of the selector 20 are controlled by the latch data signals LTQ and XLTQ from the second latch circuit 12. When the latch data signal LTQ is at the H level (the logical level of the image data is “1”), the transfer gate TGS1 is turned on and the TGS2 is turned off. Accordingly, the on-drive waveform signal SON is selected, and the signal SLQ is buffered by the output circuit 30 and output to the pixel as the drive data signal SDR. On the other hand, when the data signal LTQ is at the L level (the logical level of the image data is “0”), the transfer gate TGS1 is turned off and the TGS2 is turned on. Therefore, the off-drive waveform signal SOFF is selected, and the signal SLQ is buffered by the output circuit 30 and output to the pixel as the drive data signal SDR.

  Further, during normal operation of the electro-optical device, the test signal ST becomes L level (XST is H level), and the high impedance control signal SHZ becomes H level (XHZ is L level). Accordingly, the P-type transistor TPQ1 and the N-type transistor TNQ1 of the transfer gate TGQ are turned off, and the P-type transistor TPQ2 and the N-type transistor TNQ2 of the clocked inverter circuit CIVQ are turned on. As a result, the clocked inverter circuit CIVQ operates as an inverter circuit having a normal configuration, and buffers the signal SLQ from the selector 20 and outputs it as the drive signal SDR.

  On the other hand, at the time of testing (inspection), the test signal ST becomes H level (XST is L level), and the high impedance control signal SHZ becomes L level (XHZ is H level). Accordingly, the P-type transistor TPQ1 and the N-type transistor TNQ1 of the transfer gate TGQ are turned on, and the P-type transistor TPQ2 and the N-type transistor TNQ2 of the clocked inverter circuit CIVQ are turned off. As a result, the clocked inverter circuit CIVQ is set to the high impedance output state. Therefore, at the time of testing (inspection), a test signal can be input as a given signal to the signal node of the transfer gate TGQ. Alternatively, the pixel inspection result signal can be output as a given signal from the signal node of the transfer gate TGQ. This enables an efficient test (inspection) of the electro-optical device.

  That is, the transfer gate TGQ is not a single-channel N-type transistor switch but a complementary switch composed of the P-type transistor TPQ1 and the N-type transistor TNQ1. Accordingly, a voltage drop corresponding to the threshold voltage does not occur, and a test signal can be input at a high speed or a test result signal can be output at a high speed via the transfer gate TGQ. Therefore, the test time can be shortened, and the cost of the product can be reduced.

2. Suppression of Transistor Degradation When performing polarity inversion driving in an electro-optical device, a voltage exceeding the withstand voltage may be applied to the transistor of the pixel circuit. Specifically, a voltage exceeding the withstand voltage is applied to the P-type transistors TPQ3 and TNQ3 of the clocked inverter circuit CIVQ in FIG. 3, and the characteristics of these transistors may be deteriorated.

  Therefore, in this embodiment, the resistor RP and the diodes DI1 and DI2 are provided in the output circuit 30 to suppress the deterioration of the transistor due to the application of the voltage exceeding the withstand voltage.

  First, generation of a voltage exceeding the withstand voltage will be described with reference to FIG. In the following, a case where the voltage for driving the pixel electrode and the counter electrode is 0V to 5V will be described as an example.

  As indicated by G1 in FIG. 4, it is assumed that the driving voltage of the counter electrode is 0V and the driving voltage of the pixel electrode is 5V. At this time, as indicated by G2, the liquid crystal capacitance (parasitic capacitance of the liquid crystal layer) is charged with a charge of 5V.

  As shown in G3, it is assumed that the driving voltage of the counter electrode changes to 5V and the driving voltage of the pixel electrode changes to 0V at the same time when the polarity is inverted. At this time, as described above, since the liquid crystal capacitor is charged with a charge of 5V, the voltage of the pixel electrode rises to about 10V as indicated by G4. This voltage pulse is applied to the drains of the transistors TPQ3 and TNQ3 constituting the clocked inverter circuit CIVQ (buffer circuit in a broad sense) that drives the pixel electrode. Then, the electric charge of this voltage pulse goes out to the power supply (VDD, VSS) side through the transistor or the like of TPQ3, TNQ3 which is turned on. Or, it goes out to the power supply side through a parasitic diode of the drain.

  The current due to the voltage pulse is small when viewed from a single pixel because the capacitance value of the liquid crystal capacitance is as small as several fF. However, since polarity inversion occurs simultaneously on the entire panel surface, there is a possibility that it becomes a latch-up trigger current. In order to reduce the area of the pixel circuit, it is desirable to use a normal 5V withstand voltage transistor for the pixel circuit. When a transistor with a withstand voltage of 5 V is used, a voltage higher than the withstand voltage is applied to the drains of the transistors TPQ3 and TNQ3 by the above-described voltage pulse, which may affect the deterioration of the transistors TPQ3 and TNQ3.

  As described above, when the driving voltages of the counter electrode and the pixel electrode are reversed at the same time, there is a problem that a voltage exceeding the withstand voltage is applied to the transistor of the pixel circuit.

  Therefore, in the present embodiment, as shown in FIG. 3 and the like, a resistor RP and diodes DI1 and DI2 are provided on the output side of the output circuit 30. With such a configuration, even when a voltage exceeding the withstand voltage of the transistor is generated, the charge from the pixel electrode can be efficiently released to the power supply VDD side or the VSS side. That is, by providing the resistor RP, the charge from the pixel electrode flows to the diodes DI1 and DI2 side from the transistors TPQ3 and TNQ3, and flows to the power supply VDD and VSS side via DI1 and DI2. Therefore, it is possible to suppress the deterioration of the characteristics of the transistors TPQ3, TNQ3, etc. of the output circuit 30, and the reliability and the like can be improved.

3. Layout Method Next, a layout method of the pixel circuit of the present embodiment will be described. The layout method of the pixel circuit of the present embodiment is not limited to the method described below, and various modifications can be made.

  FIG. 5 shows a layout arrangement example of the pixel circuit of the present embodiment. FIG. 5 shows an impurity layer (ACT) that forms a source, a drain, and the like of a transistor, and a polysilicon layer (POLY) that forms a gate. Further, the vertical direction toward the paper surface is the first direction D1, and the horizontal direction is the second direction D2. In FIG. 5, the upper region is a P-type transistor region formed on the N-type well, and the lower region is an N-type transistor region formed on the P-type well. .

  The resistor RP in FIG. 3 includes a P-type impurity region in which the drain of the P-type transistor TPQ3 (source of TPQ1) is extended as shown by C1 in FIG. 5, and a drain (TNQ1) of the N-type transistor TNQ3 as shown in C2. And an N-type impurity region extending from the source. For example, in C1, the drains of the P-type transistor TPQ3 and the N-type transistor TNQ3 extend along a second direction D2 orthogonal to the first direction D1, and the extension RP (diffuse resistance) ) Is realized.

  The diode DI1 includes a diode having a P-type impurity region indicated by C1 as an anode, an N-type impurity region for potential stabilization indicated by C3, and an N-type well in which the N-type impurity region for potential stabilization is formed as a cathode. Become. Here, the N-type impurity region for potential stabilization indicated by C3 is opposed to the extended P-type impurity region indicated by C1, and is connected to the VDD node.

  The diode DI2 is a diode having an N-type impurity region indicated by C2 as a cathode, a potential stabilization P-type impurity region indicated by C4, and a P-type well in which the potential stabilization P-type impurity region is formed as an anode. Become. Here, the P-type impurity region for potential stabilization indicated by C4 is opposed to the extended N-type impurity region indicated by C2, and is connected to the VSS node.

  6A, FIG. 6B, FIG. 7A, and FIG. 7B are diagrams for explaining details of the layout arrangement of the resistor RP and the diodes DI1 and DI2. 6B is a cross-sectional view taken along the line AA in FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line BB in FIG. 7A.

  For example, as shown in FIG. 6A, the P-type impurity region formed by extending the drain of the P-type transistor TPQ3 has a first P-type impurity region PR1 and a second P-type impurity region PR2. The first P-type impurity region PR1 is a region formed by extending the drain of the P-type transistor TPQ3 along the first extending direction DE1. On the other hand, the second P-type impurity region PR2 is a region formed to extend from the end (corner position) of the first P-type impurity region PR1 along the second extending direction DE2. That is, the first and second P-type impurity regions PR1 and PR2 are formed by extending the drain of the P-type transistor TPQ3 in an L shape. The second extending direction DE2 is a direction intersecting the first extending direction DE1, and is a direction orthogonal to DE1 in FIG.

  The potential stabilizing N-type impurity region NRS is laid out at a location on the first extending direction DE1 side of the second P-type impurity region PR2 and facing the PR2. That is, the second P-type impurity region PR2 and the potential stabilizing N-type impurity region NRS are formed along the second extending direction DE2 while facing each other. As shown in FIG. 6B, the diode DI1 includes a diode having a P-type impurity region PR2 or the like as an anode and an N-type well NWL in which potential stabilization N-type impurity regions NRS and NRS are formed as a cathode. Become.

  Further, as shown in FIG. 7A, the N-type impurity region in which the drain of the N-type transistor TNQ3 is extended has a first N-type impurity region NR1 and a second N-type impurity region NR2. The first N-type impurity region NR1 is a region formed by extending the drain of the N-type transistor TNQ3 along the first extending direction DE1. On the other hand, the second N-type impurity region NR2 is a region formed to extend from the end (corner position) of the first N-type impurity region NR1 along the third extending direction DE3. That is, the first and second N-type impurity regions NR1 and NR2 are formed by extending the drain of the N-type transistor TNQ3 in an L shape. The third extending direction DE3 is a direction that intersects the first extending direction DE1, and is a direction orthogonal to DE1 in FIG. 7A.

  The potential stabilizing P-type impurity region PRS is laid out at a location on the first extending direction DE1 side of the second N-type impurity region NR2 and facing NR2. That is, the second N-type impurity region NR2 and the potential stabilizing P-type impurity region PRS are formed along the third extending direction DE3 while facing each other. As shown in FIG. 7B, the diode DI2 includes an N-type impurity region NR2 and the like as a cathode, and a diode having a P-type well PWL in which the potential stabilizing P-type impurity regions PRS and PRS are formed as an anode. Become.

  As described above, when the resistor RP is formed using an L-shaped P-type impurity region or an N-type impurity region, the resistor RP is formed to extend without significantly increasing the width of the pixel circuit in the second direction D2. The length of the impurity region can be increased, and the resistance value of the resistor RP can be increased. That is, a high resistance RP can be obtained with a small layout area. By increasing the resistance value of the resistor RP, the charge flowing from the pixel electrode to the transistor side of the output circuit 30 (CIVQ) can be further restricted, and deterioration of the characteristics of the transistor of the output circuit 30 can be suppressed.

  In FIGS. 6A and 6B, the second P-type impurity region PR2 and the N-type impurity region NRS for stabilizing the potential formed along the second extending direction DE2 while facing each other are used. , Diode DI1 is formed. Similarly, in FIGS. 7A and 7B, the second N-type impurity region NR2 and the potential stabilizing P-type impurity region PRS formed along the third extending direction DE3 while facing each other are shown. As a result, a diode DI2 is formed. In this way, the area of the PN junction surface of the diodes DI1 and DI2 can be increased, and the charge from the pixel electrode can easily flow to the diodes DI1 and DI2, so that the transistors of the output circuit 30 It becomes possible to suppress deterioration of characteristics and the like.

  Returning to the description of the layout arrangement in FIG. As shown in F1 of FIG. 5, the P-type transistors TPQ2 and TPQ3 constituting the clocked inverter circuit CIVQ of FIG. 3 and the P-type transistor TPQ1 constituting the transfer gate TGQ are laid out along the first direction D1. Is done. Similarly, as indicated by F2, N-type transistors TNQ2 and TNQ3 constituting the clocked inverter circuit CIVQ and an N-type transistor TNQ1 constituting the transfer gate TGQ are laid out along the first direction D1. Specifically, the channel regions (overlapping regions of the polysilicon layer and the impurity layer) of these transistors are laid out along the first direction D1.

  With such a layout arrangement, the six transistors TPQ2, TPQ3, TPQ1, TNQ2, TNQ3, and TNQ1 can be efficiently and compactly arranged in a narrow space in the horizontal direction. Therefore, the width of the pixel circuit in the horizontal direction (D2 direction) can be reduced, and the layout area of the pixel circuit can be reduced.

  Further, in FIG. 5, as indicated by F3, the drain of the P-type transistor TPQ2 and the source of the P-type transistor TPQ3 of the clocked inverter circuit CIVQ are formed by a common impurity region (P-type impurity region). As indicated by F4, the drain of the P-type transistor TPQ3 and the source of the P-type transistor TPQ1 of the transfer gate TGQ are formed by a common impurity region (P-type impurity region). That is, three polysilicon patterns corresponding to the gates of TPQ2, TPQ3, and TPQ1 are formed so as to overlap with one P-type impurity region. Similarly, as indicated by F5, the drain of the N-type transistor TNQ2 and the source of the N-type transistor TNQ3 of the clocked inverter circuit CIVQ are formed by a common impurity region (N-type impurity region). As indicated by F6, the drain of the N-type transistor TNQ3 and the source of the N-type transistor TNQ1 of the transfer gate TGQ are formed by a common impurity region (N-type impurity region). That is, three polysilicon patterns corresponding to the gates of TNQ2, TNQ3, and TNQ1 are formed so as to overlap with one N-type impurity region.

  With this layout arrangement, the six transistors TPQ2, TPQ3, TPQ1, TNQ2, TNQ3, and TNQ1 can be efficiently and compactly arranged in a narrow space in the vertical direction. Therefore, the width of the pixel circuit in the vertical direction (D1 direction) can be reduced, and the layout area of the pixel circuit can be reduced. Note that the source of the transistor is an impurity region (diffusion region) on the power supply side (VDD side, VSS side), and the drain is an impurity region on the output node side.

  Further, as shown in B1 of FIG. 5, the P-type transistors TP2 and TP3 constituting the clocked inverter circuit CIV1 of FIG. 3 and the P-type transistor TP1 constituting the transfer gate TG1 are laid out along the first direction D1. Be placed. Similarly, as indicated by B2, N-type transistors TN2 and TN3 constituting the clocked inverter circuit CIV1 and N-type transistor TN1 constituting the transfer gate TG1 are laid out along the first direction D1.

  With such a layout arrangement, the six transistors TP2, TP3, TP1, TN2, TN3, and TN1 can be efficiently and compactly arranged in a narrow space in the lateral direction. Therefore, the width of the pixel circuit in the horizontal direction (D2 direction) can be reduced, and the layout area of the pixel circuit can be reduced.

  Further, as shown in B3 in FIG. 4, the drain of the P-type transistor TP2 and the source of the P-type transistor TP3 of the clocked inverter circuit CIV1 are formed by a common impurity region (P-type impurity region). As shown in B4, the drain of the P-type transistor TP3 and the source of the P-type transistor TP1 of the transfer gate TG1 are formed by a common impurity region (P-type impurity region). Similarly, as indicated by B5, the drain of the N-type transistor TN2 and the source of the N-type transistor TN3 of the clocked inverter circuit CIV1 are formed by a common impurity region (N-type impurity region). As shown in B6, the drain of the N-type transistor TN3 and the source of the N-type transistor TN1 of the transfer gate TG1 are formed by a common impurity region (N-type impurity region).

  With such a layout arrangement, the six transistors TP2, TP3, TP1, TN2, TN3, and TN1 can be efficiently and compactly arranged in a narrow space in the vertical direction. Therefore, the width of the pixel circuit in the vertical direction (D1 direction) can be reduced, and the layout area of the pixel circuit can be reduced.

  In FIG. 5, as indicated by B6, P-type transistors TP6 and TP7 constituting the clocked inverter circuit CIV2 and P-type transistor TP5 constituting the transfer gate TG2 are laid out along the first direction D1. . Similarly, as indicated by B7, N-type transistors TN6 and TN7 constituting the clocked inverter circuit CIV2 and an N-type transistor TN5 constituting the transfer gate TG2 are laid out along the first direction D1.

  Further, in FIG. 5, the drain of the P-type transistor TP6 and the source of the P-type transistor TP7 are formed by a common impurity region, and the drain of the P-type transistor TP7 and the source of the P-type transistor TP5 are formed by a common impurity region. Similarly, the drain of the N-type transistor TN6 and the source of the N-type transistor TN7 are formed by a common impurity region, and the drain of the N-type transistor TN7 and the source of the N-type transistor TN5 are formed by a common impurity region. By adopting such a layout arrangement, the layout area of the pixel circuit can be further reduced.

  In FIG. 5, as shown by B1 and B2, P-type transistors TP2, TP3, TP1, and N-type transistors TN2, TN3, and TN1 are laid out along the first line L1 along the first direction D1. The Similarly, as indicated by B6 and B7, P-type transistors TP6, TP7 and TP5 and N-type transistors TN6, TN7 and TN5 are laid out along the second line L2 along the first direction D1.

  As shown in B8 and B9, the P-type transistor TP4 and the N-type transistor TN4 constituting the inverter circuit IV1 of FIG. 3 are laid out between the first line L1 and the second line L2.

  In this way, the space between the first line L1 and the second line L2 can be effectively used to lay out the P-type transistor TP4 and the N-type transistor TN4 constituting the inverter circuit IV1. Therefore, the inverter circuit IV1 can be laid out efficiently while minimizing the increase in the width of the pixel circuit in the horizontal and vertical directions. Further, by arranging the transistors of the inverter circuit IV1 between the first and second lines L1 and L2 where the transistors of the transfer gate TG1 and the clocked inverter circuit CIV1 are arranged, the input and output of the inverter circuit IV1 are arranged. The signal lines connected to can be efficiently wired.

  FIG. 8 is a layout arrangement example in which the wiring of the first metal layer (MET1) is shown in addition to the impurity layer (ACT) and the polysilicon layer (POLY) of FIG. Here, the metal layer is, for example, an aluminum layer. As shown in FIG. 8, most of the signal lines connecting the transistors are formed of the first metal layer.

  FIG. 9 is a layout wiring example of the second metal layer (MET2) of the pixel circuit. In FIG. 9, the signal line formed of the second metal layer is wired along the second direction D2. Specifically, the signal lines of the scanning signals SG and XSG and the test signals XT and XST are formed of the second metal layer and wired in the horizontal direction along the second direction D2. These signal lines are connected to the lower signal lines and transistors through via contacts.

  FIG. 10 is a layout wiring example of the third metal layer (MET3) of the pixel circuit. In FIG. 10, the signal line formed of the third metal layer is wired along the first direction D1. Specifically, the signal lines of the data signal SDA, the subframe synchronization signals SF and XSF, the ON drive waveform signal SON, the OFF drive waveform signal SOFF, and the high impedance control signals SHZ and XSHZ are formed in the third metal layer. Then, it is wired in the vertical direction along the first direction D1. These signal lines are connected to the lower signal lines and transistors through via contacts.

  In the present embodiment, the pixel circuit connected to the same scanning line and the corresponding pixel are arranged along the second direction D2. Then, the scanning signals SG and XSG are supplied to the pixel circuits connected to the same scanning line from the signal line wired in the second metal layer along the second direction D2 as shown in FIG. The same applies to the test signals ST and XST.

  On the other hand, the pixel circuit connected to the same data line and the corresponding pixel are arranged along the first direction D1. For the pixel circuits connected to the same signal line, as shown in FIG. 10, the data signal SDA, subframe synchronization signals SF and XSF, which are wired in the third metal layer along the first direction D1, are turned on. Signals are supplied from the signal lines of the waveform signal SON, the off-drive waveform signal SOFF, and the high impedance control signals SHZ and XSHZ. Note that VDD and VSS power supply lines are wired along the second direction D2 as shown in FIG. 9 and also along the first direction D1 as shown in FIG. Is done.

  As described above, by arranging the signal lines formed of the second and third metal layers, it is possible to realize an appropriate and efficient signal line layout according to the arrangement state of the pixels.

4). Sub-frame driving Next, as an example of a driving method of the electro-optical device (electro-optical panel) to which the present embodiment is applied, sub-frame driving at equal intervals will be described.

  In subframe driving, as shown by A1 in FIG. 11, one frame is divided into, for example, six subframes SF1 to SF6. The subframes SF1 to SF6 are equally spaced subframes having the same period length.

  In each subframe, the pixel is driven with an on voltage or an off voltage. In FIG. 11, subframes that are driven with the on-voltage are shaded. For example, the on-voltage is an applied voltage that maximizes the transmittance in the transmittance characteristics of the liquid crystal with respect to the applied voltage. The off voltage is an applied voltage at which the transmittance is minimum in the transmittance characteristics of the liquid crystal with respect to the applied voltage.

  As shown in A1, it is assumed that an on-voltage is applied in the subframe SF1 and an off-voltage is applied in the subframes SF2 to SF6. In this case, as indicated by A2, since the length of the subframe is short with respect to the response time of the liquid crystal, the transmittance does not become maximum within the period of the subframe SF1, and the transmittance gradually increases. In the subsequent subframe, the transmittance gradually decreases. At this time, the gradation of the pixel value is determined by the integral value of the transmittance curve shown in A2, and the larger the integral value, the higher the gradation.

  As shown in A3, when the combination pattern of on-voltage and off-voltage (hereinafter referred to as subframe pattern) is changed, the shape of the transmittance curve changes according to the subframe pattern as shown in A4. Therefore, the gradation of an image can be displayed by setting a subframe pattern for each gradation in advance so that desired gradation characteristics can be obtained. Note that in this embodiment, a period in which a pixel is driven with an off-voltage may be provided in a subframe in which the pixel is driven with an on-voltage, and a change in gradation characteristics due to a change in transmittance response characteristics may be suppressed.

  FIG. 12 shows a configuration example of a circuit device of an electro-optical device that realizes subframe driving. This circuit device includes a waveform signal supply circuit 40 and first to kth pixel circuits 50-1 to 50-k (k is a natural number). Note that the circuit device according to the present embodiment is not limited to the configuration shown in FIG. 12, and various modifications such as omitting some of the components or adding other components are possible.

  The pixel circuits 50-1 to 50-k output drive data signals SDR1 to SDRk to drive the pixel electrodes of the pixels 60-1 to 60-k. More specifically, the pixel circuits 50-1 to 50-k include latch units 10-1 to 10-k, selectors 20-1 to 20-k, and output circuits 30-1 to 30-k, respectively. Hereinafter, the configuration and operation of the pixel circuit 50-1 will be described as an example, but the configurations and operations of the other pixel circuits 50-2 to 50-k are the same.

  The latch unit 10-1 receives the scanning signal SG (XSG), the data signal SDA, and the subframe synchronization signal SF (XSF), and latches (stores or holds) the data signal corresponding to the pixel 60-1.

  The selector 20-1 receives the on-drive waveform signal SON, the off-drive waveform signal SOFF, and the data signal held in the latch unit 10-1, and outputs a signal SLQ1. Specifically, the selector 20-1 outputs the on-drive waveform signal SON as the signal SLQ1 in the subframe in which the data signal is at the on logic level. On the other hand, the selector 20-1 outputs the off drive waveform signal SOFF as the signal SLQ1 in the subframe in which the data signal is at the off logic level. Then, the output circuit 30-1 outputs a signal obtained by buffering the signal SLQ1 from the selector 20-1 to the corresponding pixel 60-1 as the drive data signal SDR1.

  Here, the ON logic level of the data signal is a first logic level corresponding to the ON driving state of the pixel, and is, for example, a logic level “1”. The off logic level of the data signal is a second logic level corresponding to the off drive state of the pixel, for example, a logic level “0”. For example, in a liquid crystal display device such as LCOS (Liquid Crystal On Silicon), a driving state in which a pixel is driven to transmit light is an on driving state, and a driving state in which the pixel is driven to transmit light is not transmitted. The drive state is off. The subframe pattern described above with reference to FIG. 11 and the like is represented by a combination of the on logic level and the off logic level, and the combination is set corresponding to each gradation data.

  The waveform signal supply circuit 40 outputs an on-drive waveform signal SON and an off-drive waveform signal SOFF. For example, these waveform signals are generated and output based on a temperature detection result from a temperature sensor (not shown). The waveform signal supply circuit 40 outputs a counter electrode drive signal VCOM (counter electrode drive voltage) to drive the counter electrodes of the pixels 60-1 to 60-k.

  The on-drive waveform signal SON (on-drive waveform voltage) output from the waveform signal supply circuit 40 is a signal that defines the voltage waveform of the drive data signal corresponding to the on logic level of the data signal. The off drive waveform signal SOFF (off drive waveform voltage) is a signal that defines the voltage waveform of the drive data signal corresponding to the off logic level of the data signal. The voltage waveform applied to the pixel 60-1 is determined by the voltage waveform of the drive data signal and the voltage waveform of the counter electrode drive signal.

5. Electro-Optical Device FIG. 13 shows a configuration example of an electro-optical device in which the pixel circuit of this embodiment is used. This electro-optical device includes an electro-optical panel 400 (liquid crystal display panel in a narrow sense), a scanning signal output circuit 410, a data signal output circuit 420, a display controller 430, and a waveform signal supply circuit 440, and performs so-called frame sequential digital driving. Realize. The electro-optical device according to the present embodiment is not limited to the configuration shown in FIG. 13, and various modifications such as omitting some of the components or adding other components are possible.

  The electro-optical panel 400 includes a plurality of pixels for displaying a display image and a plurality of pixel circuits for driving the plurality of pixels. A scanning signal, a data signal, driving waveform signals SON and SOFF, a counter electrode driving signal VCOM, and a subframe synchronization signal SF are input to this pixel circuit. For example, one pixel circuit corresponds to one pixel, and the pixel and the pixel circuit are arranged in a matrix along scanning lines (gate lines) and data lines. For example, a pixel circuit CPX11 for driving the pixels PX11 and PX11 is arranged at the intersection of the line of the scanning signal SG1 and the line of the data signal SDA1.

  The display controller 430 receives the data transfer clock signal DCK, the data signal DATA, and other control signals from an external host controller or the like, controls each component of the electro-optical device, and performs display control of the electro-optical device. . In addition, the display controller 430 generates a data signal for driving the equidistant subframes based on the data signal DATA. That is, the gradation data of the data signal DATA is converted into a subframe pattern that is a combination of an on logic level and an off logic level.

  The scanning signal output circuit 410 supplies scanning signals SG1 to SGm (m is a natural number) to the electro-optical panel 400. The scanning signals SG1 to SGm (gate signals) are signals for selecting (instructing) the scanning lines (gate lines) into which the data signals SDA1 to SDAn are taken in by the pixel circuit. The scanning signal output circuit 410 receives a horizontal synchronization signal HSYNC, a subframe synchronization signal SF, and the like from the display controller 430.

  The data signal output circuit 420 supplies data signals SDA <b> 1 to SDAn to the electro-optical panel 400. The data signals SDA1 to SDAn are data signals for driving equally spaced subframes corresponding to pixels on each data line. The data signal output circuit 420 receives a horizontal synchronization signal HSYNC, a subframe synchronization signal SF, a data signal converted into a subframe pattern, and the like from the display controller 430.

  The waveform signal supply circuit 440 supplies an on drive waveform signal SON, an off drive waveform signal SOFF, and a counter electrode drive signal VCOM to the electro-optical panel 400. The waveform signal supply circuit 440 receives a temperature detection result from a temperature sensor (not shown) and a signal from the display controller 430 (subframe synchronization signal, horizontal synchronization signal count value, subframe synchronization signal count value, etc.).

  The electro-optical device of FIG. 13 is configured by, for example, LCOS (liquid crystal display device in a broad sense). LCOS is a liquid crystal display device in which a pixel circuit, a wiring layer, a reflective electrode (pixel electrode), a liquid crystal layer, and a counter electrode are stacked on a silicon substrate (in a broad sense, a semiconductor substrate). Peripheral circuits such as a waveform signal supply circuit 440 are also integrated on the silicon substrate. The LCOS is a reflective liquid crystal display device, and light incident from the transparent counter electrode side passes through the liquid crystal layer and is reflected by the reflective electrode, and the reflected light is emitted again through the liquid crystal layer. The display image is obtained by projecting the emitted light onto a screen or the like.

  FIG. 14 shows an example of a signal waveform for explaining the operation of this embodiment. FIG. 14 shows signal waveform examples of the subframe synchronization signal SF, the scanning signals SG1 to SGm, and the data signal SDA.

  As shown at E1 in FIG. 14, when the scanning signal SG1 becomes H level (active), the transfer gate TG1 in FIG. 3 is turned on, the clocked inverter circuit CIV1 is in the high impedance output state, and the data signal SDA is the first. The latch circuit 11 takes in. As shown in E2, when the scanning signal SG1 becomes L level (inactive), the transfer gate TG1 is turned off, the clocked inverter circuit CIV1 is in the output state, and the captured data signal is transferred to the first latch circuit 11. Is held.

  After the scanning line for one screen is selected, when the subframe synchronization signal SF becomes H level (active) as shown by E3, the transfer gate TG2 is turned on, and the clocked inverter circuit CIV2 outputs a high impedance signal. The data signal latched in the first latch circuit 11 is transferred to the second latch circuit 12 and taken in. Then, as shown at E4, when the subframe synchronization signal SF becomes L level, the transfer gate TG2 is turned off, the clocked inverter circuit CIV2 enters the output state, and the fetched data signal is held in the second latch circuit 12. Is done.

  As described above, when the present embodiment is applied to subframe driving, a frame is divided into a plurality of subframes as shown in FIG. Then, in each subframe of the plurality of subframes, each scanning line of the plurality of scanning lines of the electro-optical device is sequentially selected as shown in FIG.

  The transfer gate TG1 of the pixel circuit of FIG. 3 and the P-type transistor TP3 and the N-type transistor TN3 of the clocked inverter circuit CIV1 are on / off controlled based on the scanning signal SG. This scanning signal SG is a signal that becomes active (H level) when a scanning line corresponding to a pixel circuit among a plurality of scanning lines is selected.

  On the other hand, the transfer gate TG2 of the pixel circuit and the P-type transistor TP6 and the N-type transistor TN6 of the clocked inverter circuit CIV2 are on / off controlled based on the subframe synchronization signal SF. This subframe synchronization signal SF is a signal that becomes active in synchronization with each subframe (a signal that becomes active in synchronization with the start of the subframe).

  As described above, the electro-optical panel can be driven by applying sub-frame driving to the electro-optical device having the pixel circuit of the present embodiment.

6). Electronic Device FIG. 15 shows a configuration example of an electronic device to which the electro-optical device of this embodiment is applied. The electronic apparatus includes an electro-optical device 500, a controller 510 (host controller), a processing unit 520, a storage unit 530, and an I / F unit (external interface unit) 540. Note that the electronic apparatus of the present embodiment is not limited to the configuration of FIG. 15, and various modifications such as omitting some of the components or adding other components are possible.

  In this electronic device, image data and moving image data are input via the I / F unit 540. The input image data and moving image data are stored in the storage unit 530. The processing unit 520 processes image data and moving image data from the storage unit 530. For example, the processing unit 520 performs tone correction processing, processing for improving image quality, processing for converting a data format, and the like. The processing unit 520 outputs the processed data to the electro-optical device 500, and the electro-optical device 500 performs image display by the above-described equally-spaced subframe driving or the like based on the data. The controller 510 is composed of, for example, an MPU and controls the above processing.

  According to the above configuration, various electronic devices such as a liquid crystal projector, a projection-type television device, and a 3D projector can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (clocked inverter circuits, liquid crystal display devices, etc.) described together with different terms (buffer circuit, electro-optical device, etc.) in a broader sense or the same meaning at least once are used in the specification or drawings. It can be replaced by the different terms at any point. Further, the configuration and operation of the pixel circuit, the electro-optical device, the electronic apparatus, and the like are not limited to those described in the present embodiment, and various modifications can be made.

RP resistor, DI1, DI2 first and second diodes,
TG1, TG2, TGS1, TGS2, TGQ transfer gate,
CIV1, CIV2, CIVQ clocked inverter circuit,
IV1, IV2 inverter circuit,
SDA, SDA1-SDAn data signal, SG, XSG, SG1-SGm scanning signal,
SDR, SDR1 to SDRk drive data signal,
SON ON drive waveform signal, SOFF OFF drive waveform signal,
SF, XSF subframe synchronization signal,
ST XST Test signal, SHZ, XSHZ High impedance control signal,
10, 10-1 to 10-k latch part,
11 first latch circuit, 12 second latch circuit,
20, 20-1 to 20-k selector, 30, 30-1 to 30-k output circuit,
40 waveform signal supply circuit, 50-1 to 50-k pixel circuit, 60-1 to 60-k pixel,
410 scanning signal output circuit, 420 data signal output circuit,
430 display controller, 440 waveform signal supply circuit,
500 electro-optical device, 510 controller, 520 processing unit,
530 storage unit, 540 I / F unit (external interface unit)

Claims (12)

A pixel circuit for driving a pixel of an electro-optical device,
A latch unit for latching data signals;
An output circuit having a buffer circuit and buffering a drive data signal based on a latch data signal from the latch unit and outputting the buffered data signal to the pixel;
The output circuit is
A resistor provided between an output node of the buffer circuit and a pixel circuit output node;
A first diode provided between a high-potential side power supply node and the pixel circuit output node and having a forward direction from the pixel circuit output node toward the high-potential side power supply node;
A second diode provided between the pixel circuit output node and the low-potential-side power supply node and having a forward direction from the low-potential-side power supply node toward the pixel circuit output node;
Only including,
The buffer circuit of the output circuit is:
Including a P-type transistor and an N-type transistor connected in series,
The resistance is
A pixel circuit comprising: a P-type impurity region in which a drain of the P-type transistor is extended and an N-type impurity region in which a drain of the N-type transistor is extended . In claim 1 ,
The first diode is
An N-type impurity region for stabilizing the potential and an N-type impurity region for stabilizing the potential, which are opposed to the P-type impurity region and connected to the high-potential-side power supply node, and the N-type impurity region for potential stabilization are formed. A diode having a type well as a cathode,
The second diode is
The N-type impurity region is used as a cathode, and a P-type impurity region for stabilizing the potential and the P-type impurity region for stabilizing the potential, which are opposed to the N-type impurity region and connected to the low-potential side power supply node, are formed. A pixel circuit characterized by being a diode having a mold well as an anode. In claim 2 ,
The P-type impurity region is
A first P-type impurity region extending along the first extending direction, and a second extension that intersects the first extending direction from an end of the first P-type impurity region A second P-type impurity region formed extending along the direction;
The N-type impurity region is
A first N-type impurity region formed extending along the first extending direction, and a third extension intersecting the first extending direction from an end of the first N-type impurity region. A second N-type impurity region formed extending along the current direction;
The potential stabilizing N-type impurity region is disposed on the first extending direction side of the second P-type impurity region and at a location facing the second P-type impurity region,
The potential stabilization P-type impurity region is disposed on the first extending direction side of the second N-type impurity region and at a location facing the second N-type impurity region. A characteristic pixel circuit. In any one of Claims 1 thru | or 3 ,
The output circuit is
A transfer gate that is provided between a signal node to which a given signal is input or output and the output node of the output circuit, and is configured by a first P-type transistor and a first N-type transistor connected in parallel. When,
Including a clocked inverter circuit which is the buffer circuit;
The clocked inverter circuit is:
A second P-type transistor, a third P-type transistor, a third N-type transistor, and a second N-type transistor connected in series,
The P-type transistor is the third P-type transistor of the clocked inverter circuit;
The pixel circuit, wherein the N-type transistor is the third N-type transistor of the clocked inverter circuit. In claim 4 ,
The second P-type transistor and the third P-type transistor constituting the clocked inverter circuit, and the first P-type transistor constituting the transfer gate are disposed along a first direction;
The second N-type transistor and the third N-type transistor constituting the clocked inverter circuit and the first N-type transistor constituting the transfer gate are arranged along the first direction. A pixel circuit characterized by that. In claim 5 ,
The drain of the second P-type transistor and the source of the third P-type transistor are formed by a common impurity region, and the drain of the third P-type transistor and the source of the first P-type transistor are common. Formed by impurity regions;
The drain of the second N-type transistor and the source of the third N-type transistor are formed by a common impurity region, and the drain of the third N-type transistor and the source of the first N-type transistor are common. A pixel circuit formed by an impurity region. In any one of Claims 4 thru | or 6 .
At the time of testing, a test signal is input as the given signal to the signal node of the transfer gate, or the pixel inspection result signal is output as the given signal from the signal node of the transfer gate. A pixel circuit. In claim 7 ,
During normal operation,
The first P-type transistor and the first N-type transistor of the transfer gate are turned off, the second P-type transistor and the second N-type transistor of the clocked inverter circuit are turned on,
During testing,
The first P-type transistor and the first N-type transistor of the transfer gate are turned on, and the second P-type transistor and the second N-type transistor of the clocked inverter circuit are turned off. A pixel circuit. A pixel circuit for driving a pixel of an electro-optical device,
A latch unit for latching data signals;
An output circuit having a buffer circuit and buffering a drive data signal based on a latch data signal from the latch unit and outputting the buffered data signal to the pixel;
The output circuit is
A resistor provided between an output node of the buffer circuit and a pixel circuit output node;
A first diode provided between a high-potential side power supply node and the pixel circuit output node and having a forward direction from the pixel circuit output node toward the high-potential side power supply node;
A second diode provided between the pixel circuit output node and the low-potential-side power supply node and having a forward direction from the low-potential-side power supply node toward the pixel circuit output node;
Only including,
The latch portion is
A first latch circuit that latches and stores a data signal for driving the pixel;
A second latch circuit for latching and storing the data signal transferred from the first latch circuit;
The pixel circuit further comprising a selector which is controlled based on the latch data signal from the second latch circuit and selects and outputs either the on-drive waveform signal or the off-drive waveform signal . In claim 9 ,
When one frame is divided into a plurality of subframes, and each scanning line of the plurality of scanning lines of the electro-optical device is sequentially selected in each subframe of the plurality of subframes,
The first latch circuit includes:
Latching the data signal based on a scanning signal that becomes active when a scanning line corresponding to a pixel circuit of the plurality of scanning lines is selected;
The second latch circuit includes:
A pixel circuit that latches the data signal transferred from the first latch circuit based on a subframe synchronization signal that becomes active in synchronization with each subframe. A plurality of pixels;
A plurality of pixel circuits each of which is a pixel circuit according to any one of claims 1 to 10 ;
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 11 .

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