JP5606787B2 - Thin film transistor manufacturing method, thin film transistor, image sensor, X-ray sensor, and X-ray digital imaging apparatus - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film transistor, and relates to a thin film transistor, an image sensor, an X-ray sensor, and an X-ray digital imaging apparatus.

  In recent years, thin film transistors using an In—Ga—Zn—O-based (hereinafter sometimes abbreviated as “IGZO-based” or “IGZO”) oxide semiconductor thin film for a channel layer have been actively developed. (See Non-Patent Documents 1 and 2). The oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light, so a flexible transparent thin film transistor is formed on a substrate such as a plastic plate or a resin film. Is possible.

On the other hand, in a thin film transistor using an IGZO-based oxide semiconductor film, a change in threshold voltage during continuous energization is extremely large and lacks stability as a device. It has been proposed to stabilize the electrical characteristics by performing a heat treatment (referred to as “post-annealing” or “annealing” as appropriate) later in an oxidizing atmosphere (see Patent Document 1).
In addition, in the case where an IGZO-based oxide semiconductor film is used for the channel layer, a resistance layer is provided between the oxide semiconductor layer and the oxide semiconductor layer and the gate insulating film in order to suppress change over time in electrical characteristics. A thin film transistor has been proposed (see Patent Document 2).

JP 2007-311404 A JP 2007-73701 A

K. Nomura, et al. , Science, 300 (2003) 1269 K. Nomura, Nature, 432 (2004) 488

  The IGZO thin film is very sensitive to the annealing temperature when it is annealed, and its conductivity changes by about 5 to 6 digits particularly in a low temperature annealing region of about 100 to 300 ° C. The large change in the conductivity in such a narrow temperature region means that, particularly when a thin film transistor is manufactured on a large-area substrate, the temperature unevenness during annealing is directly reflected in the electrical property unevenness, and the device characteristics It becomes difficult to ensure in-plane uniformity.

  While the need for post-annealing has been recognized, no method has been established to suppress electrical characteristic unevenness due to temperature unevenness during annealing, and this is a significant barrier especially in manufacturing large-area devices.

  In view of the above, a main object of the present invention is to provide a method for manufacturing a thin film transistor, in which variation in electrical characteristics due to heat treatment is suppressed when manufacturing a thin film transistor including an oxide semiconductor layer, and which is particularly suitable for manufacturing a large-area device. And

In order to solve the above problems, the following inventions are provided.
<1> A method for manufacturing a thin film transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode over a substrate,
Has a stacked structure including three or more layers having different compositions of the adjacent layers, and, located on the side closest to the gate electrode a gate recently layer and the farthest is located on the side gate farthest layer from the gate electrode between the gate recently layer and the gate resistivity is less than the farthest layer low-resistance layer is present at least one layer, wherein the gate recently layer, each layer of the gate farthest layer, and the low-resistance layer The step of forming an oxide semiconductor layer having a total thickness of 30 to 200 nm ,
Forming a heat treatment after forming the oxide semiconductor layer;
A method of manufacturing a thin film transistor including:
<2> The method for producing a thin film transistor according to <1>, wherein the oxide semiconductor layer is formed with a three-layer structure.
<3> The method for producing a thin film transistor according to <1> or <2>, wherein the oxide semiconductor layer is amorphous.
<4> The method for manufacturing a thin film transistor according to any one of <1> to <3>, wherein each layer constituting the oxide semiconductor layer includes at least one element of In and Ga.
<5> Each of the layers constituting the oxide semiconductor layer is made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO). The manufacturing method of the thin-film transistor of description.
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.)
<6> the gate of the recent layer b / (a + b) and the gate farthest layer b / (a + b) is a thin film transistor, wherein the low-resistance layer b / (a + b) is greater than <5> Production method.
<7> The band gap of the gate recently layer bandgap and the gate farthest layer of manufacturing a thin film transistor according to any one of the wider than the band gap of the low-resistance layer <2> to <6> Method.
<8> The method for producing a thin film transistor according to any one of <1> to <7>, wherein the heat treatment step is performed in an oxidizing atmosphere.
<9> The method for producing a thin film transistor according to any one of <1> to <8>, wherein the heat treatment step is performed at a temperature of 100 ° C. to 300 ° C.
<10> The method for producing a thin film transistor according to any one of <1> to <9>, wherein the substrate has flexibility.
<11> A thin film transistor manufactured using the method for manufacturing a thin film transistor according to any one of <1> to <10>.
<12> A display device comprising the thin film transistor according to <11>.
<13> An image sensor comprising the thin film transistor according to <11>.
<14> An X-ray sensor comprising the thin film transistor according to <11>.
<15> An X-ray digital imaging apparatus comprising the X-ray sensor according to <14>.

  According to the present invention, when a thin film transistor having an oxide semiconductor layer is manufactured, variation in electrical characteristics due to heat treatment is suppressed, and the thin film transistor manufacturing method particularly suitable for manufacturing a large-area device, and the manufacturing method thereof. A thin film transistor, an image sensor, an X-ray sensor, and an X-ray digital imaging apparatus are provided.

It is sectional drawing which shows schematically the structure of the thin-film transistor manufactured by this invention. (A) Top gate-top contact type, (B) Top gate-bottom contact type, (C) Bottom gate-top contact type, (D) Bottom gate-bottom contact type It is a schematic sectional drawing which shows a part of liquid crystal display device of embodiment. It is a schematic block diagram of the electrical wiring of the liquid crystal display device of FIG. It is a schematic sectional drawing which shows a part of organic EL display apparatus of embodiment. It is a schematic block diagram of the electrical wiring of the organic electroluminescent display apparatus of FIG. It is a schematic sectional drawing which shows a part of X-ray sensor array of embodiment. It is a schematic block diagram of the electrical wiring of the X-ray sensor array of FIG. It is a figure which shows the relationship between annealing temperature and specific resistance. It is a figure which shows the relationship between annealing temperature and carrier concentration. It is a figure which shows the relationship between the annealing temperature and specific resistance in the comparative example 7. It is a figure which shows the relationship between the annealing temperature of Comparative Example 7, and carrier density. 6 is a schematic cross-sectional view showing a sample structure manufactured in Example 2. FIG. It is a figure which shows the Vg-Id characteristic of Example 2 and Comparative Example 8.

  Hereinafter, a method for manufacturing a thin film transistor of the present invention will be mainly described with reference to the accompanying drawings. In addition, what has the substantially same function may attach | subject the same code | symbol through all drawings, and may abbreviate | omit the description.

The inventors of the present invention can suppress the variation in conductivity particularly at low temperature annealing from room temperature to about 300 ° C. by forming an oxide semiconductor layer from three or more layers and then performing heat treatment. I found what I can do.
That is, the method for manufacturing a thin film transistor according to the present invention is a method for manufacturing a thin film transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate, to have a stacked structure including three or more layers with different composition of the layer, and the gate farthest layer disposed farthest from the nearest located on the side gate recently layer and the gate electrode to the gate electrode during the gate recently layer and the gate than the farthest layer having small specific resistance low resistance layer is present at least one layer, wherein the gate recently layer, the gate farthest layer, and each layer of the low-resistance layer The thickness is 5 to 100 nm, and includes a step of forming an oxide semiconductor layer having a total thickness of 30 to 200 nm and a step of heat-treating after forming the oxide semiconductor layer.

  1A to 1D schematically show the structures of thin film transistors that can be manufactured by the thin film transistor manufacturing method of the present invention. Note that in each thin film transistor in FIGS. 1A to 1D, common elements are denoted by the same reference numerals.

  The thin film transistors 1 to 4 according to this embodiment include an oxide semiconductor layer 12, a source electrode 13, a drain electrode 14, a gate insulating film 15, and a gate electrode 16 on a substrate 11. The oxide semiconductor layer 12 has a stacked structure composed of three layers 12A, 12B, and 12C having adjacent compositions different from each other, and includes the layer 12C and the gate electrode 16 that are disposed on the side closest to the gate electrode 16. Between the layer 12A disposed on the farthest side, the layer 12C disposed on the side closest to the gate electrode 16 and the low resistance layer having a smaller specific resistance than the layer 12A disposed on the side farthest from the gate electrode 16 12B exists and is configured. In the present invention, “the composition is different” means that a part of the components (elements) constituting the layer is different, and even if the components (elements) constituting the layer are the same, the content ratio of those components The case where the (composition ratio) is different is also included.

A thin film transistor 1 in the form shown in FIG. 1A is a top gate-top contact type transistor, and a thin film transistor 2 in the form shown in FIG. 1B is a top gate-bottom contact type transistor. The thin film transistor 3 in the embodiment shown in FIG. 1C is a bottom gate-top contact transistor, and the thin film transistor 4 in the form shown in FIG. 1D is a bottom gate-bottom contact transistor.
In the thin film transistor of the embodiment shown in FIGS. 1A to 1D, the function of each element given the same reference numeral is the same, and the same material can be applied.

  Hereinafter, each component will be described in detail. Note that the case where the top gate-top contact type thin film transistor 1 shown in FIG. 1A is manufactured as a typical example will be specifically described; however, the present invention is similarly applied to the case where other types of thin film transistors are manufactured. can do.

(substrate)
First, a substrate 11 for forming a thin film transistor is prepared.
There is no restriction | limiting in particular about the shape of the board | substrate 11, a structure, a magnitude | size, etc., It can select suitably according to the objective. The structure of the substrate 11 may be a single layer structure or a laminated structure.
The material of the substrate 11 may be selected according to the device to be manufactured. For example, an inorganic substrate such as glass, YSZ (yttrium stabilized zirconium), a resin substrate, a composite material thereof, or the like can be used.
Among these, a resin substrate or a composite material thereof is preferable from the viewpoint of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, Synthetic resin substrates such as aromatic ether, maleimide-olefin, cellulose, episulfide compounds, silicon oxide Composite plastic materials with children, metal nanoparticles, inorganic oxide nanoparticles, composite plastic materials with inorganic nitride nanoparticles, carbon fibers, composite plastic materials with carbon nanotubes, glass ferkes, glass fibers, glass beads Composite plastic materials, composite plastic materials with clay minerals and particles having a mica-derived crystal structure, laminated plastic materials having at least one bonding interface between the thin glass and the single organic material, an inorganic layer and an organic layer Oxidation treatment (for example, anodic oxidation treatment) is applied to a composite material having barrier performance having at least one bonding interface by alternately laminating, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate, or the surface. With an oxide film with improved surface insulation Aluminum substrate or the like can be used. The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.

  The thickness of the substrate 11 in the present invention is preferably 50 μm or more and 500 μm or less. When the thickness of the substrate 11 is 50 μm or more, the flatness of the substrate itself is further improved. Further, when the thickness of the substrate 11 is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a substrate for a flexible device becomes easier.

(Oxide semiconductor layer)
An oxide semiconductor layer 12 having a stacked structure of three or more layers and having different compositions of adjacent layers 12A, 12B, and 12C is formed over the substrate 11.
The material constituting each of the layers 12A, 12B, and 12C constituting the oxide semiconductor layer 12 is not particularly limited as long as it is an oxide semiconductor that functions as a channel layer, but Al, Sc, At least one element selected from the group consisting of Ti, Mn, Fe, Ga, Y, In, Sn, Ho, Er, Tm, Yb, and Lu; and Mg, Ca, Ni, Zn, Sr, and Ba Preferably, it contains at least one element selected from the group consisting of, and more preferably contains at least one element of In and Ga.

  The oxide semiconductor layer 12 is preferably amorphous. An amorphous film is easy to form a uniform film over a large area, and since there is no grain boundary like a polycrystal, it is easy to suppress variations in device characteristics. Whether or not the oxide semiconductor layer 12 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 12 can be determined to be amorphous.

  Of the layers 12A, 12B, and 12C constituting the oxide semiconductor layer 12, the layer 12C (referred to as “gate nearest layer” as appropriate) disposed on the side closest to the gate electrode 16 and the side farthest from the gate electrode 16 Between the arranged layer 12A (referred to as “gate farthest layer” as appropriate), there is at least one layer (low resistance layer) 12B having a smaller specific resistance than the gate nearest layer 12C and the gate farthest layer 12A. ing. With such a layer structure, the low-resistance layer 12B functions as a channel, and the gate nearest layer 12C and the gate farthest layer 12A also function as a protective layer, before and after the formation of the oxide semiconductor layer 12. It is possible to suppress the influence of damage caused by the process. In addition, the magnitude of the specific resistance of each layer can be evaluated by a scanning spread resistance microscope (Scanning Spread Resistance Microscopy).

  In addition, a layer (gate closest layer) 12C disposed on the side closest to the gate electrode 16 in the oxide semiconductor layer 12 and a layer (farthest gate layer) 12A disposed on the side farthest from the gate electrode 16 are separated from each other with a band gap. By forming the layer 12B having a narrow band gap in a region sandwiched between the gate closest layer 12C and the gate farthest layer 12A, a variation in electrical characteristics during annealing, which is an effect of the present invention, is formed by using a wide oxide semiconductor. In addition to being suppressed, the region sandwiched between the nearest gate layer 12C and the farthest gate layer 12A forms a quantum well, resulting in improved mobility.

More specifically, in the oxide semiconductor layer 12, the constituent layers 12A, 12B, and 12C are made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO). Is particularly preferred. Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively. In particular, it is more preferable that b / (a + b) of the gate nearest layer 12C and the gate farthest layer 12A is larger than b / (a + b) of the low resistance layer 12B. By adopting such a layer structure, the low resistance layer 12B can be easily formed and is sandwiched between the same kind of materials having different cation composition ratios. In comparison, the defect density at the interface is reduced, and a thin film transistor excellent in terms of uniformity, stability, and reliability can be provided.

For example, the In—Ga—Zn—O system is used, and the oxide semiconductor layer 12 including three or more layers is formed using a deposition method such as sputtering so that the composition of adjacent layers is different.
From the viewpoint of film flatness and manufacturing suitability, the thickness of each layer 12A, 12B, 12C of the oxide semiconductor layer 12 is preferably 5 nm or more and 100 nm or less, and the total thickness (total thickness) of the oxide semiconductor layer 12 is About 30-200 nm is preferable.

  In addition, it is preferable that the three or more layers 12A, 12B, and 12C constituting the oxide semiconductor layer 12 are continuously formed without being exposed to the atmosphere. By continuously forming the film without being exposed to the atmosphere, it is possible to suppress contamination of the interface between the regions of the respective layers 12A, 12B, and 12C and generation of defects at the interface. As a result, more excellent transistor characteristics can be obtained. In addition, since the number of film formation steps can be reduced, the manufacturing cost can be reduced.

As a method of stacking the oxide semiconductor layers 12 having different compositions (for example, cation composition ratio) by sputtering, for example, after forming the first layer 12A or the second layer 12B constituting the oxide semiconductor layer 12 Alternatively, the film formation may be stopped once, the power applied to the target may be changed, and then the film formation may be resumed, or the power applied to the target may be changed quickly or slowly without stopping the film formation. May be.
Alternatively, a method may be used in which two or more targets having different composition ratios are arranged in the deposition chamber, and the layers 12A, 12B, and 12C are deposited using different targets. The target to be used may be co-sputtering using a combination of In, Ga, Zn, or an oxide or a composite oxide thereof, or the composition of the metal element in the IGZO film formed in advance. A single sputtering of a complex oxide target may be used such that the ratio is a desired ratio, for example, Ga / (In + Ga) = 0.75, Zn / (In + Ga) = 0.5.
Note that when a plurality of oxide semiconductor layers (regions) are formed by, for example, a method in which the power applied to the target is changed quickly or slowly without stopping the film formation, the composition continuously changes between adjacent layers. However, what is necessary is just to set thickness etc. by making the intermediate position of the area | region where a composition changes continuously into the boundary of an adjacent layer.

  After the film formation, the oxide semiconductor layer 12 is patterned. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid (Al etching solution: manufactured by Kanto Chemical Co., Inc.) A pattern is formed by etching.

(Source / drain electrodes)
A metal film for forming the source / drain electrodes 13 and 14 is formed on the oxide semiconductor layer 12. The source / drain electrodes 13 and 14 are made of a material having high conductivity, for example, metal such as Al, Mo, Cr, Ta, Ti, Au, Au, Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide. In addition, a metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (IZO) can be used. As the source / drain electrodes 13 and 14, these conductive films can be used as a single layer structure or a laminated structure of two or more layers.

The source / drain electrodes 13 and 14 are formed by, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of suitability with the material to be used. The thickness of the metal film is preferably 10 nm or more and 1000 nm or less, more preferably 50 nm or more and 100 nm or less in consideration of film formability, patterning properties by etching or lift-off methods, conductivity, and the like.
Next, the metal film is patterned into a predetermined shape by etching or a lift-off method to form the source electrode 13 and the drain electrode 14. At this time, it is preferable to pattern the source / drain electrodes 13 and 14 and the wiring connected to these electrodes 13 and 14 simultaneously.

(Gate insulation film)
After forming the source / drain electrodes 13 and 14 and the wiring, the gate insulating film 15 is formed. The gate insulating film 15 preferably has high insulating properties. For example, an insulating film such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , or a compound thereof is at least included. An insulating film including two or more kinds may be used. The gate insulating film 15 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of the suitability of
The gate insulating film 15 is patterned into a predetermined shape by photolithography and etching.
Note that the gate insulating film 15 needs to have a thickness for reducing the leakage current and improving the voltage resistance. On the other hand, if the gate insulating film 15 is too thick, the driving voltage is increased. Although the gate insulating film 15 depends on the material, the thickness of the gate insulating film 15 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

(Gate electrode)
After forming the gate insulating film 15, the gate electrode 16 is formed. The gate electrode 16 is made of a material having high conductivity, for example, metal such as Al, Mo, Cr, Ta, Ti, Au, Au, Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide. It can be formed using a metal oxide conductive film such as (ITO) or zinc indium oxide (IZO). As the gate electrode 16, these conductive films can be used as a single layer structure or a stacked structure of two or more layers.

The gate electrode 16 is a material used from, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of the suitability of The thickness of the metal film is preferably 10 nm or more and 1000 nm or less, more preferably 50 nm or more and 200 nm or less in consideration of film formability, patterning properties by etching or lift-off methods, conductivity, and the like.
After the film formation, the gate electrode 16 is formed by patterning into a predetermined shape by etching or a lift-off method. At this time, it is preferable to pattern the gate electrode 16 and the gate wiring simultaneously.

(Post annealing)
After patterning the gate electrode 16, heat treatment (post-annealing) is performed. The post-annealing process may be performed at any timing after the oxide semiconductor layer 12 is formed, immediately after the oxide semiconductor film is formed, or after the formation of the source / drain electrodes 13 and 14, the gate insulating film. It may be performed after forming 15 or after all the patterning is completed.

  The temperature of the post-annealing is preferably 100 ° C. or more and 300 ° C. or less, more preferably 200 ° C. or less, considering the case where a flexible substrate is used. When the temperature is 100 ° C. or higher, moisture contained in the oxide semiconductor layer 12 can be reliably blown away. On the other hand, when the temperature is 300 ° C. or lower, particularly 200 ° C. or lower, it is formed on a flexible resin substrate such as a plastic substrate. Easy to do. Therefore, it becomes easier to apply the present invention to a flexible display using a plastic substrate with a thin film transistor.

  The atmosphere during post-annealing is preferably an oxidizing atmosphere. When post-annealing is performed in an inert atmosphere or a reducing atmosphere, oxygen in the oxide semiconductor layer is released and excess carriers are easily generated. However, if heat treatment is performed in an oxidizing atmosphere, oxygen in the oxide semiconductor layer is generated. And the normally-off driving thin film transistor can be easily manufactured.

In the present embodiment, the case of manufacturing the thin film transistor 1 having the top gate type structure has been described. However, the thin film transistor manufactured by the present invention is not limited to the top gate type, and may be a bottom gate type thin film transistor.
Regardless of the type of thin film transistor manufactured, according to the present invention, it is possible to effectively suppress variations in the electrical characteristics of the thin film transistor that are likely to occur due to heat treatment (post-annealing) after the oxide semiconductor layer 12 is formed. In particular, it is possible to provide a thin film transistor having high in-plane uniformity, stability, and reliability in manufacturing a large-area device. This effect inevitably improves the yield and leads to a reduction in production costs.

The use of the thin film transistor manufactured using the thin film transistor manufacturing method of the present invention is not particularly limited. For example, display devices such as an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, and an inorganic EL display device) , Etc.).
Furthermore, the thin film transistor manufactured using the manufacturing method of the present invention can be manufactured by a low temperature process using a resin substrate (for example, a flexible display), various sensors such as an X-ray sensor, MEMS (Micro Electro Mechanical System), etc. It is suitably used as a drive element (drive circuit) in various electronic devices.

The electro-optical device or sensor of the present invention includes the above-described thin film transistor of the present invention.
Examples of electro-optical devices include display devices (eg, liquid crystal display devices, organic EL display devices, inorganic EL display devices, etc.).
As an example of a sensor, an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like is suitable.
The electro-optical device or sensor of the present invention exhibits good characteristics with low power consumption. The term “characteristic” as used herein refers to a display characteristic in the case of an electro-optical device and a sensitivity characteristic in the case of a sensor.
Hereinafter, a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of an electro-optical device or sensor including a thin film transistor manufactured according to the present invention.

<Liquid crystal display device>
FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and FIG. 3 is a schematic configuration diagram of the electric wiring.

  As shown in FIG. 2, the liquid crystal display device 5 of this embodiment includes a top gate type thin film transistor 1 shown in FIG. 1A and a pixel lower portion on the gate electrode 16 protected by the passivation layer 54 of the transistor 1. A liquid crystal layer 57 sandwiched between the electrode 55 and the opposed upper electrode 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, respectively on the substrate 11 side and the color filter 58 of the TFT 1. In this configuration, polarizing plates 59a and 59b are provided.

  As shown in FIG. 3, the liquid crystal display device 5 of this embodiment includes a plurality of gate wirings 51 that are parallel to each other and data wirings 52 that are parallel to each other and intersect the gate wirings 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 1 is connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.

  In the liquid crystal device of this embodiment shown in FIG. 2, the top gate type thin film transistor 1 is provided. However, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type. A bottom-gate thin film transistor may also be used.

Since the thin film transistor manufactured according to the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, and in particular, in-plane uniformity, stability, and reliability are extremely high. Therefore, it is suitable for a large screen in a liquid crystal display device. In addition, when the active layer IGZO is amorphous, variations in device characteristics can be suppressed, and an excellent display quality with a large screen and no unevenness can be realized.
In addition, since the characteristic shift is small, the gate voltage can be reduced, and thus the power consumption of the display device can be reduced. In addition, according to the present invention, a thin film transistor can be manufactured using an amorphous IGZO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer. Therefore, a resin substrate (plastic substrate) is used as a substrate. Can be used. Therefore, according to the present invention, it is possible to provide a flexible liquid crystal display device that is excellent in display quality and has a large screen.

<Organic EL display device>
FIG. 4 shows a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 5 shows a schematic configuration diagram of electric wiring.

  There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

  In the active matrix type organic EL display device 6 of the present embodiment, the top gate type thin film transistor 1 shown in FIG. 1A is provided as a driving 1a and a switching 1b on a substrate 60 provided with a passivation layer 61a. An organic light emitting element 65 comprising an organic light emitting layer 64 sandwiched between the lower electrode 62 and the upper electrode 63 is provided on the transistors 1a and 1b, and the upper surface is also protected by the passivation layer 61b.

  As shown in FIG. 5, the organic EL display device 6 according to the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a data wiring 67 and a driving wiring 68 that are parallel to each other and intersect the gate wiring 66. I have. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16 a of the switching thin film transistor 1 b is connected to the gate wiring 66, and the source electrode 13 b of the switching thin film transistor 1 b is connected to the data wiring 67. The drain electrode 14b of the switching thin film transistor 1b is connected to the gate electrode 16a of the driving thin film transistor 1a, and the driving thin film transistor 1a is kept on by using the capacitor 69. The source electrode 13 a of the driving thin film transistor 1 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.

  The organic EL device of this embodiment shown in FIG. 4 includes the top gate type thin film transistors 1a and 1b. However, the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type. Without limitation, a bottom-gate thin film transistor may be used.

  Since the thin film transistor manufactured according to the present invention has high mobility, low power consumption and high quality display can be achieved. In particular, since in-plane uniformity, stability, and reliability are very high, it is suitable for manufacturing a large-screen organic EL display device. In addition, according to the present invention, a thin film transistor can be manufactured using an amorphous IGZO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer. Therefore, a resin substrate (plastic substrate) is used as a substrate. Can be used. Therefore, according to the present invention, it is possible to provide a flexible organic EL display device that is excellent in display quality and has a large screen.

  In the organic EL display device shown in FIG. 4, the top electrode 63 may be a top emission type with a transparent electrode, or the bottom electrode 62 and each TFT electrode may be a transparent electrode.

<X-ray sensor>
FIG. 6 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 7 shows a schematic configuration diagram of its electric wiring.

  More specifically, FIG. 6 is a schematic cross-sectional view enlarging a part of the X-ray sensor array. The X-ray sensor 7 of this embodiment includes a thin film transistor 1 and a capacitor 70 formed on a substrate, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. Composed. A passivation film 75 is provided on the thin film transistor 1.

  The capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 6) of the thin film transistor 1 through a contact hole 79 provided in the insulating film 78.

The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77.
The X-ray conversion layer 72 is a layer made of amorphous selenium, and is provided so as to cover the thin film transistor 1 and the capacitor 70.
The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

  As shown in FIG. 7, the X-ray sensor 7 of this embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that are parallel to each other and intersect the gate wiring 81. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate wiring 81 and the data wiring 82.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 1 is connected to a charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with a grounded counter electrode 76.

  In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper part (upper electrode 73 side) in FIG. 6, and electron-hole pairs are generated in the X-ray conversion layer 72. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 1.

  Since the X-ray sensor of the present invention includes the thin film transistor 1 having a high on-current, excellent in-plane uniformity and reliability, the S / N is high and suitable for a large screen. Moreover, since it has excellent sensitivity characteristics, an image with a wide dynamic range can be obtained when used in an X-ray digital imaging apparatus. In particular, the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when IGZO of the active layer in the thin film transistor is amorphous, an image with excellent uniformity can be obtained.

  The X-ray sensor of this embodiment shown in FIG. 6 is provided with a top gate type thin film transistor. However, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, but a bottom gate type. A thin film transistor may be used.

  Examples will be described below, but the present invention is not limited to these examples.

<Example 1>
The following samples were prepared and evaluated for the relationship between the annealing temperature and electrical characteristics of an oxide semiconductor film composed of three layers with different In: Ga ratios.
As the substrate, a synthetic quartz glass substrate (manufactured by Covalent Materials, product number T-4040) was used. A stacked film of oxide semiconductors was formed on the substrate in the following order.

-Film formation 1-
Cation composition ratio In: Ga: Zn = 0.5: 1.5: 1
Thickness 10nm
Deposition chamber ultimate vacuum 6 × 10 ⁻⁶ Pa
Deposition pressure 4.4 × 10 ⁻¹ Pa
Ar flow rate 30sccm
O ₂ flow rate 0.3 sccm

-Film formation 2-
Cation composition ratio In: Ga: Zn = 1.5: 0.5: 1
Thickness 5nm
Deposition chamber ultimate vacuum 6 × 10 ⁻⁶ Pa
Deposition pressure 4.4 × 10 ⁻¹ Pa
Ar flow rate 30sccm
O ₂ flow rate 0.6 sccm

-Film formation 3-
Cation composition ratio In: Ga: Zn = 0.5: 1.5: 1
Thickness 30nm
Deposition chamber ultimate vacuum 6 × 10 ⁻⁶ Pa
Deposition pressure 4.4 × 10 ⁻¹ Pa
Ar flow rate 30sccm
O ₂ flow rate 0.15 sccm

Films 1, 2, and 3 were continuously formed without being exposed to the air between each film formation. Sputtering of each layer (region) is performed by co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target, and the composition ratio is adjusted by changing the power ratio applied to each target It was done by letting. The thickness of each region was adjusted by adjusting the film formation time.

<Comparative Examples 1-5>
Different samples were prepared and evaluated in the same manner as in Example 1. For the samples of Comparative Examples 1 to 5, the composition ratio of the film and the oxygen flow rate at the time of film formation were changed. Neither modulation nor oxygen flow rate modulation during film formation is performed.

<Comparative Example 7>
Different samples were prepared and evaluated in the same manner as in Example 1. The sample of Comparative Example 7 was an oxide semiconductor film having a two-layer structure.

  Table 1 shows the composition ratio of each oxide semiconductor film and the oxygen gas flow rate (sccm) of the atmospheric gas in the above Examples and Comparative Examples.

(Annealing process)
Each sample was subjected to post-annealing treatment using an electric furnace capable of controlling the annealing atmosphere. The atmosphere in the chamber was an O ₂ atmosphere, and an As-depo film (no heat treatment), a 200 ° C. anneal film, and a 300 ° C. anneal film were prepared for each. The rate of temperature increase to the annealing temperature was 5 ° C./min, and the temperature was maintained at a predetermined temperature for 1 hour, and then cooled to room temperature by furnace cooling.

(Electrical characteristics evaluation)
Each sample subjected to the annealing treatment was subjected to the following electrical property evaluation after a four-terminal electrode was formed on the film surface.
FIG. 8 shows the specific resistance and carrier concentration for the manufactured Example 1 and Comparative Examples 1 to 5. A Hall measuring device (manufactured by Toyo Technica Co., Ltd., Hall effect / specific resistance measuring device Resi Test 8300) was used for the measurement. As shown in FIG. 8, even if the composition ratio and oxygen flow rate during film formation are changed in a single film, variation in specific resistance and carrier concentration due to annealing temperature cannot be suppressed, and the range from room temperature to 300 ° C. The specific resistance changed from 2 to 5 digits.
On the other hand, in Example 1, the specific resistance when annealing is performed in the range from room temperature to 300 ° C. is suppressed to within one digit by using a three-layer laminated structure in which the composition ratio or the oxygen flow rate during film formation is changed. Was made.

  In addition, as shown in FIG. 9, it can be seen that the change amount of the carrier concentration is reduced as the change amount of the specific resistance is reduced. Regarding the as-depo film of Comparative Example 3, the 300 ° C. annealed film, and the as-depo film of Comparative Example 5, the carrier concentration was too low to measure.

  Further, in Example 1, the evaluation result of the laminated structure in which both the composition ratio and the oxygen flow rate at the time of film formation were changed was shown, but even when the composition ratio and the oxygen flow rate at the time of film formation are individually modulated, the same results are obtained. The effect was obtained.

  On the other hand, Comparative Example 7 in which an oxide semiconductor film having a two-layer structure is formed has a large amount of change in specific resistance (see FIGS. 10 and 11) and is not suitable for increasing the area.

<Example 2>
A TFT element using an oxide semiconductor film composed of three layers with different In: Ga ratios was manufactured and evaluated. As shown in FIG. 12, a silicon oxide substrate with a thermal oxide film 100 nm in thickness was used as the substrate, and a simple element 110 using the thermal oxide film 102 as a gate insulating film was fabricated. After the oxide semiconductor laminated film 104 was formed on the substrate 100 in the same procedure as in Example 1, the same post-annealing process as in Example 1 was performed. The annealing temperature was 300 ° C.
After annealing, Ti-Au electrode (Ti: 106, Au: 108 ) was deposited, using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies), the transistor characteristics _(V g -I _d characteristics) and mobility μ Measurements were made. Measurement of V _g -I _d characteristics, the drain voltage _{(V d)} is fixed to 10V, the gate voltage _{(V g)} is changed within the range of -15V~ + 15V, the drain current at gate voltages _{(V g)} This was done by measuring (I _d ).

<Comparative Example 8>
An IGZO single-layer TFT element was produced and evaluated in the same manner as in Example 2. The IGZO film was formed under the conditions of Comparative Example 1.

The Vg-Id characteristics of Example 2 and Comparative Example 8 are shown in FIG. The TFT element of Example 2 had a linear mobility of 26 cm ² / Vs, whereas the TFT element of Comparative Example 8 had a linear mobility of 12 cm ² / Vs. From this result, it is understood that not only in-plane uniformity of device characteristics but also mobility can be obtained by using the method for manufacturing a thin film transistor of the present invention.

1, 2, 3, 4 Thin film transistor 11 Substrate 12 Oxide semiconductor layer 12A Oxide semiconductor layer first layer 12B Oxide semiconductor layer second layer 12C Oxide semiconductor layer third layer 13 Source electrode 14 Drain Electrode 15 Gate insulating film 16 Gate electrode

Claims (15)

A method of manufacturing a thin film transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode over a substrate,
Has a stacked structure including three or more layers having different compositions of the adjacent layers, and, located on the side closest to the gate electrode a gate recently layer and the farthest is located on the side gate farthest layer from the gate electrode between the gate recently layer and the gate resistivity is less than the farthest layer low-resistance layer is present at least one layer, wherein the gate recently layer, each layer of the gate farthest layer, and the low-resistance layer The step of forming an oxide semiconductor layer having a total thickness of 30 to 200 nm ,
Forming a heat treatment after forming the oxide semiconductor layer;
A method of manufacturing a thin film transistor including:   The method for manufacturing a thin film transistor according to claim 1, wherein the oxide semiconductor layer is formed in a three-layer structure.   The method for manufacturing a thin film transistor according to claim 1, wherein the oxide semiconductor layer is amorphous.   4. The method for manufacturing a thin film transistor according to claim 1, wherein each of the layers constituting the oxide semiconductor layer contains at least one element of In and Ga. 5. Each layer constituting the oxide semiconductor _{layer, a (In 2 O 3)} · b (Ga 2 O 3) · c according to any one of claims 1 to 4 is made of a (ZnO) Manufacturing method of the thin film transistor.
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.) The gate recent layer of b / (a + b) and the gate farthest layer b / (a + b) The method for producing a thin film transistor according the to claim 5 greater than the low-resistance layer b / (a + b). The gate bandgap recent layer bandgap and the gate farthest layer of the thin film transistor manufacturing method according to any one of the wider bandgap claims 2 6 in the low resistance layer.   The method for manufacturing a thin film transistor according to claim 1, wherein the heat treatment is performed in an oxidizing atmosphere.   The method for manufacturing a thin film transistor according to claim 1, wherein the heat treatment step is performed at a temperature of 100 ° C. or higher and 300 ° C. or lower.   The method for manufacturing a thin film transistor according to any one of claims 1 to 9, wherein the substrate has flexibility.   The thin-film transistor manufactured using the manufacturing method of the thin-film transistor as described in any one of Claims 1-10.   A display device comprising the thin film transistor according to claim 11.   An image sensor comprising the thin film transistor according to claim 11.   An X-ray sensor comprising the thin film transistor according to claim 11.   An X-ray digital imaging apparatus comprising the X-ray sensor according to claim 14.