JP5606003B2 - Display control device - Google Patents

Description

  The present invention relates to a display control apparatus capable of controlling display of a video by detecting an abnormality of a clock signal used for displaying the video.

  FIG. 1 is an example of an ASIC (Application Specific Integrated Circuit) 9 according to a conventional technique. The ASIC 9 is configured by a custom IC (Integrated Circuit) that controls image output to a TFT (Thin Film Transistor) liquid crystal display (hereinafter referred to as “TFT”) 2 and lighting of a backlight. The ASIC 9 includes a PLL (Phase Locked Loop) unit 11, a frequency dividing unit 12, an input I / F unit 13, a video processing unit 14, a TFT backlight control unit 15, and other control units 16.

  The PLL unit 11 receives an LVDS (Low Voltage Differential Signaling) clock signal, generates a 7-fold clock signal obtained by multiplying the LVDS clock signal by 7, and inputs the generated 7-fold clock signal to the input I / F unit 13 and the frequency dividing unit. 12 is supplied. The LVDS clock signal is a clock signal having a maximum frequency of, for example, 33.3 MHz, and is transmitted and received as an LVDS signal that is a differential signal. The frequency divider 12 generates a 7-divided clock signal obtained by dividing the 7-fold clock signal supplied from the PLL unit 11 by 7 and supplies the generated 7-divided clock signal to the video processor 14.

  The input I / F unit 13 receives an LVDS video data signal, captures video data from the input LVDS video data signal in synchronization with the 7-fold clock signal supplied from the PLL unit 11, and imports the video data Is sent to the video processing unit 14. The LVDS video data signal is a video data signal having a maximum frequency of, for example, 233 MHz, and is transmitted and received as an LVDS signal that is a differential signal. The video processing unit 14 performs processing for displaying the video data received from the input I / F unit 13 on the TFT 2, for example, processing such as contrast and gamma correction, and sends the processed video data to the TFT 2 for display.

  The TFT backlight control unit 15 controls lighting (hereinafter referred to as “ON”) and extinguishing (hereinafter referred to as “OFF”) of the backlight provided in the TFT 2. The other control unit 16 includes, for example, a touch SW (switch) processing unit and a TFT power supply control unit. The other control unit 16 includes a clock signal from the crystal oscillator 3 provided outside the ASIC 9, for example, a frequency of 5 MHz. A clock signal is supplied.

  FIG. 2 is a time chart for explaining the relationship between the LVDS clock signal and the operation of the PLL unit 11. The LVDS clock signal input to the ASIC 9 may not be output when an electronic device using the ASIC 9 is reset. In the example shown in FIG. 2, the output of the LVDS clock signal is stopped during the period from time t1 to time t2. The backlight is on during this period, but the PLL unit 11 is self-running during this period because the LVDS clock signal to be synchronized is not output. The free-running of the PLL unit 11 is to oscillate at a frequency determined by the circuit configuration of the PLL unit 11. The PLL unit 11 normally generates a 7-fold clock signal synchronized with the LVDS clock signal before time t1 and after time t2. If the PLL unit 11 is self-propelled, an abnormal image may be output to the TFT 2.

  A semiconductor device described in Patent Literature 1 includes a PLL (Phase Locked Loop) circuit that generates an internal clock signal from an external clock signal, and an external clock determination circuit that determines the presence or absence of the external clock signal. If it is determined that there is no external clock signal, the operation of the PLL circuit is stopped, or the output of the PLL circuit is stopped from propagating to the subsequent stage. The external clock determination circuit includes a counter that counts a clock output from an external oscillator that oscillates at a frequency higher than the frequency of the external clock signal, and resets the counter at the rising edge of the external clock signal. When the external clock signal disappears, the counter continues counting without being reset and exceeds a predetermined threshold value, so that the external clock determination circuit can determine that the external clock signal has disappeared.

  A synchronization signal monitoring device for a liquid crystal display described in Patent Document 2 monitors a synchronization signal from a host with a synchronization signal monitoring circuit, and transmits a stop signal to a buffer circuit and a power supply circuit when the synchronization signal is not detected. Shut off the power supply to the liquid crystal display and backlight. The synchronization signal monitoring circuit discharges the integration circuit at the rising edge of the synchronization signal. When the synchronization signal is no longer detected, the integration circuit is not discharged, the output of the integration circuit reaches a certain level, and a stop signal indicating that the synchronization signal has stopped is transmitted.

JP-A-6-187063 JP 2003-177721 A

  However, when it is determined that there is no external clock signal, the semiconductor device according to Patent Document 1 stops the operation of the PLL circuit or stops the output of the PLL circuit from propagating to the subsequent stage. Nothing is disclosed about the influence on the circuit and the countermeasures. The synchronization signal monitoring device for a liquid crystal display according to Patent Document 2 transmits a stop signal to the buffer circuit and the power supply circuit when the synchronization signal is not detected, thereby shutting off the power supply to the liquid crystal display and the backlight. However, the timing for shutting off the power supply to the liquid crystal display and the backlight and the timing for turning on the power are not disclosed. For example, if the power supply of the liquid crystal display is turned off and then the power supply of the backlight is turned off, the entire screen becomes a white screen, and there is a possibility that burning will occur.

  An object of the present invention is to provide a display control device capable of appropriately controlling the on / off timing of a liquid crystal display and a backlight when output of a clock signal is stopped and output is restarted.

The present invention (1) includes a backlight turn-on reference value for determining when to turn on a backlight provided in a display unit for displaying video, a backlight turn-off reference value for determining timing for turning off the backlight, A first clock signal used when converting input video data into video data to be displayed on the display unit is generated based on a second clock signal that oscillates at a predetermined first frequency. A clock generation start reference value for determining the timing of starting the operation of one clock generation unit, which is smaller than the backlight lighting reference value, and the operation of the first clock generation unit Clock generation stop reference value for determining when to stop the clock, which is larger than the backlight extinction reference value A storage unit for storing the formed stop reference value,
A monitoring unit,
A first counter that counts a third clock signal that oscillates at a frequency different from the frequency of the second clock signal, outputs a first count value, and resets the first count value by a first reset signal;
A second counter that counts a third clock signal to output a second count value and resets the second count value by a second reset signal;
The comparison result between the first count value and the backlight extinction reference value stored in the storage unit, the comparison result between the first count value and the clock generation stop reference value, the second count value and the clock generation start reference value, And a control unit for controlling the turning-off and lighting of the backlight and the stop and start of the operation of the first clock generation unit based on the comparison result of the second and the comparison result between the second count value and the reference value for lighting the backlight, Have
The first reset signal is a second clock signal,
The second reset signal is a signal representing a comparison result between the first count value and the backlight extinction reference value,
The control unit turns off the backlight when the first count value reaches the reference value for turning off the backlight, and then operates the first clock generation unit when the first count value reaches the reference value for stopping clock generation. When the second count value reaches the reference value for starting clock generation, the operation of the first clock generation unit is started. After that, when the second count value reaches the reference value for lighting the backlight, the backlight is started. And a monitoring unit that lights up the display control device.

According to the first aspect of the present invention, the storage unit uses the storage unit to determine the backlight lighting reference value for determining the timing for turning on the backlight provided in the display unit for displaying the video, and the backlight for determining the timing for turning off the backlight. A second clock signal for oscillating a first clock signal used for converting the reference value for turning off the light and the input video data into video data to be displayed on the display unit at a predetermined first frequency. A clock generation start reference value for determining the timing to start the operation of the first clock generation unit that is generated based on the clock generation start reference value that is smaller than the backlight lighting reference value, and the first Is a reference value for stopping clock generation for determining the timing to stop the operation of the clock generator of Big clock generation stop reference value is stored than. When the monitoring result output by the monitoring unit is a result of outputting the second clock signal, the control unit determines that the backlight is turned off when the count value output by the monitoring unit reaches the reference value for turning off the backlight. Then, when the count value output by the monitoring unit reaches the reference value for stopping clock generation, the operation of the first clock generation unit is stopped. In addition, when the monitoring result output by the monitoring unit is a result in which the second clock signal is not output, when the count value output by the monitoring unit reaches the reference value for starting clock generation, The operation of one clock generation unit is started, and then the backlight is turned on when the count value output by the monitoring unit reaches the backlight lighting reference value.
In this manner, the control unit outputs the backlight lighting reference value, the backlight turn-off reference value, the clock generation start reference value, and the clock generation stop reference stored in the storage unit as the count value output by the monitoring unit. Based on whether or not each reference value has been reached, the backlight is turned off and on, and the operation of the first clock generator is stopped and started.

  Therefore, when the output of the second clock signal is stopped and resumed, the on / off timing of the display unit, for example, the liquid crystal display and the backlight can be appropriately controlled, and the display of a white screen on the liquid crystal display is avoided. It can prevent the burning of the liquid crystal display.

It is an example of ASIC9 by a prior art. 6 is a time chart for explaining a relationship between an LVDS clock signal and an operation of a PLL unit 11; It is a block diagram which shows the structure of ASIC1 including the LVDS oscillation control circuit 20 which is one Embodiment of this invention. 3 is a block diagram illustrating a configuration of a pulse determination unit 22. FIG. 3 is a time chart showing timings of input / output signals of a pulse generation unit 21. 3 is a time chart showing timings of input / output signals of a pulse determination unit 22; It is a block diagram which shows the structure of ASIC1a containing the LVDS oscillation control circuit 20a which is the other form of implementation of this invention. 4 is a time chart showing timings at which an external memory read unit 24 operates. It is a block diagram which shows the structure of ASIC1b containing the LVDS oscillation control circuit 20b which is the further another form of implementation of this invention. 4 is a time chart showing timings at which an external memory read unit 24 and a reference value correction unit 25 operate.

  FIG. 3 is a block diagram showing a configuration of an ASIC (Application Specific Integrated Circuit) 1 including the LVDS oscillation control circuit 20 according to the embodiment of the present invention. The ASIC 1 is a custom IC (Integrated Circuit) that controls video output to a TFT (Thin Film Transistor) liquid crystal display (hereinafter referred to as “TFT”) 2 and lighting of a backlight (not shown) provided in the TFT 2 that is a display unit. A PLL (Phase Locked Loop) unit 11, a frequency dividing unit 12, an input I / F unit 13, a video processing unit 14, a TFT backlight control unit 15, and an LVDS oscillation control circuit 20.

  The PLL unit 11 as the first clock generation unit receives an LVDS (Low Voltage Differential Signaling) clock signal, generates a 7-fold clock signal obtained by multiplying the LVDS clock signal by 7, and inputs the generated 7-fold clock signal as an input I. / F unit 13 and frequency divider 12 are supplied. The 7-fold clock signal is the first clock signal. The LVDS clock signal, which is the second clock signal, is a clock signal having a predetermined first frequency, for example, a maximum of 33.3 MHz, and is transmitted and received as a LVDS signal, which is a differential signal. The frequency divider 12 generates a 7-divided clock signal obtained by dividing the 7-fold clock signal supplied from the PLL unit 11 by 7 and supplies the generated 7-divided clock signal to the video processor 14.

  The input I / F unit 13 receives an LVDS video data signal, captures video data from the input LVDS video data signal in synchronization with the 7-fold clock signal supplied from the PLL unit 11, and imports the video data Is sent to the video processing unit 14. The LVDS video data signal is a video data signal having a maximum frequency of, for example, 233 MHz, and is transmitted and received as an LVDS signal that is a differential signal. The video processing unit 14 performs processing for displaying the video data received from the input I / F unit 13 on the TFT 2, for example, processing such as contrast and gamma correction, and sends the processed video data to the TFT 2 for display.

  The TFT backlight control unit 15 controls lighting (hereinafter referred to as “ON”) and extinguishing (hereinafter referred to as “OFF”) of the backlight provided in the TFT 2. The other control unit 16 includes, for example, a touch SW (switch) processing unit and a TFT power supply control unit. The other control unit 16 includes a clock signal from the crystal oscillator 3 provided outside the ASIC 9, for example, a frequency of 5 MHz. A certain 5 MHz clock signal is supplied.

  The LVDS oscillation control circuit 20, which is a display control device, includes a 2 ms periodic pulse generation unit (hereinafter referred to as “pulse generation unit”) 21, 2 ms pulse detection and determination unit (hereinafter referred to as “pulse determination unit”) 22, and a reference value storage unit 23. The pulse generation unit 21 divides the LVDS clock signal to generate a 2 ms pulse signal with a 2 ms period, and sends the generated 2 ms pulse signal to the pulse determination unit 22. The period is not necessarily 2 ms.

The pulse determination unit 22 counts the number of clocks of the 5 MHz clock signal from the crystal oscillator 3 (hereinafter referred to as “count”), and compares the counted value with a reference value stored in the reference value storage unit 23. It monitors whether the LVDS clock signal is being output. The 5 MHz clock signal is a third clock signal. The pulse determination unit 22 controls a PLL stop / operation signal to be sent to the PLL unit 11 and a backlight ON / OFF instruction signal to be sent to the TFT backlight control unit 15 based on the monitoring result. The pulse generation unit 21 and the pulse determination unit 22 constitute a monitoring unit.

  When the PLL stop / operation signal is at a high level, the PLL unit 11 is instructed to operate, and when at a low level, the PLL unit 11 is instructed to stop its operation. The backlight ON / OFF instruction signal instructs to turn on the backlight when it is at a high level, and instructs to turn off the backlight when it is at a low level.

  The PLL unit 11 generates and outputs a 7-fold clock signal when the PLL stop / operation signal is at a high level, and stops generating the 7-fold clock signal when the PLL stop / operation signal is at a low level. The TFT backlight control unit 15 turns on the backlight when the backlight ON / OFF instruction signal is at a high level, and turns off the backlight when the backlight ON / OFF instruction signal is at a low level.

  The reference value storage unit 23 which is a storage unit is configured by a read-only nonvolatile memory such as a PROM (Programmable Read Only Memory), for example, and includes a backlight ON reference value, a backlight OFF reference value, and a PLL operation start reference. The four reference values of the value and the reference value for stopping the PLL are stored.

  The backlight ON reference value, which is the backlight lighting reference value, is a reference value for determining the timing of lighting the backlight. The backlight OFF reference value, which is the reference value for turning off the backlight, is a reference value for determining the timing for turning off the backlight. The reference value for starting the PLL operation, which is a reference value for starting clock generation, is a reference value for determining the timing for starting the operation of the PLL unit 11, and is smaller than the reference value for turning on the backlight. The PLL stop reference value, which is a clock generation stop reference value, is a reference value for determining the timing at which the operation of the PLL unit 11 is stopped, and is larger than the backlight OFF reference value.

  FIG. 4 is a block diagram illustrating a configuration of the pulse determination unit 22. The pulse determination unit 22 includes a first counter 220, a second counter 221, a first comparator 222, a second comparator 223, a third comparator 224, a fourth comparator 225, and a first flip-flop (hereinafter referred to as “FF”). ) 226 and the second FF 227.

  The first counter 220 receives the 5 MHz clock signal from the crystal oscillator 3 at the clock terminal CK, the 2 ms pulse signal from the pulse generator 21 to the reset terminal R, and outputs the first comparator 222 and the second comparison signal. Connected to the non-inverting input terminal of the device 223. The first counter 220 counts the number of clocks of the 5 MHz clock signal and resets the counted value when the 2 ms pulse signal changes, that is, every 1 ms.

  In the second counter 221, the 5 MHz clock signal from the crystal oscillator 3 is input to the clock terminal CK, the output of the second comparator 223 is input to the reset terminal R, and the outputs are the third comparator 224 and the fourth comparator 225. Connected to the non-inverting input terminal. The second counter 221 counts the number of clocks of the 5 MHz clock signal, and resets the counted value when the output of the second comparator 223 becomes high level. The output of the second comparator 223 becomes high level when the value counted by the first counter 220 is greater than or equal to the backlight OFF reference value.

The first comparator 222 to the fourth comparator 225 are constituted by, for example, comparators. In the first comparator 222, the output of the first counter 220 is connected to the non-inverting input terminal, the PLL stop reference value stored in the reference value storage unit 23 is input to the inverting input terminal, and the output is reset to the second FF 227. Connected to terminal R. In the second comparator 223, the output of the first counter 220 is connected to the non-inverting input terminal, the backlight OFF reference value stored in the reference value storage unit 23 is input to the inverting input terminal, and the output is the first FF 226. It is connected to the reset terminal R.
In the third comparator 224, the output of the second counter 221 is connected to the non-inverting input terminal, the PLL operation start reference value stored in the reference value storage unit 23 is input to the inverting input terminal, and the output is the second FF 227. Connected to the set terminal S. In the fourth comparator 225, the output of the second counter 221 is connected to the non-inverting input terminal, the backlight ON reference value stored in the reference value storage unit 23 is input to the inverting input terminal, and the output terminal is the first FF 226. Are connected to the set terminal S.

  The first comparator 222 outputs a high-level signal when the output of the first counter 220, that is, the value counted by the first counter 220 is equal to or greater than the reference value for stopping the PLL, and when the output becomes less than the reference value for stopping the PLL. Output a low level signal. The second comparator 223 outputs a high level signal when the value counted by the first counter 220 is greater than or equal to the backlight OFF reference value, and when the value is less than the backlight OFF reference value, the second comparator 223 outputs a low level signal. Output a signal. The third comparator 224 outputs a high level signal when the value counted by the second counter 221 is equal to or greater than the reference value for starting the PLL operation, and outputs a low level signal when the value is less than the reference value for starting the PLL operation. Output. The fourth comparator 225 outputs a high level signal when the value counted by the second counter 221 exceeds the backlight ON reference value, and outputs a low level signal when the value is less than the backlight ON reference value. Output.

  The first FF 226 and the second FF 227 are set-reset type flip-flops. In the first FF 226, the output of the fourth comparator 225 is connected to the set terminal S, and the output of the second comparator 223 is connected to the reset terminal R. In the second FF 227, the output of the third comparator 224 is connected to the set terminal S, and the output terminal of the first comparator 222 is connected to the reset terminal R.

  The first FF 226 outputs a high-level backlight ON / OFF instruction signal when the output of the fourth comparator 225 becomes high level, that is, when the value counted by the second counter 221 exceeds the backlight ON reference value. When the output of the second comparator 223 becomes high level, that is, when the value counted by the first counter 220 becomes equal to or higher than the backlight OFF reference value, a low level backlight ON / OFF instruction signal is output. The second FF 227 outputs a high-level PLL stop / operation signal when the output of the third comparator 224 becomes high level, that is, when the value counted by the second counter 221 exceeds the reference value for starting PLL operation, When the output of the first comparator 222 becomes high level, that is, when the value counted by the first counter 220 becomes equal to or higher than the PLL stop reference value, a low level PLL stop / operation signal is output. The first comparator 222 to the fourth comparator 225, and the first FF 226 and the second FF 227 are control units.

  FIG. 5 is a time chart showing the timing of the input / output signals of the pulse generator 21. The pulse generator 21 divides the input LVDS clock signal to generate and output a 2 ms pulse signal having a 2 ms period. The 2 ms pulse signal has a half cycle of 1 ms, for example. When the output of the LVDS clock signal stops at time t1, the pulse generator 21 stops outputting the 2 ms pulse signal. In the example shown in FIG. 5, the output of the 2 ms pulse signal is stopped at the high level during the period when the output is stopped at the low level of the LVDS clock signal. When the output of the LVDS clock signal is resumed at time t2, the output of the 2 ms pulse signal is also resumed.

FIG. 6 is a time chart showing the timing of the input / output signals of the pulse determination unit 22. Prior to time t1, a 2 ms pulse signal is output, and the first counter 220 counts the number of clocks of the 5 MHz clock signal, but is reset every time the 2 ms pulse signal changes. At this time, since the LVDS clock signal is output, the PLL unit 11 continues to operate.

  When the output of the LVDS clock signal stops at time t1, the output of the 2 ms pulse signal also stops, so the first counter 220 continues counting without being reset. When the value of the first counter 220 reaches the backlight OFF reference value at time t11, the first FF 226 is reset by the second comparator 223, and the backlight ON / OFF instruction signal becomes low level. When the backlight ON / OFF instruction signal becomes low level, the TFT backlight control unit 15 turns off the backlight. The backlight ON / OFF instruction signal is a backlight OFF instruction when it is at a low level, and is a backlight ON instruction when it is at a high level.

  When the first counter 220 continues counting and the value of the first counter 220 reaches the PLL stop reference value at time t12, the second FF 227 is reset by the first comparator 222, and the PLL drive / stop signal becomes low. Become a level. When the PLL drive / stop signal becomes low level, the PLL unit 11 stops its operation. When the PLL drive / stop signal is at a low level, it indicates a PLL stop, and when the PLL drive / stop signal is at a high level, it indicates a PLL operation.

  During the period from the time when the output of the LVDS clock signal is stopped at time t1 to the time t12 when the operation of the PLL unit 11 is stopped, the PLL unit 11 runs free because there is no signal for synchronization. The frequency at which the PLL unit 11 runs is changed from a frequency synchronized with the LVDS clock signal to a frequency determined by the circuit configuration of the PLL unit 11. Since the time from time t1 to time t12 is short, at the time t12, the frequency at which the PLL unit 11 runs is almost the same as the frequency when synchronized with the LVDS clock signal, and the video output to the TFT 2 There will be no abnormality.

  The second counter 221 is reset when the output of the second comparator 223 is at a high level, and counts when the output is at a low level. When the value of the first counter 220 reaches the backlight OFF reference value at time t11, the output of the second comparator 223 becomes high level, so the second counter 221 is reset. Thereafter, when the output of the LVDS clock signal is resumed, the output of the 2 ms pulse signal is also resumed, and the first counter 220 is reset at time t2 when the 2 ms pulse signal changes. When the first counter 220 is reset, the value of the first counter 220 becomes less than the reference value for backlight OFF, so the output of the second comparator 223 becomes low level, and the second counter 221 receives the 5 MHz clock signal. Start counting the number of clocks.

  When the value of the second counter 221 reaches the PLL operation start reference value at time t21, the second FF 227 is set, and the PLL drive / stop signal becomes high level. When the PLL drive / stop signal becomes high level, the PLL unit 11 resumes operation. When the second counter 221 continues counting and the value of the second counter 221 reaches the backlight ON reference value at time t22, the first FF 226 is set and the backlight ON / OFF instruction signal becomes high level. . When the backlight ON / OFF instruction signal becomes high level, the TFT backlight control unit 15 turns on the backlight.

  FIG. 7 is a block diagram showing a configuration of an ASIC 1a including an LVDS oscillation control circuit 20a according to another embodiment of the present invention. The ASIC 1a is a custom IC that controls video output to the TFT 2 and lighting of the backlight provided in the TFT 2, and includes a PLL unit 11, a frequency dividing unit 12, an input I / F unit 13, a video processing unit 14, and a TFT backlight control. Part 15 and an LVDS oscillation control circuit 20a. Among the components of the ASIC 1a and the LVDS oscillation control circuit 20a, the same components as those of the ASIC 1 and the LVDS oscillation control circuit 20 shown in FIG. Omitted.

  The LVDS oscillation control circuit 20a, which is a display control device, includes a pulse generation unit 21, a pulse determination unit 22a, a reference value storage unit 23a, and an external memory read unit 24. The reference value storage unit 23a, which is a storage unit, is configured by a writable and readable memory such as a RAM (Random Access Memory), for example, and stores four reference values read from the external memory 4 by the external memory read unit 24. Remember. The four reference values are the same reference values as the backlight ON reference value, the backlight OFF reference value, the PLL operation start reference value, and the PLL stop reference value stored in the reference value storage unit 23 shown in FIG. It is.

  The external memory 4 that is an external storage device is configured by, for example, a flash memory or an EEPROM (Electrically Erasable Programmable Read Only Memory), and stores these four reference values. These four reference values do not necessarily have to be stored in the external memory 4, and may be configured such that the external memory read unit 24 can access and take in the four reference values. For example, another device having a microcomputer stores four reference values, the microcomputer of the other device communicates with the external memory read unit 24, and the external memory read unit 24 obtains four reference values from the microcomputer. May be.

  When the ASIC reset signal is canceled, the external memory read unit 24 serving as a reading unit reads the four reference values stored in the external memory 4 and writes the read four reference values into the reference value storage unit 23a. The ASIC reset signal is a signal output for resetting the ASIC 1a immediately after the power is turned on. When the ASIC reset signal is canceled, the ASIC 1a starts operation. The pulse determination unit 22 shown in FIG. 3 starts to operate when the ASIC reset signal is released, but the pulse determination unit 22a receives a pulse monitoring signal (hereinafter referred to as “dotclk monitoring signal”) from the external memory read unit 24. When is output, the operation starts. The dotclk monitoring signal is output when the external memory read unit 24 reads the four reference values from the external memory 4 and finishes writing the read four reference values to the reference value storage unit 23a.

  FIG. 8 is a time chart showing the timing at which the external memory read unit 24 operates. When the ASIC reset signal is canceled at time t3, the external memory read unit 24 reads the four reference values from the external memory 4, and performs an external memory read operation for writing the read four reference values to the reference value storage unit 23a. . When the external memory read operation is finished at time t4, the external memory read unit 24 sends a dotclk monitoring signal to the pulse determination unit 22a, and causes the pulse determination unit 22a to start monitoring whether or not the LVDS clock signal is output. .

  Since the pulse determination unit 22a performs monitoring based on the four reference values read from the external memory 4 to the reference value storage unit 23a, the characteristics of the PLL unit 11 included in the ASIC 1a, for example, the operation is stopped before the operation is stopped. It is possible to set a reference value in accordance with characteristics such as a lock period until restart and characteristics of the TFT 2 connected to the ASIC 1a, for example, characteristics such as time required to turn on and off the backlight.

  FIG. 9 is a block diagram showing a configuration of an ASIC 1b including an LVDS oscillation control circuit 20b according to still another embodiment of the present invention. The ASIC 1b is a custom IC that controls video output to the TFT 2 and lighting of the backlight provided in the TFT 2, and includes a PLL unit 11, a frequency dividing unit 12, an input I / F unit 13, a video processing unit 14, and a TFT backlight control. Part 15 and an LVDS oscillation control circuit 20b. Among the components of the ASIC 1b and the LVDS oscillation control circuit 20b, the same components as those of the ASIC 1a and the LVDS oscillation control circuit 20a shown in FIG. Omitted.

  The LVDS oscillation control circuit 20b, which is a display control device, includes a pulse generation unit 21, a pulse determination unit 22a, a reference value storage unit 23a, an external memory read unit 24a, and a reference value correction unit 25. When the ASIC reset signal is canceled, the external memory read unit 24a serving as a reading unit reads the four reference values stored in the external memory 4 and sends the read four reference values to the reference value correction unit 25.

  The reference value correction unit 25, which is a correction unit, determines whether or not the four reference values received from the external memory read unit 24a satisfy a predetermined relationship. The predetermined relationship is that the PLL operation start reference value is smaller than the backlight ON reference value, and the PLL stop reference value is larger than the backlight OFF reference value.

  When the four reference values received from the external memory read unit 24a satisfy a predetermined relationship, the reference value correction unit 25 directly uses the four reference values received from the external memory read unit 24a as the reference value storage unit 23a. Write to. When the four reference values received from the external memory read unit 24a do not satisfy the predetermined relationship, the four reference values are corrected to satisfy the predetermined relationship, and the corrected four reference values are used as the reference value storage unit. Write to 23a. The reference value correction unit 25 writes the four reference values in the reference value storage unit 23a, and then outputs a dotclk monitoring signal to the pulse determination unit 22a.

  When the reference value for starting the PLL operation is not smaller than the reference value for turning on the backlight, for example, the reference value for starting the PLL operation is changed without changing the reference value for turning on the backlight. The time from when the backlight ON / OFF instruction signal changes from the high level to the low level until the PLL drive / stop signal changes from the high level to the low level is larger than the backlight ON reference value. 6 is corrected to a value that is the time from time t11 to time t12 in the time chart shown in FIG. Alternatively, the backlight ON reference value may be corrected so as to satisfy the above-described relationship without changing the PLL operation start reference value.

  When the reference value for stopping the PLL is not larger than the reference value for turning off the backlight, for example, without changing the reference value for stopping the PLL, the reference value for turning off the backlight is larger than the reference value for stopping the PLL, and The time from when the backlight ON / OFF instruction signal changes from low level to high level until the PLL drive / stop signal changes from low level to high level is shown in the time chart of FIG. 6 from time t21 to time t22. It corrects to the value which becomes time until. Alternatively, the reference value for stopping the PLL may be corrected so as to satisfy the above-described relationship without changing the reference value for backlight OFF.

  FIG. 10 is a time chart showing timings at which the external memory read unit 24a and the reference value correction unit 25 operate. When the ASIC reset signal is released at time t3, the external memory read unit 24a reads the four reference values from the external memory 4 and sends the read four reference values to the reference value correction unit 25. When the reference value correction unit 25 has received four reference values from the external memory read unit 24a at time t4, the reference value correction unit 25 determines whether the four reference values need to be corrected.

  When the reference value correction unit 25 determines that correction is necessary, the reference value correction unit 25 corrects the four reference values, writes the four reference values after correction to the reference value storage unit 23a, and then, at time t5, dotclk. The monitoring signal is output to the pulse determination unit 22a. When it is determined that correction is not necessary, the four reference values received from the external memory read unit 24a are written in the reference value storage unit 23a without correction, and then a dotclk monitoring signal is output to the pulse determination unit 22a.

  When the four reference values received from the external memory read unit 24a do not satisfy the predetermined relationship, the reference value correction unit 25 corrects the four reference values so as to satisfy the predetermined relationship, and stores the reference value. Since the data is written in the unit 23a, it is possible to prevent a white image or an abnormal image from being output to the TFT 2 even if there is a mistake in setting the four reference values in the external memory 4.

As described above, the reference value storage unit 23 uses the backlight ON reference value for determining the timing for turning on the backlight provided in the TFT 2 for displaying an image, and the backlight OFF for determining the timing for turning off the backlight. A PLL unit that generates a 7-fold clock signal used when converting the reference value and input video data into video data to be displayed on the TFT 2 based on the LVDS clock signal oscillated at a predetermined first frequency 11 is a reference value for starting the PLL operation for determining the timing for starting the operation of 11, which is a reference value for starting the PLL operation that is smaller than the reference value for turning on the backlight, and the timing for stopping the operation of the PLL unit 11. PLL stop reference value, which is larger than the backlight OFF reference value L stop reference value is stored. The pulse generation unit 21 and the pulse determination unit 22 monitor the LVDS clock signal based on a 5 MHz clock signal that oscillates at a frequency different from the frequency of the LVDS clock signal. Then, the backlight ON reference value, the backlight OFF reference value, and the PLL operation start reference stored in the reference value storage unit 23 by the first comparator 222 to the fourth comparator 225, and the first FF 226 and the second FF 227. It is determined whether the LVDS clock signal is output by comparing the value and the PLL stop reference value with the monitoring results by the pulse generator 21 and the pulse determination unit 22, and based on the determination result, the backlight The extinction and lighting, and the stop and start of the operation of the PLL unit 11 are controlled.

Therefore, when the output of the LVDS clock signal is stopped and the output is restarted, the on / off timing of the TFT 2 and the backlight can be properly controlled, and a white screen is prevented from being displayed on the TFT 2, and the burning of the TFT 2 is prevented. Can do.
Further, when the first comparator 222 to the fourth comparator 225 and the first FF 226 and the second FF 227 indicate that the LVDS clock signal is not output, the backlight is turned off. After the operation of the PLL unit 11 is stopped, after the operation of the PLL unit 11 is stopped and the operation of the PLL unit 11 is stopped, the determination result indicates that the LVDS clock signal is output. The backlight is turned on. Therefore, since the operation of the PLL unit 11 is stopped before the PLL unit 11 self-runs at a frequency at which an abnormal video is output, it is possible to prevent an abnormal video from being output. Power consumption due to running oscillation can be reduced. Further, the backlight is turned off before the operation of the PLL unit 11 is stopped, and the operation of the PLL unit 11 is restarted before the backlight is turned on. Is displayed, it is possible to avoid displaying a white image on the TFT 2 and to prevent burning of the TFT 2.

  Further, information stored in the external memory 4 is read by the external memory read unit 24, and the read information is stored in the reference value storage unit 23a. The backlight ON reference value, the backlight OFF reference value, the PLL operation start reference value, and the PLL stop reference value stored in the reference value storage unit 23a are read from the external memory 4 by the external memory read unit 24. Information. Therefore, characteristics of the PLL unit 11 to be used, such as characteristics such as a lock period from when the operation is stopped to when the operation is restarted, and characteristics of TFTs to be connected, such as time required for turning on and off the backlight, etc. It is possible to set a reference value according to the characteristics from the outside.

  Further, the reference value correction unit 25 reads the backlight ON reference value, the backlight OFF reference value, the PLL operation start reference value to be read by the external memory read unit 24a and stored in the reference value storage unit 23b, and When the four reference values consisting of the reference values for stopping the PLL are smaller than the reference value for turning on the backlight and the reference value for stopping the PLL is larger than the reference value for turning off the backlight, the reference for starting the PLL operation One of the four reference values is corrected so as to satisfy the relationship that the value is smaller than the backlight ON reference value and the PLL stop reference value is larger than the backlight OFF reference value. The four reference values are stored in the reference value storage unit 23b.

  Therefore, even if the reference value set from the outside does not satisfy the condition that the operation of the PLL unit 11 is stopped after the backlight is turned off and the backlight is turned on after the operation of the PLL unit 11 is resumed, the reference value is met. Since the reference value is corrected as described above, it is possible to prevent an abnormal image from being output and a white image from being displayed even if the reference value set in the external memory 4 has a mistake.

1,1a, 1b, 9 ASIC
2 TFT
3 Crystal oscillator 4 External memory 11 PLL unit 12 Dividing unit 13 Input I / F unit 14 Video processing unit 15 TFT backlight control unit 16 Other control unit 20, 20a, 20b LVDS oscillation control circuit 21 Pulse generation unit 22, 22a Pulse Determination unit 23, 23a Reference value storage unit 24, 24a External memory read unit 25 Reference value correction unit 220 First counter 221 Second counter 222-225 First to fourth comparators 226, 227 First, second FF

Claims (3)

A reference value for turning on the backlight for deciding the timing for turning on the backlight provided in the display unit for displaying the video, a reference value for turning off the backlight for deciding the timing for turning off the backlight, and input video data, Operation of a first clock generation unit that generates a first clock signal used when converting into video data to be displayed on the display unit based on a second clock signal that oscillates at a predetermined first frequency Clock generation start reference value for determining the timing to start the clock, and to determine the clock generation start reference value smaller than the backlight lighting reference value and the timing to stop the operation of the first clock generation unit Clock generation stop reference value that is greater than the backlight turn-off reference value A storage unit for storing to,
A monitoring unit,
A first counter that counts a third clock signal that oscillates at a frequency different from the frequency of the second clock signal, outputs a first count value, and resets the first count value by a first reset signal;
A second counter that counts a third clock signal to output a second count value and resets the second count value by a second reset signal;
The comparison result between the first count value and the backlight extinction reference value stored in the storage unit, the comparison result between the first count value and the clock generation stop reference value, the second count value and the clock generation start reference value, And a control unit for controlling the turning-off and lighting of the backlight and the stop and start of the operation of the first clock generation unit based on the comparison result of the second and the comparison result of the second count value and the reference value for lighting the backlight Have
The first reset signal is a second clock signal,
The second reset signal is a signal representing a comparison result between the first count value and the backlight extinction reference value,
The control unit turns off the backlight when the first count value reaches the reference value for turning off the backlight, and then operates the first clock generation unit when the first count value reaches the reference value for stopping clock generation. When the second count value reaches the reference value for starting clock generation, the operation of the first clock generation unit is started. After that, when the second count value reaches the reference value for lighting the backlight, the backlight is started. A display control device comprising: a monitoring unit that lights up . It further includes a reading unit that reads information stored in the external storage device and stores the read information in the storage unit,
The backlight lighting reference value, backlight extinction reference value, clock generation start reference value, and clock generation stop reference value stored in the storage unit are information read from the external storage device by the reading unit. The display control apparatus according to claim 1 . Four reference values consisting of a reference value for lighting the backlight, a reference value for turning off the backlight, a reference value for starting clock generation, and a reference value for stopping clock generation are to be read by the reading unit and stored in the storage unit. When the reference value for starting clock generation is smaller than the reference value for turning on the backlight and the reference value for stopping clock generation is not larger than the reference value for turning off the backlight, the reference value for starting clock generation is One of the four reference values is corrected to satisfy the relationship that the reference value for stopping the light generation is smaller than the reference value for turning on the light and the reference value for stopping the clock generation is larger than the reference value for turning off the backlight. The display control apparatus according to claim 2 , further comprising a correction unit that stores one reference value in the storage unit.

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