JP5601860B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a test circuit that generates a test signal for adjusting the operation of an internal circuit.

  As semiconductor elements are miniaturized, fluctuations in electrical characteristics received by the semiconductor elements due to manufacturing variations are increasing. Therefore, there is an increasing need to generate a test signal by a test circuit provided in the semiconductor device and adjust the operation of the internal circuit based on the test result. For example, the test circuit generates a test signal for operation adjustment, and optimizes the internal power supply voltage and the internal signal timing. In addition, a test signal is generated by a test circuit, and an internal power supply voltage and internal signal timing are adjusted so as to reduce an operation margin of the internal circuit, thereby revealing a malfunction of the semiconductor device, and a semiconductor device having a small operation margin. Deterioration is performed.

  For example, Patent Document 1 discloses a semiconductor device including a test circuit that generates a plurality of test signals.

Japanese Patent Laid-Open No. 2001-243796

However, the conventional semiconductor device such as the semiconductor device disclosed in Patent Document 1 has the following problems.
6 and 7 are drawings created by the inventor of the present application in order to explain problems in a semiconductor device having a conventional test circuit. FIG. 6 is a circuit block diagram showing a portion related to generation of a test signal in the semiconductor device 900. FIG. 7 is a layout drawing of the semiconductor device 900.
In the conventional semiconductor device 900 shown in FIG. 6, the address latch 105 latches a test code (address signal address) by a test command signal TRS generated from the command decoder 102 during a test operation. The address latch 105 also outputs the latched test address signal TA (m bits) to the DFT decoder 202 (Design For Test Decoder) via the address predecoder 201.
Then, the DFT decoder 202 decodes the pre-decoded test pre-address signal TPA (k signals) and outputs desired test signals DFT0 to DTFn. In addition, the DFT decoder 202 outputs the test signals DFT0 to DFTn to a target circuit (Ckt. A or the like) controlled in the test through a dedicated wiring provided for each test signal. Here, since there are as many test signals DFTn as the number of tests for adjusting the circuit to be controlled, the number of dedicated wirings may be about 200 as shown in FIG. 7, for example.

  As described above, in the semiconductor device including the conventional test circuit, the DFT decoder 202 and the target circuit are connected by the dedicated wiring provided for each test signal, so that the number of target circuits controlled in the test increases. Along with this, the number of dedicated wires increases and a large wiring area is required. For example, in a DDR3-SDRAM representing a semiconductor device, there are hundreds of target circuits to be controlled in a test, and the number of wirings provided for each test signal is hundreds. For this reason, in a semiconductor chip, a region (wiring region) used for test signal wiring occupies a large portion of the chip size. In other words, in a semiconductor device equipped with a conventional test circuit, there is a problem that the chip size is increased due to an increase in the wiring area, and an increase in the test signal is an obstacle to reducing the chip size. was there.

  The present invention is connected to a decoder for activating a predetermined first test signal indicated by the test code signal among a plurality of first test signals in response to a test code signal supplied from the outside, A first register that receives a plurality of first test signals supplied in parallel from a decoder and outputs the plurality of first test signals in series as a plurality of second test signals; A second register unit connected to receive a plurality of second test signals supplied in series from the first register unit and to output the plurality of second test signals in parallel as a plurality of third test signals; The plurality of third test signals connected to the second register unit and supplied in parallel from the second register unit are received, and the operation of the memory cell array is controlled according to the plurality of third test signals. And control unit, which is a semiconductor device, characterized in that it comprises a.

  According to the present invention, the decoder activates one of the plurality of first test signals, and the activated test signal is input to one of the plurality of first registers and activated. The test signals are sequentially transferred in a plurality of first registers and a plurality of second registers connected to a plurality of control circuits each controlling the operation of the memory cell array. As a result, the decoder that activates the test signal controls the data transmission signal between the first and second registers and the first and second registers, which are sent to the control unit that controls the operation of the memory cell array. Therefore, the number of test signal wirings can be greatly reduced as compared with the prior art. Therefore, even when the number of target circuits controlled in the test is increased, the wiring area for the test signal can be reduced, and an increase in chip size can be suppressed. Further, even if the number of test signals is increased, there is an effect that the possibility of becoming an obstruction factor when reducing the chip size can be reduced.

It is a schematic block diagram which shows the structure of the semiconductor device 100 of this invention. FIG. 2 is a circuit block diagram of a portion related to a test operation in the semiconductor device 100 shown in FIG. FIG. 3 is a circuit diagram of first and second registers shown in FIG. 2. 4 is a timing chart used for explaining a test operation of the semiconductor device 100. FIG. 2 is a layout diagram of the semiconductor device 100 shown in FIG. 1. It is a whole block diagram of the conventional semiconductor device 900. FIG. 7 is a layout diagram of the semiconductor device 900 shown in FIG. 6.

A typical example of the technical idea for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present invention are not limited to this technical idea, but are the contents described in the claims of the present invention.
A DFT decoder that activates a test signal generates a test signal DFT according to a test code input from the outside in order to adjust the characteristics and operation of a target circuit controlled in the test.

  Here, as a target circuit controlled in the test, for example, in a DRAM or the like, a delay circuit that speeds up the sense amplifier activation timing or conversely delays it can be considered. In the normal operation mode, the sense amplifier is activated after a sufficient potential difference is generated in the bit line pair after the word line is selected. However, there may be a case where a memory cell capacity is small due to manufacturing variations, etc., and in the normal operation mode timing setting, the product is judged to be non-defective, and the memory cell characteristics deteriorate after shipping the product. It may be possible. Therefore, an acceleration test for rejecting defective products in advance can be performed by providing a switch or the like in the delay circuit so that the sense amplifier activation timing is advanced and the operation margin of the DRAM is eliminated. Further, in the evaluation after the design, when there is no DRAM operation margin, it is possible to confirm whether the operation margin is widened by delaying the sense amplifier activation time by delaying the sense amplifier activation timing. Therefore, the test signal DFT can be used as a signal for controlling the switch of the delay circuit.

  A DRAM or the like generally includes an internal voltage generation circuit, and a memory cell is generally operated by the output of the step-down circuit. In order to reject the initial failure in the reliability test, the memory cell is operated at a high voltage different from that at the time of product shipment. In such a case, it is conceivable to perform switching by providing a bypass switch that connects the internal voltage generation circuit to a circuit that generates another voltage. Further, in the evaluation after the design, when there is no operation margin of the DRAM, it is possible to confirm how the operation margin changes by increasing or decreasing the output of the step-down circuit. Therefore, the test signal DFT can be used as a signal for controlling the bypass switch.

The DFT decoder is a circuit that generates the test signal DFT as described above according to the input test code. However, as the number of tests increases, the number of test signals DFT increases. The wiring area increases, leading to an increase in the chip size or an obstacle to the reduction in the chip size.
In view of this, the technical idea of the semiconductor device according to the present invention is to reduce the wiring area necessary for the test signal by serially transmitting the test signal to the register trains connected in a daisy chain. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. Here, a semiconductor memory device is used as an example. The semiconductor device 100 includes a clock generation circuit 101, a command decoder 102, a memory cell array 103, a read / write control unit 104, an address latch 105, a decoder unit 106, a first register unit 107, and a second register unit 108. Yes.
The clock generation circuit 101 includes a clock signal CK, an inverted clock signal / CK that is a complementary signal of the clock signal CK, a clock enable signal CKE that indicates whether the input clock signal CK and the inverted clock signal / CK are valid, , Is input. Further, the clock generation circuit 101 sends an external clock signal CK to the read / write control unit 104 which is an internal circuit of the semiconductor device 100 in response to the input clock signal CK, inverted clock signal / CK, and clock enable signal CKE. Supply a synchronized internal clock signal. The clock generation circuit 101 supplies an internal clock signal synchronized with the external clock signal CK to the command decoder 102.

  The command decoder 102 latches and decodes the command signals (chip select signal CSB, row address strobe signal RASB, column address strobe signal CASB and write enable WEB) in synchronization with the internal clock signal. A control signal (internal command signal) for instructing the operation is output to the read / write control unit 104. Further, when a test command (TEST) is input, the command decoder 102 outputs a test command signal TRS synchronized with the internal clock signal to the address latch 105.

The memory cell array 103 is configured by arranging a plurality of memory mats including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bits.
The memory cell array 103 includes a plurality of sense amplifiers that perform operations such as amplifying data read from the memory cells to the bit lines, a plurality of word drivers that drive the plurality of word lines, a bit line, and an IO line. Are provided with a plurality of Y switches. The sense amplifier is a circuit that amplifies a weak data signal from a memory cell appearing on a bit line in a read operation. Further, in the write operation, it is a circuit for writing data to the memory cell via the bit line. The operation timing of the sense amplifier is controlled by a sense amplifier drive signal output from an X decoder and an X timing circuit described later. The Y switch controls the opening and closing timing by a Y decoder and a Y timing circuit described later. In the read operation, when the Y switch is opened in the read operation, the data from the bit line is read, and this data is transferred to the read / write control unit 104 arranged outside the memory cell array 103. Further, the IO line transfers write data from the read / write control unit 104 to the bit line in the write operation.

The read / write control unit 104 is a control unit that controls the operation of the memory cell array 103, and includes an X decoder, an X timing circuit, a Y decoder / Y timing circuit, and the like.
The X decoder and the X timing circuit decode the row address (internal address signal) input from the address latch 105, and select the memory cell of the memory cell array 103 using the word line according to the decoding result. The X decoder and the X timing circuit control the operation timing of the sense amplifier that amplifies the difference potential between the bit lines.
The Y decoder and Y timing circuit decode the column address (internal address signal) input from the address latch 105 and select a Y switch interposed between the bit line and the IO line according to the decoding result. Etc. The Y decoder and the Y timing circuit are synchronized with the internal clock signal input from the clock generation circuit 101 and from the selected memory cell via the IO line in accordance with the internal command signal input from the command decoder 102. The operation of reading data or the operation of writing data to the selected memory cell via the IO line is controlled. The Y decoder and the Y timing circuit output the memory cell data to the outside as DQ signals (DQ0 to n). The data circuit writes a DQ signal input from the outside as data in the memory cell. These reading and writing operations are also performed in synchronization with the internal clock signal.

  As described above, the read / write control unit 104 includes an X decoder and an X timing circuit, a Y decoder and a Y timing circuit. These X decoder and X timing circuit, Y decoder and Y timing circuit further have the following control circuit, and control the operation of the memory cell array 103. The control circuit includes a circuit for changing the timing (for example, a circuit for increasing or decreasing the drive timing of the sense amplifier, or a delay circuit embedded in advance in a signal control system used for control for writing and reading). Further, the control circuit includes a circuit for changing the voltage level of the internally generated power supply circuit (for example, a circuit that can switch the input reference voltage input to the internally generated power supply circuit to a high voltage or a low voltage by the test signal DFT). There is. In addition, the control circuit is a circuit that changes the circuit operation by enabling or disabling the control signal (the circuit that was originally inactivated can be activated by the test signal DFT, or vice versa. A circuit that can be deactivated by a test signal DFT).

  The address latch 105 latches an address signal input from the outside in synchronization with the internal clock signal in the read / write operation, and the X decoder, X timing circuit, Y decoder, and Y timing circuit of the read / write control unit 104. An internal address signal is supplied to. In the test operation, the address latch 105 latches an address signal (test code signal) input from the outside in response to the test command signal TRS in synchronization with the internal clock signal, and supplies the test address signal TA to the decoder unit 106. To do.

The decoder unit 106, the first register unit 107, and the second register unit 108 are characteristic portions of the semiconductor device 100, and will be described below with reference to FIG.
FIG. 2 is a circuit block diagram of a portion related to the test operation. The command decoder 102, the read / write control unit 104, the address latch 105, the decoder unit 106, the first register unit 107, and the second register unit in FIG. 108 is shown.
The decoder unit 106 includes an address predecoder 201 and a decoder circuit 202 (DFT decoder). The address predecoder 201 receives the m-bit test address signal TA from the address latch 105 and supplies k test preaddress signals TPA to the decoder circuit 202. Here, the address predecoder 201 divides the m-bit test address signal TA into a plurality of groups, decodes the test address signal TA in each group, and outputs a decoding result signal to the decoder circuit 202. . For example, when the test address signal TA is 8 bits, the address predecoder 201 divides into 3 groups of 2 bits, 3 bits, and 3 bits. The address predecoder 201 outputs four, eight, and eight decoding result signals from each group to the decoder circuit 202. Thus, the relationship between the number of bits m of the test address signal TA and the number of signals k of the test pre-address signal TPA is such that k> m.

  The decoder circuit 202 is generally composed of an AND circuit, decodes the test pre-address signal TPA input from the address pre-decoder 201, generates test signals DFT0 to DFTn, and outputs them to the first register unit 107. . Here, the decoder circuit 202 can generate a maximum of (2 k powers) DFT signals. In FIG. 2, (n + 1) test signals DFT0 to DFTn are generated.

The first register unit 107 includes (n + 1) first registers DFTrA0 to DFTrAn. The first register DFTrAk (0 ≦ k ≦ n) is connected to the decoder unit 106 and receives the test signal DFTk. The output of the first register DFTrAk is connected to the next stage DFTrA (k + 1). The first register DFTrAn at the final stage is connected to the second register unit 108.
The second register unit 108 includes (n + 1) second registers DFTrB0 to DFTrBn. The input of the second register DFTrBk is connected to the previous stage DFTrA (k−1). The second register DFTrBk supplies a control test signal DFTFk to the control circuit CKTk in the read / write control unit 104.
Note that the input node of the first register DFTRa0, which is the first stage of the first register unit 107 (the node to which the input signal TSIN is input), has a fixed potential fixed at either the H level or the L level, for example. Connecting.
In addition, an output node of the second register DFTrBn that is the final stage of the second register unit 108 (a node that outputs the output signal TSOUT) is connected to the data terminal DQ through an output buffer included in the semiconductor device. Good. In this way, the actual state of the test signal can be monitored at the data terminal DQ.

FIG. 3 is a circuit diagram of the first register DFTrA and the second register DFTrB. FIG. 3A shows the first register DFTrA, and FIG. 3B shows the second register DFTrB. .
The first register DFTrA includes a selector SELA and a D-type flip-flop DFFA.
The selector SELA supplies the test signal DFT to the data input terminal D of the D-type flip-flop DFFA when the register control signal TMON is at the H level (logic level “1”). The selector SELA receives the input signal TSIN (the output signal TSOUT of the D-type flip-flop DFFA in the first register DFTrA in the previous stage) when the register control signal TMON is at the L level (logic level “0”). Supplied to the data input terminal D of the DFFA.

The D-type flip-flop DFFA latches data input from the selector SELA to the data input terminal D in synchronization with the rising edge of the register control signal TCK input to the clock terminal, and until the next rising edge of the register control signal TCK, The latched data is held at the data output terminal Q. The D-type flip-flop DFFA supplies the output signal TSOUT from the data output terminal Q to the first register DFTRA in the next stage (the first register DFTrA in the final stage is the second register DFTrB in the first stage).
Note that when the register control signal TRST is input to the reset terminal R, the D-type flip-flop DFFA resets the level of the data output terminal Q to the L level.

The second register DFTrB includes a selector SELB, a D-type flip-flop DFFB1, and a D-type flip-flop DFFB2.
The selector SELB supplies the control test signal DFTF, which is the output of the D-type flip-flop DFFB2, to the data input terminal D of the D-type flip-flop DFFB1, when the register control signal TMON is at the H level. This is because when the control test signal DFTF is monitored, the data input terminal D of the D-type flip-flop DFFB1 is connected to the data output terminal Q of the D-type flip-flop DFFB2, so that the control test signal DFTF is connected to the D-type flip-flop. Into DFFB1. Then, the captured control test signal DFTF is sequentially transferred using the second register DFTrB, and is output to the outside of the semiconductor device for monitoring, for example. Further, when the register control signal TMON is at L level, the selector SELB receives the input signal TSIN (the output signal TSOUT of the D-type flip-flop DFFB1 in the second register DFTRB in the previous stage) and the data input terminal D of the D-type flip-flop DFFB1. To supply.

The D-type flip-flop DFFB1 latches data input from the selector SELB to the data input terminal D in synchronization with the rise of the register control signal TCK input to the clock terminal, and until the next rise of the register control signal TCK, The latched data is held at the data output terminal Q. The D-type flip-flop DFFB1 supplies the output signal TSOUT from the data output terminal Q to the second register DFTrB1 at the next stage. The D-type flip-flop DFFB1 supplies the output signal TSOUT to the data input terminal D of the D-type flip-flop DFFB2 connected to its own data output terminal Q.
The D-type flip-flop DFFB2 latches data input from the D-type flip-flop DFFB1 to the data input terminal D in synchronization with the rise of the register control signal TUPD input to the clock terminal, and the latched data is output to the data output terminal. Hold on Q. The D-type flip-flop DFFB2 supplies a control test signal DFTF from the data output terminal Q to the control circuit CKT in the read / write control unit 104.
Each of the D flip-flops DFFB1 and DFFB2 resets the level of the data output terminal Q to L level when the register control signal TRST is input to the reset terminal R.

Returning to FIG. 2, the read / write control unit 104 includes control circuits CKT0 to CKTn. The input of the control circuit CKTk is connected to the output of the second register DFTrBk.
As described with reference to FIG. 1, the control circuits CKT0 to CKTn are circuits that change timing, circuits that change the voltage level of the internally generated power supply circuit, circuits that change circuit operation by enabling or disabling control signals, and the like. is there.

Next, operations related to the test operation among the operations of the semiconductor device 100 will be described with reference to the drawings.
FIG. 4 is a timing chart used for explaining the test operation of the semiconductor device 100. In FIG. 4, the semiconductor device 100 takes in a test command signal (TEST) and a test code signal (address A, B, C, D, E) in synchronization with a clock signal CK input from the outside, and a test address signal. The timing for generating TA, test pre-address signal TPA, test signal DFTn, control test signal DFTFn, etc. is shown.
FIG. 4 shows a case where the test signal DFTn becomes H level among the test signals DFT0 to DFTn which are output signals of the decoder unit 106 in FIG.
Also, the register control signals (TCK, TMON, TRST, and TUPD) used for the description of the circuit configurations of the first and second registers are generated by the decoder unit 106 using the test pre-address signal TPA.
In particular, the register control signal TCK is generated in the clock generation circuit in the decoder unit 106 according to the test pre-address signal TPA by arranging a clock generation circuit for generating the register control signal TCK in the decoder unit 106 as an example. To do.
Further, as another first configuration for generating the register control signal TCK, the decoder unit 106 is configured to generate the register control signal TCK for one cycle in accordance with a predetermined test pre-address signal TPA. By inputting the test pre-address signal TPA, it is possible to generate the register control signal TCK as many times as desired.
Furthermore, as another second configuration for generating the register control signal TCK, the decoder unit 106 includes a circuit for controlling the number of clock toggles, and the decoder unit 106 is based on a clock supplied from the outside to the semiconductor device 100. It is also possible to employ a configuration in which the decoder 106 controls the number of toggles of the clock supplied from the outside by the decoder unit 106 and generates the clock supplied from the outside whose toggle number is controlled as the register control signal TCK.

At time t1, the command decoder 102 takes in the test command (TEST) and outputs a test command signal TRS synchronized with the internal clock signal to the address latch 105. The address latch 105 latches an externally input address signal (test code signal A) in synchronization with the test command signal TRS, and supplies the test address signal TA to the decoder unit 106. In the decoder unit 106, the address predecoder 201 supplies the test preaddress signal TPA to the decoder circuit 202, and the decoder circuit sets the test signal DFTn among the test signals DFT0 to DFTn to the H level.
Since the register control signal TMON inputted to all selectors (SELA, SELB) in the first and second registers is at the L level, the input level of the data input terminal D of the D flip-flops DFFA and DFFB1 Are all at the L level.

At time t2, the address latch 105 latches an address signal (test code signal B) input from the outside in synchronization with the test command signal TRS, and supplies the test address signal TA to the decoder unit 106. The decoder unit 106 generates a register control signal TMON that is a switching signal for all selectors (SELA and SELB) in the first and second registers. Thereby, in all the selectors (SELA) in the first register, the input path is switched to the side for taking in DFTn. That is, each data input terminal D of the D-type flip-flop DFFA of the first registers DFTrA0 to DFTrAn is connected to the decoder unit 106.
The decoder unit 106 generates the register control signal TCK once at the same time as the register control signal TMON. As a result, each of the D-type flip-flops DFFA of the first registers DFTrA0 to DFTrAn latches the data (test signals DFT0 to DFTn) input to the respective data input terminals D until the next rise of the register control signal TCK. The latched data is held at the data output terminal Q.
Here, since only the test signal DFTn is at H level, only the output (output signal TSOUT) of the D-type flip-flop DFFA of the first register DFTrAn becomes H level, and the other first registers DFTrA0 to DFTn−1 The output (output signal TSOUT) of the D-type flip-flop DFFA is at the L level.

  Subsequently, at time t 3, the address latch 105 latches an address signal (test code signal C) input from the outside in synchronization with the test command signal TRS, and supplies the test address signal TA to the decoder unit 106. The decoder unit 106 generates a predetermined number of register control signals TCK. In this embodiment, since the number of test signals DFT is (n + 1), the data stored in the first register is transferred to the corresponding second register. The control signal TCK is generated (n + 1) times. Although (n + 1) TCKs are not shown in FIG. 4 because of the limitation that can be illustrated, (n + 1) TCKs are generated between times t3 and t4. Further, unlike time t2, the decoder unit 106 does not generate the register control signal TMON (maintains the L level).

  Thus, in the first register unit 107, the data input terminals D of the D-type flip-flops DFFA of the first registers DFTrA0 to DFTrAn are connected as follows. That is, in the first register DFTrA0, the data input terminal of the D-type flip-flop DFFA is connected to a fixed potential. In the first registers DFTrA1 to DFTrAn, each of the data input terminals D of the D-type flip-flop DFFA is connected to the output of the first register DFTRa in the previous stage (the data output terminal Q of the D-type flip-flop DFFA). The

  In the second register unit 108, the data input terminals D of the D-type flip-flops DFFB1 of the second registers DFTrB0 to DFTrBn are connected as follows. That is, in the second register DFTrB0, the data input terminal D of the D-type flip-flop DFFB1 is connected to the output of the first register DFTrAn in the previous stage (data output terminal Q of the D-type flip-flop DFFA). In the second registers DFTrB1 to DFTrBn, each of the data input terminals D of the D-type flip-flop DFFB1 is connected to the output of the second register DFTRB of the previous stage (the data output terminal Q of the D-type flip-flop DFFB1). The

That is, each of the second registers takes in the input signal TSIN from each input terminal in synchronization with the rise of the register control signal TCK and outputs it as the output signal TSOUT. With this operation, the test signal DFTn is sequentially transmitted between adjacent registers.
For example, at the rise time (time tk) of the k-th register control signal TCK counted from time t3, the second register DFTrBk outputs the output (H level) of the second register DFTrB (k−1) at the previous stage. The input signal TSIN (k) is taken in synchronization with the register control signal TCK. The second register DFTrBk holds data (H level) until the next rising edge of the register control signal TCK (time tk + 1), and outputs an H level signal to the second register DFTrB (k + 1) at the next stage. Output as TSOUT.
At time tk + 1, the second register DFTrB (k + 1) takes the output (H level) of the second register DFTrBk in the previous stage as the input signal TSIN (k + 1) in synchronization with the register control signal TCK. The second register DFTrB (k + 1) holds the data (H level) until the next register control signal TCK rises (time tk + 2) and outputs the H level to the second register DFTrB (k + 2) at the next stage. Output as signal TSOUT.

  In this way, the test signal DFTn is sequentially transmitted between adjacent registers. Then, in synchronization with the (n + 1) th rise of the register control signal TCK, in the second register DFTrBn, the level of the data output terminal Q of the D-type flip-flop DFFB1 becomes H level. Further, since the data output terminal Q of the D-type flip-flop DFFB1 is connected to the data input terminal D of the D-type flip-flop DFFB2, the level of the data input terminal D of the D-type flip-flop DFFB2 is also H level.

At time t4, the address latch 105 latches an address signal (test code signal D) input from the outside in synchronization with the test command signal TRS, and supplies the test address signal TA to the decoder unit 106. The decoder unit 106 generates a register control signal TUPD. Note that the decoder unit 106 does not perform the data (test signal DFT) shift operation in the first register unit 107 and the second register unit 108, and therefore does not generate the register control signals TCK and TMON.
In the second register DFTrBn, since the level of the data input terminal D of the D-type flip-flop DFFB2 is H level, the test signal DFTFn for H level control is received in response to the rising of the register control signal TUPD to H level. Is supplied to the control circuit CKTn in the read / write control unit 104. As a result, the control circuit CKTn is adjusted. That is, the control circuit CKTn controls the memory cell array 103 by adjusting, for example, the timing of the read / write operation to characteristics and operations different from those in the normal operation mode.
In the other second registers DFTrB0 to (n-1), the level of the data input terminal D of the D-type flip-flop DFFB2 is L level, so that the L level control test signals DFTF0 to (n) -1) is supplied to the control circuits CKT0 to (n-1).

  Finally, at time t5, the address latch 105 latches an externally input address signal (test code signal E) in synchronization with the test command signal TRS and supplies the test address signal TA to the decoder unit 106. The decoder unit 106 generates a register control signal TRST. As a result, the contents of all the registers are reset, and the state returns to the default state (the output signal TSOUT is at the L level).

  As described above, the output (output signal TSOUT) of the second register DFTrBn (final stage), which is the final stage of the second register unit 108, is connected to the data terminal DQ via the output buffer provided in the semiconductor device. When the actual test signal state is monitored by the data terminal DQ, the test code signal C is input again during the period between the time t4 and the time t5 in FIG. Generate (n + 1) times. At this time, before inputting the test code C, the test code A is input again, and each second register DFTrB0 is input to the D-type flip-flop DFFB1 of each of the second registers DFTrB0 to DFTrBn of the second register section. The operation of fetching data held by the D-type flip-flop DFFB2 of ˜DFTrBn may be performed.

As described above, in the semiconductor device according to the present embodiment, the predetermined first code indicated by the test code signal among the plurality of first test signals (DFT0 to DFTn) in accordance with the test code signal (address) supplied from the outside. A decoder (decoder unit 106) that activates one test signal, and a plurality of first test signals that are connected to the decoder and supplied in parallel from the decoder, and that receive the plurality of first test signals as a plurality of second test signals. A first register unit (first register unit 107) that outputs the test signal in series as a test signal, and a plurality of second test signals that are connected to the first register unit and supplied in series from the first register unit And a second register unit (second register unit 108) that outputs a plurality of second test signals in parallel as a plurality of third test signals (DFTF0 to DFTFn), and a second register A plurality of third test signals supplied in parallel from the second register unit and controlling the operation of the memory cell array (memory cell array 103) according to the plurality of third test signals. A semiconductor device (semiconductor device 100).
The first register unit is a plurality of first registers (DFTrA) that are cascade-connected to each other, each connected to a decoder, and each one corresponding to one of the plurality of first test signals. Receiving the test signal, each of the plurality of first registers excluding the first register (DFTrAn) at the final stage applies the plurality of first test signals to the first register at the next stage. The first register in the final stage includes a plurality of first registers that output a plurality of second test signals in series, and the second register unit (second register unit 108) includes: A plurality of second registers (DFTrB) that are subordinately connected to each other, and the second register (DFTrB0) in the first stage among the plurality of second registers is connected to the output of the first register in the last stage; Multiple second cashiers The second registers (DFTrBn) of each of the data stages sequentially transfer a plurality of second test signals as a plurality of third test signals to the second register of the next stage. Contains registers.

  According to the present invention, the decoder (decoder unit 106) activates one of the first test signals (DFT0 to DFTn), and the activated test signal is one of the plurality of first registers. The test signals input and activated are sequentially transferred in a plurality of first registers and a plurality of second registers connected to a plurality of control circuits each controlling the operation of the memory cell array. The As a result, the test signal sent from the decoder (decoder unit 106) that activates the test signal to the control unit (read and write control unit 104) that controls the operation of the memory cell array is transmitted between the first and second registers. Since the number of transmission lines (output signal TSOUT) and signals for controlling the first and second registers (register control signals TCK, TMON, TRST, and TUPD) can be reduced, the number of test signal wirings can be greatly increased as compared with the prior art. Can be reduced. Therefore, even when the number of target circuits controlled in the test is increased, the wiring area for the test signal can be reduced, and an increase in chip size can be suppressed. Further, even if the number of test signals is increased, there is an effect that the possibility of becoming an obstruction factor when reducing the chip size can be reduced.

Next, the layout of the semiconductor device 100 of the present invention will be described.
FIG. 5 is a schematic layout diagram of the semiconductor device 100 shown in FIG. In FIG. 5, the same components as those in FIG.
The memory cell array 103 in FIG. 1 is divided into two memory cell array regions (a memory cell array region 103a and a memory cell array region 103b). A peripheral circuit region is arranged between the two memory cell array regions. Here, the peripheral circuit area includes the clock generation circuit 101, the command decoder 102, the memory cell array 103, the read / write control unit 104, the address latch 105, the decoder unit 106, the first register unit 107, and the second register in FIG. This is an area including the portion 108. In FIG. 5, the decoder unit 106 and the first register unit 107 are collectively shown as a decoder unit 202a (DFT DEC). Further, the second register DFTrB constituting the second register unit 108 is disposed so as to surround the peripheral circuit region. Here, each of the second registers DFTrB is arranged corresponding to the control circuit CKT described above. By arranging in this way, the semiconductor device 100 transmits the test signal DFT clockwise along one line connecting the second registers DFTrB in FIG. In the vicinity of the second register DFTrB, a control circuit CKT for adjusting the operation of the memory cell array is appropriately arranged according to a necessary test, and a test signal DFT necessary for the adjustment is daisy chain connected. The second register DFTrB can be supplied. As a result, wiring as many as the number of test signals is not required as in the prior art, and only the register control signal is wired in the peripheral circuit area, so that an increase in the peripheral circuit area can be suppressed as compared with the prior art.

As described above, the memory cell array 103 shown in FIG. 5 is divided into the first and second memory cell array regions, and the peripheral circuit region disposed between the first memory cell array region and the second memory cell array region is divided. In addition, a decoder unit 106, a first register unit 107, a second register unit 108, and a read / write control unit 104 are formed in the peripheral circuit region, and a plurality of second registers surround the peripheral circuit region. Is arranged.
However, the memory cell array 103 as shown in FIG. 5 is divided into two upper and lower memory cell array regions, which is an example of the embodiment, and of course is not limited to this example. The memory cell array 103 may not be divided or may be further divided into a plurality of memory cell array regions larger than two. Here, what is characteristic is that a plurality of control circuits (control circuits CKT) are arranged adjacent to the memory cell array (memory cell array 103) in the peripheral circuit region, and each second register includes a plurality of control circuits (control circuits). Circuit CKT).

In the present invention, since the decoder unit 106 constituting the semiconductor device 100 has the same decoding method as the conventional one, the test code (address input B, C) described with reference to FIG. , D), the same test as before can be performed simply by incorporating a sequence corresponding to the above.
As described above, when the test code signal A (first test code signal) is input, the decoder (decoder unit 106) generates a plurality of test signals DFT0 to DFTn. Further, when the test code signal B (second test code signal) is input, the decoder latches each of the plurality of test signals in each of the first registers DFTrA0 to DFTrAn (a plurality of first registers). When a decoder control unit (a logic unit that generates register control signals TMON and TCK) and a test code signal C (third test code signal) are input, a plurality of latched latches in a plurality of first registers A second decoder control unit (a logic unit that generates (n + 1) predetermined register control signals TCK) that latches each test signal in each of the second registers DFTrB0 to DFTrBn (a plurality of second registers); When a test code signal D (fourth test code signal) is input, a plurality of tests latched in a plurality of second registers are received. Signals respectively, the control circuit CKT0～CKTn (plural control circuits) have third decoder control section supplies, respectively (the logic unit for generating a register control signal TUPD), the.
Thereby, in the test method of the semiconductor device 100, the second step of inputting the second test code signal and the third test code signal are added to the first step of inputting the first test code signal in the related art. By adding the third step of inputting and the fourth step of inputting the fourth test code signal, it is possible to provide a test method for adjusting the operation of the memory cell array as in the conventional case. Further, when creating a program used for the test method, it is possible to create a program simply by additionally describing the second to fourth steps in the program in which the first step used conventionally is described.

The basic technical idea of the present application is not limited to this, and a semiconductor chip having the functions of the present application can be applied to semiconductor devices such as SOC, SIP, and POP (package on package). The function of the semiconductor chip having the function of the present application can be applied to a semiconductor device such as a CPU, MCU, DSP, or memory.
The transistors constituting the logic circuit may be field effect transistors (FETs). Besides MOS (Metal Oxide Semiconductor), MIS (Metal-Insulator Semiconductor), TFT (Thin Film Transistor), etc. Applicable to various FETs. It can be applied to various FETs such as transistors. A bipolar transistor may be used. Transistors other than FETs may be used.
Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various modifications and corrections that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

  For example, when the same test signal DFT is used in a plurality of control circuits CKT, the first register unit 107 includes a plurality of first registers DFTrA that latch the same test signal DFT. The register connection order may be set so that the same control test signal DFTF is supplied from the second register DFTrB of the second register unit 108 to the required control circuit CKT. For example, when the test signals DFT0 are required by the control circuits CKT0 and CKTn, the same test signal DFT0 (H level) is latched from the decoder circuit 202 in the first registers DFTrA0 and DFTrAn. As described above, if the shift operation is performed (n + 1) times, the H-level control test signals DFTF0 and DFTFn can be supplied from the second registers DFTrB0 and DFTrBn to the control circuits CKT0 and CKTn.

  When the test signal can also be controlled by the fuse, the signal from the fuse is input to the second register DFTrB of the second register unit 108 on the control circuit CKT side which is a circuit controlled by the test. To. This can be handled by performing a logical operation such as OR or EOR between the signal from the fuse and the output signal TSOUT of the D-type flip-flop DFFB2.

Further, the input node (node to which the input signal TSIN is input) of the first register DFTrA0, which is the first stage of the first register unit 107, has a predetermined signal pattern, for example, (HHLLHHLL) instead of being connected to a fixed potential. You may connect to the output of the pattern generation circuit which outputs a pattern signal. When configured in this way, when the actual state of the test signal is monitored by the data terminal DQ, the end point determination of the test signal can be easily performed.
The input node of the first register DFTRa0, which is the first stage of the first register unit 107 (the node to which the input signal TSIN is input), is connected to the final stage of the second register unit 108 instead of being connected to a fixed potential. It may be configured to be connected to an output node of a certain second register DFTrBn. When configured in this manner, the first register DFTRa0 in the first stage is also the register in the same stage as the other registers, so that the plurality of first registers DFTRa constituting the first register unit 107 have the same configuration. And can.

Furthermore, instead of generating the register control signals (TCK, TMON, TRST, and TUPD) used in the description of the circuit configurations of the first and second registers in the decoder unit 106, a control circuit for controlling the register circuit is provided. It is good also as a structure provided separately.
In addition, all control test signals DFTF0 are not generated from the present invention, but some test signals, for example, test signals frequently used in wafer tests and sorting tests after assembly, are connected in the same manner as in the past. By adopting the method of the present invention for the test signal for evaluation, it is possible to reduce the wiring area while keeping the time for the wafer test and the sorting test as before.

  DESCRIPTION OF SYMBOLS 100,900 ... Semiconductor device, 101 ... Clock generation circuit, 102 ... Command decoder, 103 ... Memory cell array, 103a, 103b ... Memory cell array area, 104 ... Read and write control part, 105 ... Address latch, 106 ... Decoder part, 107 DESCRIPTION OF SYMBOLS 1st register part, 108 ... 2nd register part, 201 ... Address predecoder, 202 ... Decoder circuit, 202a ... Decoder part, DFTrA, DFTrA0, DFTrA1, DFTrAk, DFTrAn ... 1st register, DFTrB, DFTrB0, DFTrB1, DFTrBk, DFTrBn ... second register, CKT, CKT0, CKTk, CKTn ... control circuit, SELA, SELB ... selector, DFFA, DFFB1, DFFB2 ... D-type flip-flop, DFT, D T0, DFTk, DFTn ... test signal, DFTF, DFTF0, DFTFk, DFTFn ... test signal for control, TCK, TMON, TRST, TUPD ... register control signal, TRS ... test command signal, TA ... test address signal, TPA ... test pre Address signal, TSIN ... input signal, TSOUT ... output signal

Claims (8)

A decoder that activates a predetermined first test signal indicated by the test code signal among the plurality of first test signals in response to a test code signal supplied from outside;
A first register connected to the decoder, receiving the plurality of first test signals supplied in parallel from the decoder, and outputting the plurality of first test signals in series as a plurality of second test signals And
The plurality of second test signals connected to the first register unit and supplied in series from the first register unit are received, and the plurality of second test signals are used as a plurality of third test signals. A second register unit for outputting in parallel;
Connected to the second register unit, receives the plurality of third test signals supplied in parallel from the second register unit, and controls the operation of the memory cell array according to the plurality of third test signals A control unit to
A data output terminal;
With
The first register unit is a plurality of first registers that are cascade-connected to each other, each connected to the decoder, and each one corresponding to one test signal among the plurality of first test signals Each of the plurality of first registers except for the first register at the last stage is sequentially transferred to the first register at the next stage as the plurality of first test signals as a plurality of second test signals. The first register in the final stage includes the plurality of first registers that output the plurality of second test signals in series;
The second register unit is a plurality of second registers that are cascade-connected to each other, and the first-stage second register of the plurality of second registers is the output of the last-stage first register Each of the plurality of second registers except for the second register at the last stage is connected to the second register at the next stage as the plurality of third test signals. A plurality of second registers for sequential transfer;
The second register in the last stage among the plurality of second registers sequentially transfers the plurality of third test signals to the data output terminal.   2. The semiconductor device according to claim 1, wherein the number of the plurality of first registers and the number of the plurality of second registers are the same.   3. The semiconductor device according to claim 1, wherein the first register of the first stage among the plurality of first registers further receives a fixed potential. 4.   3. The semiconductor device according to claim 1, wherein a first-stage first register of the plurality of first registers further receives a first-stage input signal having a predetermined pattern.   The second register of the last stage of the plurality of second registers is connected to the first register of the first stage of the plurality of first registers. The semiconductor device described.   The control unit includes a plurality of control circuits each connected to a corresponding one of the plurality of second registers and receiving a corresponding one of the plurality of third test signals. The semiconductor device according to claim 1, wherein: A peripheral circuit region disposed adjacent to the memory cell array;
The plurality of control circuits are arranged adjacent to the memory cell array in the peripheral circuit region, and each of the second registers is arranged corresponding to each of the plurality of control circuits. 6. The semiconductor device according to 6.   The decoder generates first and second register control signals in response to the test code signal, the decoder supplies the first register control signal to the first register unit, and the decoder Supplying the first and second register control signals to the second register unit, and the first register unit outputs the plurality of first test signals according to the first register control signal. The plurality of second test signals are output in series as a plurality of second test signals, and the second register unit is supplied in series from the first register unit in response to the first register control signal. 8. The method according to claim 1, further comprising: receiving a signal and outputting the plurality of second test signals in parallel as a plurality of third test signals in accordance with the second register control signal. Half as described in Body apparatus.

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