JP5593715B2 - Packaged semiconductor device and method for manufacturing packaged semiconductor device - Google Patents

Description

  The present invention relates to a packaged semiconductor device that is a semiconductor device with a package and a manufacturing method thereof, and more particularly, to a packaged semiconductor device having a resin wiring board in its configuration and a manufacturing method thereof.

  In the case of packaging a bare chip which is a semiconductor device, in recent years, those using a resin wiring board as a part thereof tend to be frequently used. A resin wiring board is cheaper than a ceramic substrate, and can be a useful form if measures for ensuring reliability are taken according to the form as a package.

  In general, a function required for a semiconductor package is to convert a terminal pad provided on a bare chip into a terminal having an arrangement and a form suitable for mounting on another substrate or the like through electrical continuity with the terminal pad. . Here, particularly in the case where a resin wiring board is included in the configuration, the portion for electrically connecting the terminal pad on the bare chip and the package side, the material for sealing the bare chip itself, and the physical properties of the resin wiring board It is necessary to pay attention to the difference. If the compatibility is poor, it may cause peeling at the interface or warping of the resin wiring board, resulting in a package with high reliability.

  An example of a packaged semiconductor device having a resin wiring board in its configuration is disclosed in Patent Document 1 below. In this example, in order to prevent peeling between the resin wiring board and the sealing material, the sealing resin is formed to wrap around from the upper surface to the lower surface of the resin wiring board. However, since the resin wiring board and the sealing resin cannot be the same material and have different physical properties, it is considered that there is a limit to improving the reliability.

JP-A-11-87566

  The present invention has been made in view of the above circumstances, and in a packaged semiconductor device that is a semiconductor device with a package and a method for manufacturing the same, a portion of a resin wiring board located below a bare semiconductor chip, and An object of the present invention is to provide a packaged semiconductor device that can improve the reliability of adhesion to a resin material that seals a semiconductor chip, and thereby improve the reliability of the device, and a method for manufacturing the same.

In order to solve the above problems, a packaged semiconductor device which is one embodiment of the present invention is provided with a bare semiconductor chip having a functional surface and a back surface facing the functional surface, and provided on the functional surface of the semiconductor chip. A wiring pattern including a metal bump having a height of 20 μm to 80 μm and a forming pitch of 200 μm to 100 μm, a pad positioned opposite to the metal bump, the pad of the wiring pattern, and the metal bump, electrical and a solder mechanically connecting, located in the semiconductor chip of a certain side of the wiring pattern on the wiring pattern, and so as to close contact with the functional surface and the back surface of the semiconductor chip a first resin layer that is embedded in the semiconductor chip, the wiring pattern to the inner layer of the wiring layer, the first via a wiring pattern Characterized by comprising a second resin layer located in layers with respect to fat layer.

That is, in this packaged semiconductor device, the second resin layer functions as a part of the resin wiring board located on the lower side (functional surface side) of the bare semiconductor chip, and the first resin layer , and is configured to function as a resin material for sealing the semiconductor chip. With this configuration , the resin wiring board using the first and second resin layers has a wiring pattern including a pad that is electrically connected to the metal bumps provided on the semiconductor chip as an inner wiring layer. The semiconductor chip is embedded so as to be in close contact with the functional surface and the back surface of the semiconductor chip.

  Accordingly, since the two parts can be integrally formed as a resin wiring board, the resin wiring board part located below the bare semiconductor chip and the resin material for sealing the semiconductor chip are surely in close contact with each other. The reliability will be greatly improved.

Moreover, the manufacturing method of the packaged semiconductor device which is another aspect of the present invention is a metal foil laminated on the first surface of a first resin plate having a first surface and a second surface. the patterning, and forming a wiring pattern including a connection pad of the semiconductor chip, a step of the cream solder deposition on the connection pad, a back facing the functional surface and該機Noh mask having a terminal pad A semiconductor chip on which metal bumps having a height of 20 μm to 80 μm and a forming pitch of 200 μm to 100 μm are formed on the terminal pad, on the first surface of the first resin plate; Arranging the metal bumps so as to face the connection pads, and electrically and mechanically connecting and fixing with the solder derived from the cream solder; and the functional surface and the front of the semiconductor chip In the second resin plate, the semiconductor chip is disposed so that the back surface is made of a resin material and is in close contact with the resin material of the second resin plate which is a resin plate different from the first resin plate. And the step of integrating the second resin plate into the first resin plate in a laminated form.

That is, in this manufacturing method, the first resin plate is provided with a function as a resin wiring board located on the lower side (functional surface side) of the bare semiconductor chip. A function as a resin material for sealing the semiconductor chip is provided. Then, the first resin plate and the second resin plate are integrated in a laminated form. Therefore, the two parts can be integrally configured as a part of the resin wiring board, and the part of the resin wiring board located below the bare semiconductor chip and the resin material for sealing the semiconductor chip are: Adhesion is ensured and reliability is greatly improved. Here, the “first resin plate” and the “second resin plate” are obtained as a result obtained by this manufacturing method. In the “packaged semiconductor device” mentioned above, It corresponds to “resin layer” and “first resin layer”. Since ordinal numbers are given in the order of appearance, the correspondence is reversed.

  According to the present invention, in a packaged semiconductor device which is a semiconductor device with a package and a method for manufacturing the same, a portion of a resin wiring board located below a bare semiconductor chip, and a resin material for sealing the semiconductor chip, Therefore, the reliability of the apparatus can be improved.

1 is a cross-sectional view schematically showing a configuration of a packaged semiconductor device according to an embodiment of the present invention. FIG. 3 is a process diagram schematically showing a part of a manufacturing process of the packaged semiconductor device shown in FIG. 1 in cross section. FIG. 7 is a process diagram schematically showing in cross section another part of the manufacturing process of the packaged semiconductor device shown in FIG. 1. FIG. 12 is a process diagram schematically showing still another part of the manufacturing process of the packaged semiconductor device shown in FIG. 1 in section. Sectional drawing which shows typically the structure of the packaged semiconductor device which concerns on another embodiment of this invention. FIG. 6 is a process diagram schematically showing in cross section a part of the manufacturing process of the packaged semiconductor device shown in FIG. 5. Sectional drawing which shows typically the structure of the packaged semiconductor device which concerns on another embodiment of this invention. Sectional drawing which shows typically the structure of the packaged semiconductor device which concerns on another (4th) embodiment of this invention. FIG. 9 is a process diagram schematically showing in cross section a part of the manufacturing process of the packaged semiconductor device shown in FIG. 8. Sectional drawing which shows typically the structure of the packaged semiconductor device which concerns on another (5th) embodiment of this invention.

As an embodiment of the present invention, the resin wiring board is formed on the first resin layer on the side opposite to the side where the second resin layer of the first resin layer is located, and on the second resin layer. A solder resist layer may be provided on the second resin layer on the side opposite to the side where the first resin layer of the resin layer is located . Thus, by providing the solder resist layer on the upper surface and the lower surface, the structure in the thickness direction can be symmetric and the occurrence of warpage can be reduced.

Further, as the embodiment, the resin wiring board, the wiring pattern, the antenna conductor patterns can be including, to. The antenna conductor pattern may have a spiral shape, a helical coil shape, a patch shape or a dipole planar shape. In this aspect, as an application of a packaged semiconductor device, a function as a non-contact data carrier (also referred to as an electronic tag, an IC tag, an RFID, or the like) is provided using a semiconductor chip included in the packaged semiconductor device. As a result, the added value can be increased. In this aspect, there may be no external terminals such as LGA and BGA.

Further, as an embodiment, the second resin layer, said has a hole formed I suited to the functional surface of the semiconductor chip may be a. This hole is provided as a hole that guides the flow of the resin material so that it spreads easily on the functional surface of the semiconductor chip and easily adheres to it during manufacturing. After the manufacture, the holes do not reach the functional surface of the semiconductor chip due to the flow and deformation of the resin material.

Further, as an embodiment, the first resin layer may further embed a passive element component. In this packaged semiconductor device, passive element components can be embedded in the same manner as a bare semiconductor chip. Thereby, an added value can be increased.

  Further, as an embodiment as a manufacturing method, the second resin plate has an opening at a position corresponding to the semiconductor chip as a state before being integrated with the first resin plate. The prepreg and the cured post-curing resin plate are laminated members, and the step of integrating is a step in which the surface of the prepreg of the second resin plate is laminated on the first resin plate. , And can be.

  When such a second resin plate is used, the prepreg obtained by heating enters between the semiconductor chip and the first resin plate, and the resin material is in close contact with the functional surface of the semiconductor chip. It becomes easy to obtain. In addition, since a part of the second resin plate is a cured resin plate in a cured state, an area in the height direction is secured with respect to the semiconductor chip during stacking, and an excessive pressing force is applied to the semiconductor chip. Such inconvenience can be effectively avoided.

  Further, as an embodiment, as a state before the second resin plate is integrated with the first resin plate, the first resin in a semi-cured state having an opening at a position corresponding to the semiconductor chip. A resin plate having a laminated member of a prepreg and a cured resin plate in a cured state, and a semi-cured second prepreg positioned on the side of the laminated resin plate of the laminated member. The step of converting can be a step of laminating the surface of the first prepreg of the second resin plate on the first resin plate. In this case, in addition to the effects as described above, it is easy to create a state in which the resin material is in close contact with the back side of the semiconductor chip by the second prepreg.

  Further, as an embodiment, the first resin plate may have a through hole in a region where the semiconductor chip is to be located before the semiconductor chip is fixed. . According to this, at the time of subsequent lamination, the hole facilitates the flow and deformation of the resin material of the second resin plate, and the resin material flows so as to spread on the functional surface of the semiconductor chip and becomes easy to adhere.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a packaged semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the packaged semiconductor device includes an insulating resin layer 11, 12, 13, 14, wiring layers (wiring patterns) 21, 22, an interlayer connector 31, a semiconductor chip 41, and metal bumps. 42, solder 45, solder resist 61, and 62.

  In short, the packaged semiconductor device has a configuration in which the semiconductor chip 41 is packaged and the electrical continuity from each of the terminal pads that the semiconductor chip 41 has is applied to each of the external connection terminals formed by the wiring pattern 21. . The external terminals by the wiring pattern 21 are terminals having an area arrangement (grid arrangement) such as an LGA (land grid array).

  A portion constituted by the insulating resin layer 11, the wiring patterns 21 and 22, and the interlayer connection body 31 is connected to a terminal pad provided on the semiconductor chip 41 which is a bare chip, and is electrically connected to the other terminal board. It is a functional part that converts it into a terminal having an arrangement and form suitable for mounting. And the part comprised by insulating resin 12,13,14 is the functional part which has sealed the site | part which electrically connects the terminal pad on the semiconductor chip 41, and said functional part, and semiconductor chip 41 itself. become.

  That is, this packaged semiconductor device has a function as a part of a wiring board located under the bare semiconductor chip 41 (functional surface side) and a function as a resin material for sealing the semiconductor chip 41. It is composed of an integrated resin wiring board. When viewed as an integral resin wiring board, it has a wiring pattern 22 including pads that are electrically connected to the metal bumps 42 provided on the semiconductor chip 41 as an inner wiring layer. The semiconductor chip 41 is embedded in close contact with the functional surface and the back surface.

  Therefore, by integrally configuring the two functional parts as a resin wiring board, the two functional parts, that is, the part of the resin wiring board located below the bare semiconductor chip 41 and the semiconductor chip 41 are provided. The resin material that seals the film reliably adheres and the reliability is greatly improved. This effect is a significant effect that cannot be realized with a package in which a semiconductor chip is mounted on a resin wiring board and the semiconductor chip is sealed with a mold resin or a potting resin. Furthermore, unlike the case where potting resin is used, the flatness of the upper surface of the package is high, so that when it is handled as a component, the suction stability of the mounting mounter by the suction head is well handled.

  The structure will be supplemented below as a packaged semiconductor device. The semiconductor chip 41 is electrically and mechanically connected to the inner wiring layer 22 (connection pad) via the metal bump 42 and the solder 45 by flip connection. For this connection, metal bumps 42 are formed in advance on terminal pads (not shown) of the semiconductor chip 41, and the connection pads are patterned on the wiring layer 22 in alignment with the metal bumps 42. The metal bump 42 is made of, for example, Au (gold) as a material, and is previously formed in a stud shape on the terminal pad.

  Such stud-like bumps can be formed, for example, by bonding a gold wire on a terminal pad by wire bonding technology and cutting it near the base, or by growing it on the terminal pad by plating. is there. Even plating can be formed with high productivity. Instead of the gold-made metal bumps 42 as described above, Pb (lead) bumps, solder ball bumps, Cu (copper) post bumps, or the like may be employed. The mode of flip connection of the semiconductor chip 41 will be further described later (FIGS. 2E and 2F).

  The wiring layer 21 is a wiring layer on the main surface and includes a pattern used as an external connection terminal as the packaged semiconductor device as described above. In addition to the LGA configuration described above, the external connection terminals can be configured as a BGA (ball grid array) by placing solder balls. An Ni / Au plating layer (not shown) having high corrosion resistance may be formed on the surface layer of the external connection terminal portion of the wiring layer 21.

  Solder resists 61 and 62, which are protective layers, are formed on the main surface and the main surface on the opposite side except for the portion that becomes the external connection terminal of the wiring layer 21 (thickness is about 20 μm, for example). Thus, by forming the layers of the solder resists 61 and 62 on both surfaces, a function as a protective layer is obtained, the symmetry of the structure in the thickness direction is improved, and a structure in which warpage hardly occurs as a whole can be achieved.

  Solder resist is a protective film that is generally provided on the main surface of the wiring board, and in this packaged semiconductor device that has a resin wiring board structure on both sides, such a preferable form that makes it difficult to warp easily. can get. This is also a great effect that cannot be realized with a package in which a semiconductor chip is mounted on a resin wiring board and the semiconductor chip is sealed with a mold resin or a potting resin.

  The wiring layer 22 is an inner wiring layer, and the insulating resin layer 11 is located between the wiring layer 21 and the wiring layer 22 to separate the wiring layers 21 and 22. The wiring layers 21 and 22 are each made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating resin layers 11 to 14 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of, for example, 60 μm and only the insulating resin layer 13 having a thickness of, for example, 150 μm, excluding the insulating resin layer 13. Only the insulating resin layer 13 has a position corresponding to the embedded semiconductor chip 51 serving as an opening, and provides a space for embedding the semiconductor chip 41. Then, the insulating resin layers 12 and 14 are deformed so as to fill the space of the opening of the insulating resin layer 13 for the embedded semiconductor chip 41, and the insulating resin layer 12 further includes the semiconductor chip 41 and the insulating resin. Deformation approach is also made to fill the space between the layers 11. Due to the deformation approach of the insulating resin layers 12 and 14, there is no space serving as a gap inside, and the resin material is in close contact with both the functional surface side and the back surface side of the semiconductor chip 41.

  The wiring layer 21 and the wiring layer 22 are electrically connected by an interlayer connector 31 that is sandwiched between the surfaces of these patterns and penetrates the insulating resin layer 11. The interlayer connection body 31 is derived from conductive bumps formed by screen printing of a conductive paste, and has a diameter in the axial direction (up and down stacking direction in FIG. 1) depending on the manufacturing process. It has changed. The diameter is, for example, 150 μm on the thick side. The interlayer connection body 31 can be more finely and freely arranged due to such formation process and shape characteristics.

  Next, a manufacturing process of the packaged semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2 to 4 are process diagrams schematically showing a part of the manufacturing process of the packaged semiconductor device shown in FIG. In these drawings, the same or equivalent components as those shown in the drawings already described are denoted by the same reference numerals. In the packaged semiconductor device shown in FIG. 1, the completed product is shown as an individual piece. However, in manufacturing, a large number of devices can be formed on a large multifaceted panel. In consideration of this point, FIGS. 2 to 4 show one portion on the panel.

  It demonstrates from FIG. FIG. 2 shows a manufacturing process of a portion centering on the insulating resin layer 11 in each configuration shown in FIG. First, as shown in FIG. 2 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. It is formed in a bump shape (bottom diameter, eg, 150 μm, height, eg, 130 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. Although printed on the lower surface of the metal foil 22A for convenience of explanation, the upper surface may be used. After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 2B, an FR-4 prepreg 11A having a thickness of, for example, 60 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). Subsequently, as shown in FIG. 2 (c), a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating resin layer 11.

  Next, as shown in FIG. 2D, the metal foil 22A on one side is subjected to patterning by, for example, well-known photolithography, and this is processed into a wiring pattern 22 including connection pads for flip-connecting the semiconductor chip 41. To do. Subsequently, as shown in FIG. 2E, cream solder 45 </ b> A is applied and deposited on the connection pads of the wiring pattern 22 by, for example, screen printing.

  As the cream solder 45A, a solder powder having a composition of Sn—Ag—Cu, for example, can be used. As a volume composition ratio with a flux as a medium in which the solder powder is dispersed, for example, 20% metal, flux A composition with an increased flux component such as 80% is useful. With such a composition ratio, the metal atoms of the metal bumps (gold bumps) 42 formed on the semiconductor chip 41 diffuse into the solder component and cause the shape to collapse during soldering. It can be effectively prevented.

  Next, for example, by using a mounter, the semiconductor chip 41 having the metal bumps 42 formed on the functional surface thereof is opposed to the metal bumps 42 on the connection pads formed by the wiring pattern 22 through the cream solder 45A. Placed on. The height of the metal bump 42 is set with the intention of providing a gap between the semiconductor chip 41 and the insulating resin layer 11 so that the resin material can easily enter the deformation, by adding the thickness of the wiring layer 22. deep. The ease of deformation entry is also related to the size of the semiconductor chip 41 and the formation pitch of the metal bumps 42.

  According to experiments, for example, if the size of the semiconductor chip 41 is about 1 mm square to 2 mm square and the metal bumps 42 are roughly arranged with a pitch of about 200 μm, the height of the metal bumps 42 is about 20 μm in time. . In this case, the metal bumps 42 can be Au bumps by plating. When the formation pitch of the metal bumps 42 is densely arranged at about 100 μm, it is appropriate to set the height of the metal bumps 42 to, for example, about 50 μm to 80 μm. As the metal bump 42 in this case, a stud formed by wire bonding technology can be easily used.

  In general, a mounter cannot place components as accurately as a flip chip bonder in terms of placement position accuracy, but the arrangement pitch of terminal pads (and hence metal bumps 42) of the semiconductor chip 41 is relatively wide. Under such conditions, the problem is small even with the mounter. An example of the semiconductor chip 41 having a relatively wide terminal pad arrangement pitch is a semiconductor chip for a non-contact data carrier (also referred to as an electronic tag, IC tag, RFID, or the like) having an extremely small number of terminals. . When a mounter can be used instead of a flip chip bonder for mounting the semiconductor chip 41, the cost reduction effect is great.

  After the semiconductor chip 41 is placed, a heating process is performed using, for example, an oven, the cream solder 45A is reflowed, and electrical and mechanical connection between the metal bump 42 and the connection pad by the wiring pattern 22 is performed. Establish. When the solder powder 45A has a solder powder particle size as small as about 5 μm to 10 μm, the spread of the solder is controlled and good solder connection is easily obtained, and connection with little damage to the wiring pattern 22 is obtained. It is done.

  As a result, as shown in FIG. 2F, the laminated member 1 is obtained in which the semiconductor chip 41 is electrically and mechanically connected to the connection pads formed by the wiring pattern 22 on the insulating resin layer 11 by flip connection. be able to. The subsequent steps using the laminated member 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 3 shows a manufacturing process of a part centering on the insulating resin layer 13 and 12 among the components shown in FIG. First, as shown in FIG. 3A, for example, an FR-4 insulating resin layer 13 having a thickness of 150 μm is prepared, and a semiconductor chip opening 71 is formed in a portion corresponding to the semiconductor chip 41 to be embedded.

  Subsequently, as shown in FIG. 3B, the FR-4 prepreg 12A (nominal thickness, for example, 60 μm) to be the insulating resin layer 12 is laminated on the insulating resin layer 13 in which the opening 71 is formed. To do. In the prepreg 12A, an opening corresponding to the semiconductor chip 41 to be embedded, which is the same as the insulating resin layer 13, is provided in advance. Alternatively, the following procedure may be used. Before forming the opening 71, the insulating resin layer 13 and the prepreg 12A (without opening) are laminated, and thereafter, the opening of the semiconductor chip 41 is simultaneously formed in the insulating resin layer 13 and the prepreg 12A. Let the laminated member obtained by the above be the laminated member 2. FIG.

  Next, a description will be given with reference to FIG. FIG. 4 is a diagram showing an arrangement relationship in which the laminated members 1 and 2 obtained as described above are laminated. Here, the upper laminated member 3 in the figure is a laminated body of a prepreg 14A (nominal thickness, for example, 60 μm) to be the insulating resin layer 14 and a metal foil (dummy copper foil) 25A. The prepreg 14 </ b> A side of the laminated body is disposed to face the laminated member 2. The metal foil 25A is removed, for example, by etching after the lamination shown in FIG. The metal foil 25A is a dummy foil for preventing the laminated press plate (not shown) and the prepreg 14A from adhering in the laminating step.

  Each of the laminated members 1, 2, and 3 is arranged in the arrangement as shown in FIG. 4 and is pressed and heated by a press. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12A and 14A obtained by heating, the prepreg 12A or 14A enters the space around the semiconductor chip 41 (including between the semiconductor chip 41 and the insulating resin layer 11), and the gap is Does not occur. That is, the entire semiconductor chip 41 is embedded in close contact with the resin material of the insulating resin layers 12 and 14 derived from the prepregs 12A and 14A.

  In this laminating step, the intermediate laminating member 2 has the cured insulating resin plate 13, so that the insulating resin plate 13 has a function of securing the vertical region of the semiconductor chip 41. Therefore, it is possible to prevent an excessive pressure from being applied to the semiconductor chip 41 during stacking. Therefore, the thickness of the insulating resin plate 13 can actually be set according to the thickness of the semiconductor chip 41 so that an excessive pressure is not applied during the lamination.

  More specifically, the stacking process shown in FIG. 4 can be performed by aligning, for example, by mass lamination or pin lamination. Maslamation is a process of laminating the inner layer conductor pattern on the recognition mark. This recognition mark is provided on the laminated members 1 and 2, for example, outside the region that is separated into pieces and remains as a product. Good. In pin lamination, a hole can be made in this recognition mark, and a pin can be inserted and aligned.

  After the laminating step shown in FIG. 4, the metal foil 25A on the upper surface is removed by etching, the metal foil 21A on the lower surface is patterned in a predetermined manner using well-known photolithography, and layers of solder resists 61 and 62 are formed. Thus, a packaged semiconductor device as shown in FIG. 1 can be obtained. In FIG. 4, the insulating resin layer 11 corresponds to a first insulating plate, and the prepreg 12A, the insulating resin layer 13, and the prepreg 14A correspond to a second insulating plate, respectively.

  Next, a packaged semiconductor device according to another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing the configuration of a packaged semiconductor device according to another embodiment. Components that are the same as or equivalent to those in the already described drawings are given the same reference numerals. is there. The description is omitted unless there is a matter to be added.

  This embodiment has a configuration in which the insulating resin layer 14 in the packaged semiconductor device shown in FIG. 1 is omitted. Therefore, the packaged semiconductor device can be made thinner than the packaged semiconductor device shown in FIG.

  FIG. 6 is a process diagram schematically showing a part of the manufacturing process of the packaged semiconductor device shown in FIG. 5 in a cross section, and shows a stage (stacking process) corresponding to FIG. 4 in the previous embodiment. As shown in FIG. 6, even in a laminated layer without the prepreg 14 </ b> A on the upper side, due to the fluidity of the prepreg 12 </ b> A, the space around the semiconductor chip 41 (including between the semiconductor chip 41 and the insulating resin layer 11) The prepreg 12A is deformed and no gap is generated. That is, the entire semiconductor chip 41 is embedded in close contact with the resin material of the insulating resin layer 12 derived from the prepreg 12A.

  However, the back surface (surface opposite to the functional surface) of the semiconductor chip 41 is a region where the flow and deformation of the prepreg 12A reach the latest, and in some cases, the entire region of the back surface may not be reached. However, even in that case, the electrical and mechanical connection portions between the semiconductor chip 41 and the wiring pattern 22 are completely sealed, and the reliability is not greatly impaired. In order to prevent the laminated press plate (not shown) and the prepreg 12A from adhering in the laminating step, for example, laminating a release sheet on the laminated member 2 side of the laminated press plate, Thereafter, the release sheet may be peeled off.

  Next, a packaged semiconductor device according to still another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing the configuration of a packaged semiconductor device according to still another embodiment. Components that are the same as or equivalent to those shown in the already described drawings are denoted by the same reference numerals. It is. The description is omitted unless there is a matter to be added.

  In this embodiment, a semiconductor chip for a non-contact data carrier is provided as the embedded semiconductor chip 410 in particular. The inner wiring pattern 22 and the wiring pattern 21 on the lower surface form a spiral antenna conductor pattern. That is, this is a form in which the added value is increased so as to function as a non-contact data carrier. This application, as shown, there is no need to provide an external connection terminal anywhere, including on the lower surface.

  The non-contact data carrier semiconductor chip 410 includes a communication circuit unit (not shown) and a memory unit (not shown) as main internal components. The communication circuit unit is connected to the antenna conductor pattern, thereby receiving an external data read command signal and mediating output of data stored in the memory unit in response thereto.

  More specifically, the antenna conductor pattern including the wiring patterns 21 and 22 has the following configuration. That is, the terminal (metal bump 42) on the left side of the semiconductor chip 410 as a starting point is used as an inner peripheral end of the spiral to go to the outer peripheral end with the wiring pattern 22, and from the outer peripheral end to the wiring pattern 21 with the interlayer connector 31. Then, the conduction point circulates to the inner peripheral end by the wiring pattern 21 as the outer peripheral end of the spiral in the same direction as the wiring pattern 22, and the semiconductor chip 410 is illustrated from the inner peripheral end through the interlayer connector 31 and the wiring pattern 22. It is a conductor pattern that ends at the right terminal. Such wiring patterns 21 and 22 can be easily formed by the patterning technique for the metal foils 21A and 22A as described above.

  Although the antenna conductor pattern of this embodiment is provided on the two wiring layers 21 and 22, the antenna conductor pattern may be formed only on one of the wiring layers 21 and 22. Alternatively, taking advantage of the characteristics of the packaged semiconductor device as a wiring board, an insulating resin layer, a wiring layer, and an interlayer connector that penetrates the insulating resin layer may be further provided on the lower side of the insulating resin layer 11 to make a multilayer structure. It is also possible to form an antenna conductor pattern with an increased number of spirals.

  Next, a packaged semiconductor device according to still another embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view schematically showing a configuration of a packaged semiconductor device according to still another embodiment. In the figure, the same or equivalent components as those already described are denoted by the same reference numerals. The description is omitted unless there is a matter to add to that portion.

  In this embodiment, holes 61h and 11h are provided in the solder resist 61 and the insulating resin layer 11, respectively, so as to face the functional surface of the semiconductor chip 41 (surface on the side having terminal pads). These holes 61h and 11h communicate with each other, whereby a part of the insulating resin layer 12 is exposed to the outside air.

  FIG. 9 is a process diagram schematically showing a part of the manufacturing process of the packaged semiconductor device shown in FIG. 8 in a cross section, and shows a stage corresponding to FIG. 4 in the previous embodiment. With reference to FIG. 9, the significance and effect of providing the hole 11h in the insulating resin layer 11 will be described. As shown in FIG. 9, at the stage of this lamination process, through-holes (communication holes 11h and 21h) are formed in the insulating resin layer 11 and the metal foil 21A as the laminated member 1A. These holes 11h and 21h can be provided at the stage of FIG. 2 (c) or FIG. 2 (d) with reference to FIG.

  Then, by performing the laminating process as shown in FIG. 9, the fluidized prepreg 12 </ b> A can easily spread between the semiconductor chip 41 and the insulating resin layer 11, and the effect of filling this space can be enhanced. This is because even if a void is formed, the void communicates with the outside world and the void is less likely to be confined. Therefore, the possibility that a gap remains between the semiconductor chip 41 and the insulating resin layer 11 and the reliability deteriorates can be reduced. Returning to FIG. 8, the hole 61 h provided in the solder resist 61 is because the layer of the solder resist 61 is formed avoiding the position of the hole 11 h provided in the insulating resin layer 11. Additional features of this embodiment can also be applied to the above-described embodiments.

  Next, a packaged semiconductor device according to still another embodiment of the present invention will be described with reference to FIG. FIG. 10 is a cross-sectional view schematically showing a configuration of a packaged semiconductor device according to still another embodiment. In the figure, the same or equivalent components as those already described are denoted by the same reference numerals. The description is omitted unless there is a matter to add to that portion.

  This packaged semiconductor device uses a form in which a semiconductor chip 41 is embedded by utilizing the wiring board technology, and in addition to the semiconductor chip 41, a surface-mounted passive element component 43 is also embedded. By burying such passive element parts 43, added value as a packaged semiconductor device is increased. As the passive element component 43, for example, a bypass capacitor (decoupling capacitor), a damping resistor, a pull-up or pull-down resistor, and the like can be considered.

  It is obvious that such a form can be easily manufactured as an application thereof by referring to the steps already described (FIGS. 2 to 4). Therefore, the details of the manufacturing process are omitted. Generally, the passive element component 43 is a component having a planar size of, for example, 0.6 mm × 0.3 mm (0603), has terminals 43 a at both ends, and the lower side thereof is a land for connection by the wiring layer 22. Opposite the position. The terminal 43 a of the passive element component 43 and the connection land are electrically and mechanically connected in advance by the solder 46. Additional features of this embodiment can also be applied to the above-described embodiments.

  DESCRIPTION OF SYMBOLS 1, 1A ... Laminated member, 2 ... Laminated member, 3 ... Laminated member, 11 ... Insulating resin layer, 11A ... Prepreg, 11h ... Hole, 12 ... Insulating resin layer, 12A ... Prepreg, 13 ... Insulating resin layer, 14 ... Insulating Resin layer, 14A ... prepreg, 21 ... wiring layer (wiring pattern), 21A ... metal foil (copper foil), 21h ... hole, 22 ... wiring layer (wiring pattern), 22A ... metal foil (copper foil), 25A ... metal Foil (dummy copper foil), 31 ... interlayer connection (conductive bump by conductive paste printing), 41 ... semiconductor chip, 42 ... metal bump, 43 ... passive element component (chip capacitor), 43a ... terminal, 45 ... solder 45A ... Cream solder, 46 ... Solder, 61, 62 ... Solder resist, 61h ... Hole, 71 ... Opening for semiconductor chip, 410 ... Semiconductor chip for non-contact data carrier.

Claims (9)

A bare semiconductor chip having a functional surface and a back surface facing the functional surface;
Metal bumps provided on the functional surface of the semiconductor chip and having a height of 20 μm to 80 μm and a forming pitch of 200 μm to 100 μm;
A wiring pattern including a pad located opposite to the metal bump;
Solder for electrically and mechanically connecting the pads of the wiring pattern and the metal bumps;
A first resin layer which is located on the wiring pattern on the side where the semiconductor chip of the wiring pattern is located and embeds the semiconductor chip so as to be in close contact with the functional surface and the back surface of the semiconductor chip When,
A packaged semiconductor comprising: a second resin layer positioned in a stacked manner with respect to the first resin layer via the wiring pattern so that the wiring pattern is an inner wiring layer apparatus.   A side of the first resin layer opposite to a side where the second resin layer is located and a side of the second resin layer where the first resin layer is located; 2. The packaged semiconductor device according to claim 1, further comprising a solder resist layer on the second resin layer on the opposite side.   The packaged semiconductor device according to claim 2, wherein the wiring pattern includes an antenna conductor pattern.   4. The packaged semiconductor device according to claim 3, wherein the second resin layer has a hole formed toward the functional surface of the semiconductor chip.   The packaged semiconductor device according to claim 4, wherein the first resin layer further embeds a passive element component. Patterning a metal foil laminated on the first surface of a first resin plate having a first surface and a second surface, and forming a wiring pattern including connection pads for a semiconductor chip;
A step of depositing a solder paste on the connecting pads,
A semiconductor chip having a functional surface having a terminal pad and a back surface opposite to the functional surface, wherein a metal bump having a height of 20 μm to 80 μm and a forming pitch of 200 μm to 100 μm is formed on the terminal pad; On the first surface of the first resin plate, the metal bumps are arranged so as to face the connection pads, and are electrically and mechanically connected and fixed by solder derived from the cream solder. Process,
The second surface is formed so that the functional surface and the back surface of the semiconductor chip are in close contact with the resin material of a second resin plate made of a resin material, which is a resin plate different from the first resin plate. A packaged semiconductor device comprising: embedding the entire semiconductor chip in the resin plate, and integrating the second resin plate in a stacked manner on the first resin plate. Manufacturing method. As the state before the second resin plate is integrated with the first resin plate, a semi-cured prepreg and a cured resin plate after curing having an opening at a position corresponding to the semiconductor chip And a laminated member,
The method of manufacturing a packaged semiconductor device according to claim 6, wherein the step of integrating is a step of laminating a surface of the prepreg of the second resin plate on the first resin plate. . As a state before the second resin plate is integrated with the first resin plate, a semi-cured first prepreg and a cured state curing having an opening at a position corresponding to the semiconductor chip. It is a resin plate having a laminated member with a rear resin plate, and a second prepreg in a semi-cured state, which is positioned on the side of the cured resin plate of the laminated member,
The packaged semiconductor device according to claim 6, wherein the step of integrating is a step of laminating a surface of the first prepreg of the second resin plate on the first resin plate. Manufacturing method.   The said 1st resin board has a through-hole in the area | region where the said semiconductor chip should be located as a state before the said semiconductor chip is fixed. A method of manufacturing a packaged semiconductor device.

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