JP5587562B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device that performs a read / write operation in a pipeline manner in synchronization with a clock signal, and is applied to, for example, a synchronous DRAM (dynamic random access memory) or a double data rate synchronous DRAM. Related to effective technology.

In recent years, with the rapid improvement of the operating frequency of processors, the demand for DRAM has not only shortened the access time but also the demand for higher data transfer speed. Along with this, a synchronous DRAM that operates in synchronization with a clock signal (hereinafter abbreviated as a clock) has been developed, and DDR (Double Data Rate) that inputs and outputs data at the rising and falling edges of the clock for further higher speed. A synchronous DRAM of the type has been proposed and is becoming the mainstream of DRAM.

  FIG. 29 shows a general configuration of a conventional double data rate synchronous DRAM, FIG. 30 shows a timing chart at the time of reading, and FIG. 31 shows a timing chart at the time of writing. The double data rate synchronous DRAM having such a structure is disclosed in pages 1999 to 413 (1999 IEEE Internal Solid-State Circuit Conferencing WP24.2 ", 1999 IS C. Digest of Technical Papers. A 2.5V 333 Mb / s / pin 1 Gb Double Data Rate SDRAM ", p.412-p.413).

  A conventional semiconductor memory device shown in FIG. 29 includes a memory cell array 123, an address buffer 101 that latches an externally input address, an address register 103 that latches an address fetched by the address buffer 101, and a row address. The row address decoder 109 for selecting the word line by decoding the column address, the column address decoder 116 for selecting the bit line by decoding the column address, and the row address decoder 109 receiving the output of the address buffer 101 A row address latch 104 for transmitting information, a column address counter 111 for changing a column address internally, a column address latch 110 for receiving the output of the address buffer 101 and transmitting the column address to the column address counter 111, and an external control signal Receive A command decoder 102 that generates an internal control signal, an output buffer 120 that outputs data read from the memory cell array 123 to the outside, and an output clock generation circuit that controls the timing of data output from the output buffer 120 119, an input buffer 121 that receives externally input data, and a read that transmits data read from the memory cell array 123 to the output buffer 120 or writes data from the input buffer 121 to the memory cell 123 / Write circuit 117 and the like. One of the features of the synchronous DRAM is that CAS latency (the number of clock cycles from when a column address is fetched until read data is output) can be set by a command code (hereinafter simply referred to as a command). .

  A data read operation in the DRAM of FIG. 29 will be described with reference to FIG. FIG. 30 shows that the number of clock cycles (tRCD) from the ACTV command instructing operation start to the READ command or WRITE command instructing reading or writing (hereinafter referred to as a column command when both commands are not distinguished) is two cycles. It is a timing chart in case CAS latency CL is 2 cycles. As shown in FIG. 30, at the same time when the ACTV command is input, the row address is fetched from the address buffer 101 and latched in the address register 103 by ACLK output from the command decoder 102 in response to the ACTV command. The Further, the row address is latched in the row address latch 104 by the clock RCLK output from the command decoder 102 in response to the ACTV command. Thereafter, the row address signal is decoded by the row decoder 109 to select a word line corresponding to the value of the row address. When the word line is selected, data is output from the memory cell connected to the selected word line to the bit line. When data is sufficiently output to the bit line, the sense amplifier is activated and the bit line potential is amplified.

  A READ command is input two cycles after the ACTV command is input. At the same time, the column address is taken in from the address buffer 101 and latched in the address register 103 by the clock ACLK output from the command decoder 102 in response to the READ command. Further, the column address is latched in the column address latch 110 by the clock YCLK 1 output from the command decoder 102 in response to the READ command. Thereafter, the column address signal passes through the column address counter 111 and is decoded by the column decoder 116 to select a bit line corresponding to the value of the column address. At this time, the bit line is sufficiently amplified by the sense amplifier is a condition for selecting the bit line. After the bit line is selected, the data on the bit line passes through the read circuit 117 and is output from the output buffer 120 to the outside. At this time, the timing at which the read data is output to the outside from the output buffer 120 is determined by QCLK1 generated from the output clock generation circuit 119. In the double data rate synchronous DRAM, 2n-bit data, which is twice the number of output bits (n), is read from the read circuit 117 to the output buffer 120, and is synchronized with the rising and falling edges of the clock. Thus, data is output every n bits. In FIG. 30, two column decoder inputs and two column select signals are shown when a continuous address is generated by the column address counter 111 in a burst mode or the like and a read operation is performed based thereon. Because it is.

  FIG. 31 shows a timing chart at the time of data writing when tRCD is 2 cycles and CAS latency is 2 cycles in the DRAM of FIG. As shown in FIG. 31, at the time of writing, an ACTV command is input, and at the same time, a row address is taken in, a row address is decoded by a row decoder 109, a word line is selected, and data in a memory cell is stored. Output to the bit line. When the bit line is sufficiently opened, the sense amplifier is activated and the bit line potential is amplified.

  In addition, a WRITE command is input after two cycles from the input of the ACTV command, and the column address is taken in at the same time as the WRITE command is input. Thereafter, the column address is decoded and the bit line is selected in the same manner as in reading. Write data is fetched from the outside in (CAS latency-1) = 1 cycle after the WRITE command is input. At this time, in the double data rate synchronous DRAM, n bits of write data are taken in by the input buffer 121 at both rising and falling edges of the clock, and are sent to the memory cell array 123 through the write circuit 117 as 2n bits. Then, data is written into the memory cell through the selected bit line.

1999 IS C. Sea Digest of Technical Papers, pages 412 to 413 (1999 IEEE Internal Solid-State Circuit Conference WP24.2 “A 2.5V 333 Mb / s / pin 1 Gb Double D DRAM D , P.412-p.413)

The double data rate synchronous DRAM described above has the advantage of improving the data transfer speed because it outputs the read data and takes in the write data at both the rising and falling edges of the clock. As shown in FIG. 30 and FIG. 31, one cycle is free from ACTV command input to column command input, so the command transfer efficiency is low, and the CPU that outputs the command waits for one cycle after the ACTV command is output. Since the column command is output after that, there is a problem that the performance of the entire system is not sufficiently improved.

  In view of this, a synchronous DRAM in which the column command input timing after input of the ACTV command is input one cycle ahead of time was studied. By moving the column command input timing forward by one cycle, the CPU can shift to another process earlier by one cycle, which has the advantage of improving the performance of the entire system. In addition, in this case, it is possible to cope with various systems by making the forward latency variable.

  However, it has been found that such a double command rate synchronous DRAM having a configuration as shown in FIG. 29 is impossible to realize the column command advance input. Specifically, when the READ command is input in advance, the column address is also input in advance, and the bit line is selected before the bit line data is amplified by the sense amplifier. As a result, correct data cannot be read. Further, when the WRITE command is put forward, the bit line is selected before correct write data is input to the write circuit, and correct data is not written.

  An object of the present invention is to provide a clock synchronous semiconductor memory device capable of reading and writing correct data even when a read command or a write command is input in advance and a column address is input in advance. .

  Another object of the present invention is to provide a clock synchronous semiconductor memory device capable of shortening cycle time and increasing data transfer speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  In order to achieve the above object, a semiconductor memory device according to the present invention can set a value (forward latency) for designating a read or write command input cycle in a semiconductor memory such as a double data rate synchronous DRAM. A timing adjusting register for providing a register and delaying a signal by a predetermined cycle time in accordance with the advance latency set in the register on a column address signal path between the column address latch circuit and the column decoder It was made to provide.

  That is, a memory cell array having a word line and a bit line to which a memory cell is connected, a row address latch circuit for latching a row address inputted from the outside, and selecting a word line in the memory cell array by decoding the row address A row decoder for latching, a column address latch circuit for latching a column address inputted from the outside, a column decoder for decoding a column address and selecting a bit line in the memory cell array, and data read from the memory cell array An output buffer for outputting data to the outside, an input buffer for capturing data input from the outside, and a first register capable of setting values for specifying the data fetch timing and the data output timing in the input buffer and the output buffer; The input buffer and the output buffer In a semiconductor memory device configured to determine an operation timing according to a value set in the first register, a value that can specify a data read command or write command input timing can be set. 2 registers, and on the column address signal path between the column address latch circuit and the column decoder, the signal is delayed by a predetermined time according to the value set in the second register. A timing adjustment circuit is provided.

  According to the above means, the timing adjustment circuit can control the propagation delay time of the column address signal in accordance with the value set in the second register (column command advance latency value). Even when a column address is fetched ahead of time when a command (column command) is thrown forward, the bit line is selected by the column address decoder in accordance with the timing at which the potential of the bit line is amplified, and correct data is obtained. Can be read out. Furthermore, after the write data is taken in by the input buffer, the bit line is selected, and correct data can be written to the memory cell connected to the selected word line.

  Further, even if the value (CAS latency) set in the first register is changed, the value set in the second register (column command advance latency value) is set independently. Since the adjustment circuit is also controlled independently, correct operation is guaranteed. Further, even when the setting value (CAS latency) of the first register is not changed and the setting value of the second register (column command advance latency value) is changed, the setting value (CAS latency) of the first register is changed. The timing adjustment circuit that is controlled independently from each other adjusts the propagation delay time of the column address signal and adjusts the bit line in accordance with the timing at which the potential of the bit line is amplified and the timing at which write data is input. Because it can be selected, correct operation is guaranteed.

  Preferably, a circuit for generating an internal control signal used for controlling an internal circuit based on a control signal supplied from the outside, and a predetermined cycle time according to a value set in the second register A delay control circuit for delaying the internal control signal, and the timing adjustment circuit is controlled by the internal control signal adjusted by the delay control circuit to adjust the timing of the column address signal. . As a result, a signal for controlling the timing adjustment circuit can be systematically generated efficiently.

  Furthermore, preferably, a circuit for generating a signal for giving an operation timing of the output buffer based on the internal control signal is provided, the circuit being controlled by the internal control signal generated by the delay control circuit, The signal generated according to the value set in the register is configured to be delayable. As a result, the circuit for generating the signal for giving the operation timing of the timing adjustment circuit and the output buffer can be controlled by the common signal, and the configuration of the control circuit can be simplified.

  The position of the timing adjustment circuit may be anywhere between the column address latch circuit and the column decoder, but a column address counter that automatically updates the column address latched by the column address latch circuit is provided. When provided, the timing adjustment circuit is preferably provided on a column address signal path between the column address counter and the column decoder or between the column address latch circuit and the column address counter. Thereby, in the semiconductor memory device operating in synchronization with the clock, the cycle time can be shortened by distributing and executing the address latch and address update operation and the column address decoding operation in different cycles.

  In addition, a plurality of spare memory columns that can be replaced with normal memory columns of the memory cell array, a relief address storage circuit capable of storing addresses of defective memory columns, an input column address, and a relief address storage circuit In the case of further comprising: an address comparison circuit that compares the stored address; and a redundant column decoder that decodes a signal based on the comparison result of the address comparison circuit and selects one of the spare memory columns. The address comparison circuit is configured to compare the address output from the column address counter with the address stored in the relief address storage circuit, and on the signal path between the address comparison circuit and the redundant column decoder. A second timing adjustment circuit may be provided. By providing the second timing adjustment circuit, it is possible to more optimally control the transmission timing of the column address signal. In the semiconductor memory device operating in synchronization with the timing clock, the address latch and address update operations, By performing the address comparison operation and the column address decoding operation separately in different cycles, the cycle time can be shortened.

  Further, in the case where a column predecoder for predecoding the column address is provided in the previous stage of the column decoder, the timing adjustment circuit is provided between the column address counter and the column predecoder, and the second timing adjustment. The circuit is provided between the column address comparison circuit and the column predecoder. The closer the number of timing adjustment circuits to the column decoder, the greater the number. However, with such a configuration, the cycle time can be shortened without increasing the circuit scale of the timing adjustment circuit.

  However, in the case where a column predecoder for predecoding the column address is provided in the previous stage of the column decoder, the timing adjustment circuit is provided between the column predecoder and the column decoder, and the second timing adjustment circuit is provided It is also possible to provide each between the column address comparison circuit and the column decoder. The closer the timing adjustment circuit is to the column decoder, the easier it is to distribute the optimal operation. With this configuration, the circuit scale is somewhat larger, but the cycle time can be further reduced.

  Further, a plurality of spare memory columns that can be replaced with normal memory columns of the memory cell array, a relief address storage circuit capable of storing addresses of defective memory columns, an input column address, and the relief address storage circuit The column address latch further comprising: an address comparison circuit that compares the stored address; and a redundant column decoder that decodes a signal based on the comparison result of the address comparison circuit and selects one of the spare memory columns. The third timing adjustment circuit may be provided between the circuit and the address comparison circuit. As a result, more optimal operation distribution can be performed, and the cycle time can be further shortened.

  Further, in the case of a semiconductor memory device that operates based on an externally supplied command, the value set in the second register is set ahead of the read or write command that is input after the operation start command is input. It is a value that specifies the number of cycles to be input to. This makes it possible to shorten the cycle time in a clock synchronous memory such as an existing double data rate synchronous DRAM.

  Further, the value set in the second register is based on the state of the terminal to which an external address is input when the command supplied from outside instructs the setting in the second register. Configure to be set. This makes it possible to set the second register without providing any new external terminal.

  Preferably, the timing adjustment circuit has a delay path having a signal delay means, a through path for directly outputting an input signal without the signal delay means, and a value set in the second register. In response to this, switching means for switching which of the plurality of paths the input signal is passed through is constituted. As a result, a timing adjustment circuit that can be easily controlled with a relatively simple circuit configuration can be realized.

  More preferably, a master / slave latch means that operates in accordance with the internal control signal is arranged in the delay path having the signal delay means of the timing adjustment circuit. As a result, it is possible to reliably prevent the input signal from slipping from the input terminal to the output terminal of the timing adjustment circuit due to the cue of the clock signal for controlling the circuit and the like and the desired delay cannot be obtained.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to realize a clock synchronous semiconductor memory device capable of reading and writing correct data even when a read command and a write command are input in advance and a column address is input in advance. Can do. In addition, a clock synchronous semiconductor memory device that can shorten the cycle time and increase the data transfer rate can be realized.

1 is a block configuration diagram showing an embodiment of a double data rate synchronous DRAM as an example of a semiconductor memory device to which the present invention is applied. FIG. 2 is a circuit configuration diagram illustrating a configuration example of a delay control circuit illustrated in FIG. 1. 3 is a timing chart showing timings of input / output signals of the delay control circuit shown in FIG. 2. It is a circuit diagram which shows the specific example of a column address latch. FIG. 3 is a circuit configuration diagram of a clocked inverter constituting a column address latch and the like. FIG. 2 is a circuit diagram showing a specific example of a timing adjustment circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing another configuration example of the timing adjustment circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a third configuration example of the timing adjustment circuit shown in FIG. 1. It is a circuit diagram which shows one structural example of a timing variable circuit. In the double data rate synchronous DRAM of the embodiment shown in FIG. 1, main signals at the time of read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 0 cycle. It is a timing chart. FIG. 11 is a timing chart of main signals inside the write operation of the double data rate synchronous DRAM of the embodiment under the same conditions as FIG. 10. In the double data rate synchronous DRAM of the embodiment of FIG. 1, the timing of main signals in the read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 1 cycle. It is a chart. FIG. 13 is an internal main signal timing chart during the write operation of the double data rate synchronous DRAM of the embodiment under the same conditions as FIG. 12. In the double data rate synchronous DRAM of the embodiment of FIG. 1, tRCD is 2 cycles, CAS latency is 2 cycles, column command advance latency (AL) is 0 cycle (A) and 1 cycle (B). It is a timing chart which shows the operation | movement order of the main circuits at the time of read-out operation | movement. When the time from the ACTV command to the amplification of the bit line is short, the main circuit operation during the read operation when the column command advance latency (AL) is 0 cycle (A) and 1 cycle (B) It is a timing chart which shows an order. FIG. 3 is a command configuration diagram illustrating a relationship between a command type and a command code in the double data rate synchronous DRAM of the first embodiment. In the double data rate synchronous DRAM of the first embodiment, an example (A) of values set by an extended mode register set command and an example (B) of values set by a mode register set command are shown. It is explanatory drawing. It is a block block diagram which shows 2nd Embodiment of the double data rate synchronous DRAM to which this invention is applied. In the double data rate synchronous DRAM shown in FIG. 18, a timing chart of main signals at the time of read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 1 cycle. It is. It is a block block diagram which shows 3rd Embodiment of the double data rate synchronous DRAM to which this invention is applied. In the double data rate synchronous DRAM shown in FIG. 20, the timing chart of main signals at the time of read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 1 cycle. It is. It is a block block diagram which shows 4th Embodiment of the double data rate synchronous DRAM to which this invention is applied. In the double data rate synchronous DRAM shown in FIG. 22, a timing chart of main signals during a read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 1 cycle. It is. It is a block block diagram which shows 5th Embodiment of the double data rate synchronous DRAM to which this invention is applied. In the double data rate synchronous DRAM shown in FIG. 24, a timing chart of main signals at the time of read operation when tRCD is 2 cycles, CAS latency is 2 cycles, and column command advance latency (AL) is 2 cycles. It is. FIG. 25 is a circuit diagram showing a specific configuration example of a delay control circuit in the embodiment of FIG. 24. It is a block block diagram which shows 6th Embodiment of the double data rate synchronous DRAM to which this invention is applied. In the double data rate synchronous DRAM shown in FIG. 27, the main signals in the read operation when tRCD is 2 cycles, CAS latency is 2 cycles, column command advance latency (AL) is 1.5 cycles. It is a timing chart. It is a block diagram which shows schematic structure of the conventional double data rate synchronous DRAM. FIG. 30 is a timing chart of main signals in a read operation when tRCD is 2 cycles and CAS latency is 2 cycles in the conventional double data rate synchronous DRAM shown in FIG. 29. FIG. FIG. 31 is a timing chart of main signals inside a write operation of a conventional double data rate synchronous DRAM under the same conditions as FIG. 30. FIG.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor memory device according to the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a first embodiment of a double data rate synchronous DRAM to which the present invention is applied.

  The DRAM of FIG. 1 includes, for example, a memory cell array 123 having a storage capacity of 256 megabits, for example, consisting of four banks in which a plurality of memory cells are arranged in a matrix, and address data (hereinafter referred to as addresses) input from the outside. Abbreviated) in the multiplex system, an address register 103 that latches the address fetched by the address buffer 101, and a row that latches a row address among the addresses latched in the address register 103 An address latch 104, a row relief address storage circuit 106 that stores a relief address of a row address using a fuse, a row address comparison circuit 105 that compares the relief address with the row address, and a row address pre-decode that predecodes the row address. Deco Decoder 107, redundant row address decoder 108 and row address decoder 109 for decoding a row address and selecting a corresponding word line in memory array 123, and a column address among the addresses latched in address register 103. The column address latch 110, the column address counter 111 that automatically updates the latched column address internally, the column relief address storage circuit 113 that stores the relief address of the column address, and the relief address and the column address are compared. Column address comparison circuit 112, column address predecoder 114 for predecoding the column address, redundant column address decoder 115 and column address decoder for decoding the column address and selecting a corresponding column (bit line) in memory array 123 116 and the outside A command decoder 102 that receives an input control signal such as a chip select signal / CS and generates an internal control signal, an output buffer 120 that outputs data read from the memory cell array 123 to the outside, and a CAS latency The output register 118 for controlling the timing of sending data to the output buffer 120 according to the value, the output clock generation circuit 119 for controlling the timing of the data output from the output register 118, and the data input from the outside The input buffer 121 to be received, the input register 122 in which the timing for sending the data from the input buffer 121 to the memory cell array 123 is controlled according to the CAS latency value, and the data read from the memory cell array 123 to the output Tell register 118 And a read / write circuit 117 for writing data from the input register 122 to the memory cell 123.

  As a control signal input from the outside to the command decoder 102, a pair of clocks CLK, / CLK and clocks having opposite phases are valid in addition to the chip select signal / CS for selecting the chip. Clock enable signal CKE, row address strobe signal / RAS (hereinafter referred to as RAS signal), column address strobe signal / CAS (hereinafter referred to as CAS signal), write enable signal / WE instructing data write operation, There are a data strobe signal DQS for instructing input / output, a data mask signal DM for prohibiting input / output of data, and the like. Among these signals, those having “/” in front of the sign mean that the low level is an effective level. The command decoder 102 decodes CKE, / CS, / RAS, / CAS, / WE and a part of the address signal among these control signals, understands the input command, and confirms that CAS latency and the like are set. Generating and outputting signals CL and ALE, internal control signals MAE and WBE for giving read / write timing to the read / write circuit 117, a control signal WRE for giving latch timing to the column address latch circuit 110, and the like, and a clock CLK , / CLK, a plurality of types of internal clocks ACLK, BCLK, QCLK, RCLK, DCLK, and YCLK1 to 4 having different phases and periods are generated and supplied to a desired internal circuit. The command decoder 102 is provided with a CL setting register 131 for holding a CAS latency value CL set in accordance with an MRS command for instructing setting of a mode register among input commands.

  Also, in this embodiment, the command decoder 102 sets the column command advance latency of the column command set by the MRS command instructing the setting to the mode register, that is, the normal column command input cycle for the ACTV command before how many cycles. An AL setting register 132 is provided for holding a value AL indicating whether to bring it in.

  Further, an output clock generation circuit 119 configured with a known DLL (Digital Locked Loop) circuit or the like is provided to form a signal QCLK1 that gives latch timing of the output register 118 based on the clock QCLK generated from the command decoder 102. It has been. The DLL circuit includes a variable delay circuit capable of changing a signal transmission delay time, a replica circuit configured so that a delay time is equal to a path of an original read signal, and a phase and a variable delay of an input signal of the variable delay circuit. It is a circuit configured to adjust the delay time of the variable delay circuit so that the phase of the signal that has passed through the circuit is further compared with the phase of the signal that has been delayed through the replica circuit so that the phase matches.

  In this embodiment, a two-input AND gate 133 that receives the signal generated by the output clock generation circuit 119 and the signal ORE1 delayed by the delay control circuit 126 is provided at the subsequent stage of the output clock generation circuit 119. When the signal ORE1 is enabled (high level), the output of the output clock generation circuit 119 is output as QCLK1, and when the ORE1 is disabled (low level), QCLK1 is fixed at the low level. ing.

  Furthermore, in this embodiment, a first timing adjustment circuit 124 for giving a delay according to a set forward latency AL to the preceding stage of the column predecoder 114, the column address comparison circuit 112, and the column A second timing adjustment circuit 125 having a similar function is disposed between the predecoders 114. Further, in order to form signals MAE1, ORE1, and WBE1 that are appropriately delayed from timing control signals MAE, ORE, and WBE output from the command decoder 102 based on the clock YCLK4 and the control signal ALE output from the command decoder 102. The delay control circuit 126 is provided.

  FIG. 2 shows a specific circuit example of the delay control circuit 126.

  The delay control circuit 126 includes 1-bit delay registers 201, 202, and 203, each of which receives signals MAE, ORE, and WBE supplied from the command decoder 102 and uses the internal clock YCLK4 and the signal ALE as control signals. Yes. These registers 201 to 203 are for delaying the input signals MAE, ORE, and WBE, respectively, according to the signal ALE. Among these, the register 201 is a signal as shown in FIG. When ALE is at a low level, that is, when AL is "0", the signal is in a through state and is output as signal MAE1 obtained by slightly delaying input signal MAE. When ALE is at a high level, that is, when AL is "1", input signal MAE is output. Is latched by the clock YCLK4 and output as a signal MAE1 delayed by one clock cycle.

  Further, as shown in (b) of FIG. 3B, when the AL is “0”, the register 202 enters the signal through state and outputs the signal ORE1 obtained by slightly delaying the input signal ORE. Is "1", the input signal ORE is latched by the clock YCLK4 and output as the signal ORE1 delayed by one clock cycle. Since the signal WBE is delayed by the register 203 in the same manner as the signal MAE, the illustration is omitted.

  Further, since the signal OBE1 delayed by the register 202 is input to the input AND gate 133 provided at the subsequent stage of the output clock generation circuit 119, when the AL is "0", the output clock generation circuit The signal generated at 119 is output as a signal QCLK1 slightly delayed, and when AL is “1”, it is output as a signal QCLK1 delayed by one clock cycle. Here, since the input signal QCLK of the output clock generation circuit 119 is a clock, the output signal QCLK1 has a waveform similar to that of the signal MAE1 shown in FIG.

  FIG. 4 shows a specific circuit configuration example of the column address latch circuit 110. Note that the column address latch circuit 110 in FIG. 4 has a configuration corresponding to one address bit, and such circuits are provided for the number of bits of the column address.

  The address latch circuit 110 of FIG. 4 is a master-slave flip-flop composed of a clock latched inverters 602-604 and a master latch LT1 operated by a clock BCLK and a slave latch LT2 composed of clocked inverters 605-607 and operated by a clock BCLK. The latch LT3, which is composed of the FF1 and clocked inverters 609 to 611 and which is operated by the clock YCLK1 with the output of the preceding flip-flop FF1, and the same signal as the input of the flip-flop FF1 is composed of the clocked inverters 612 to 615. The latch LT4 is operated by the clock YCLK1. The output unit is provided with clocked inverters 616 and 617 for selecting and outputting the output signal of the latch LT3 or LT4 according to the control signal WRE from the command decoder 102.

  In the circuit of FIG. 4, 1 bit of the column address is supplied as the input signal IN and is latched in the flip-flop FF1. Since the output is selected in accordance with the level of the control signal WRE, the inverter 616 is enabled and the address latched in the flip-flop FF1 is output at the time of data writing when the control signal WRE is set to the high level. At the time of data reading when the signal WRE is set to the low-high level, the inverter 617 is validated and an address via only the latch LT4 is output. As a result, the column address latch circuit 110 is controlled to transmit the input address to the output terminal OUT at a timing that is one cycle later than that at the time of reading at the time of data writing, that is, one cycle of the clock BCLK.

  In FIG. 4, among the inverters constituting each of the latches LT1 to LT4, 604, 607, 611, and 615 are ordinary two-element CMOS inverters, and the others and the output selection inverters 616 and 617 are clocked inverters. It is. Further, inverters 601, 608, and 612 are for forming a clock having a phase opposite to that of the clocks BCLK and YCLK1 in order to control the clocked inverter, and 618 is for forming a signal having a phase that is opposite to that of the control signal WRE. Each is composed of a normal inverter. FIG. 5 shows a specific example of the clocked inverter used in this embodiment.

  As shown in FIG. 5, the clocked inverter includes P-channel MOSFETs 301 and 302 and N-channel MOSFETs 303 and 304 connected in series between the power supply voltage Vcc and the ground potential GND, and the gate terminals of the MOSFETs 302 and 303. An input signal is applied to the gate terminals of the MOSFETs 301 and 304, and clocks CK and / CK having opposite phases are applied to the gate terminals of the MOSFETs 301 and 304, so that the current is cut off during the high level of the clock CK so that it does not operate as an inverter. Is done. Here, CK corresponds to the clocks BCLK and YCLK1 in the circuit of FIG.

  FIG. 6 shows a specific circuit configuration example of the timing adjustment circuits 124 and 125 in FIG. 6 has a configuration corresponding to one bit of the address, the timing adjustment circuit 124 has the same number of bits as the number of column addresses, and the timing adjustment circuit 125 has the same number of circuits as the number of spare memory columns (32). X4 = 128).

  The timing adjustment circuit shown in FIG. 6 includes clocked inverters 702 and 703 that transmit an input signal IN in a complementary manner by a timing signal ALE, a clocked inverter 704 and an inverter 705, and an input signal IN by a control signal ALE from a command decoder 102. A latch LT11, an inverter 715, a clocked inverter 716, a latch LT12 that latches the input signal IN in a complementary manner to the LT11 by a timing signal ALE, and a first timing for delaying a signal that has passed through the clocked inverter 703 An adjustment delay circuit 717 and a master-slave flip which consists of 706 to 711 and operates according to the clock YCLK3 or YCLK4 to latch the signal delayed by the timing adjustment delay circuit 717 A register 719 comprising a drop, and a second timing adjusting delay circuit 718 for delaying the latched signal in said register 719. The output unit is provided with clocked inverters 712 and 713 that complementarily select and output the output signal of the timing adjustment delay circuit 718 or the clocked inverter 702 according to the control signal ALE.

  The timing adjusting delay circuits 717 and 718 are configured as a circuit having a delay time corresponding to the sum of the gate delay times by connecting a plurality of inverters in series, for example. The delay inverter array is assigned an appropriate number of stages according to the arrangement location of the timing adjustment circuit, the signal type input to the timing adjustment circuit, and the respective cases. Note that the delay registers 201, 202, and 203 shown in FIG. 2 can also be configured by a circuit similar to that shown in FIG.

  In the timing adjustment circuits 124 and 125 in FIG. 6, when AL = 0, ALE is fixed to low, so that the clocked inverters 703 and 712 are disabled by the control signal ALE and the signal ALE obtained by inverting the control signal ALE. Able and clocked inverters 702 and 713 are enabled, the latch state of the node N701 by the latch LT12 is released, a through path directly connecting the inverters 702 and 713 is selected, and the input signal IN is output with almost no delay. The At this time, the clocked inverter 704 is enabled and the node N702 is fixed by the latch LT11.

  On the other hand, when AL = 1, the control signal ALE is fixed high, so that the clocked inverters 702 and 713 are disabled by ALE and a signal obtained by inverting it, and the clocked inverters 703 and 712 are As a result, the latch state of the node N702 by the latch LT11 is released, and the delay side signal path including the timing adjustment delay circuit 717 is selected. At this time, the clocked inverter 716 is enabled and the node N701 is fixed by the latch LT12. When AL = 1, the clock YCLK 3 or YCLK 4 is input from the command decoder 102, and the input signal IN is once latched by the register 719, and is output after being delayed by one cycle of YCLK 3 or YCLK 4. Note that the timing adjustment delay circuits 717 and 718 give a delay so that an optimal timing signal can be obtained in accordance with the respective conditions such as the location of the timing adjustment circuit 124 or 125 and the type of input signal. Configured.

  FIG. 7 shows a second embodiment of a specific circuit of the timing adjustment circuits 124 and 125. The configuration of the timing adjustment circuits 124 and 125 of this embodiment is relatively similar to the configuration of the timing adjustment circuits 124 and 125 of FIG. The difference is that instead of the timing adjustment delay circuits 717 and 718 in FIG. 6, timing variable circuits 817 and 818 capable of adjusting the delay time are used, and the timing variable circuit 817 is arranged not in the subsequent stage of the clocked inverter 703 but in the previous stage. The only difference is that the timing variable circuit 818 is provided not in the preceding stage of the clocked inverter 712 but in the subsequent stage.

  The basic operation is the same as that of the circuit of FIG. 6. When AL = 0, a through path directly connecting the inverters 702 and 713 is selected, and the input signal IN is output with almost no delay. In the case of AL = 1, the input signal IN is once latched by the register 719, and is output after being delayed by one cycle of YCLK3 or YCLK4.

  The timing variable circuits 817 and 818 are configured as shown in FIG. 9, for example. As can be seen from the figure, the timing variable circuits 817 and 818 have a configuration in which one of the register 719 and the timing adjustment delay circuit 717 or 718 in the delay timing adjustment circuits 124 and 125 of FIG. 6 is omitted. ing. As a result, the timing variable circuits 817 and 818 adjust the timing of the input signal in accordance with the state of the control signal ALE, that is, the value of AL, and output it.

  FIG. 8 shows a third embodiment of a specific circuit of the timing adjustment circuits 124 and 125.

  The timing adjustment circuit 124 (125) of this embodiment includes NOR gates 902 and 903 for selecting either the clock YCLK3 (YCLK4) or a signal obtained by inverting the clock YCLK3 (YCLK4) according to the control signal ALE, and the input signal IN. A first timing variable circuit 910 that delays, a register 912 that includes a master-slave flip-flop that latches the output of the timing variable circuit 910, and a second timing variable circuit 911 that delays the output of the register 912. ing. The configuration of the timing variable circuits 910 and 911 can be a circuit having the same configuration as the circuit shown in FIG. 9 used in the embodiment of FIG. In the timing variable circuits 910 and 911, the delay time is adjusted according to the value of AL.

  In the timing adjustment circuit 124 (125) of this embodiment, when AL = 0, since ALE is fixed low, the outputs of NOR902 and NOR903 are fixed high, and the clocked inverter 905 and the clocked inverter 907 are disabled. The clocked inverter 904 and the clocked inverter 909 are enabled, the latches of the nodes N901 and N902 are released, the through path is selected, and the input signal IN is output with almost no delay. On the other hand, when AL = 1, since ALE is fixed high, the outputs of NOR 902 and NOR 903 change according to YCLK 3 and the inverted signal of ALE generated from inverter 901. Since the clock YCLK 3 (YCLK 4) is input from the command decoder 102, the input signal IN is delayed by one cycle and output from the register 912.

  Next, the operation of the DRAM of FIG. 1 will be described. 10 to 13, assuming that the time tRCD from the input of the ACTV command to the input of the column command is 2 cycles and the CAS latency is 2 cycles, FIG. 10 shows that the column command advance latency AL is 0, FIG. 11 shows a timing chart in a read operation when a command is input two cycles after the ACTV command input, FIG. 11 shows a timing chart in a write operation when AL is 0, and FIG. 12 shows that AL is 1, that is, a column command is input from the ACTV command input. FIG. 13 shows a timing chart in a read operation when input after one cycle, and FIG. 13 shows a timing chart in a write operation when AL is 1.

  First, a read operation when AL is 0 will be described with reference to FIG. At the same time when the ACTV command is input, the row address is taken in from the address buffer 101 and latched in the address register 103 by ACLK output from the command decoder 102 in response to the ACTV command. Further, the row address is latched in the row address latch 104 by the clock RCLK output from the command decoder 102 in response to the ACTV command. Thereafter, the row address signal is input to the row address comparison circuit 105 and compared with the relief address stored in the row relief address storage circuit 106, and a match or mismatch is determined. If they match, the row predecoder 107 is deactivated and a redundant word line is selected by the redundant row decoder 108. If they do not match, the row predecoder 107 is activated, the output of the row address latch 104 is predecoded by the row predecoder 107, the output is decoded by the row decoder 109, and the word line is selected. Thereafter, data is output from the memory cell connected to the selected word line to the bit line, and when the potential of the bit line is sufficiently opened, the potential difference of the bit line where the sense amplifier is activated is amplified.

  In FIG. 10, since AL = 0, the READ command is input two cycles after the ACTV command is input. At the same time, the column address is taken in from the address buffer 101 and latched in the address register 103 by the clock ACLK output from the command decoder 102 in response to the READ command. Further, the column address is latched in the column address latch 110 by the clock YCLK 1 output from the command decoder 102 in response to the READ command. Here, the write register enable signal WRE generated by the command decoder 102 in response to the READ command is fixed to low, so that the column address is output from the column address latch 110 without being delayed by one cycle.

  Thereafter, the column address passes through the column address counter 111, is input to the column address comparison circuit 112, and is compared with the relief address stored in the column relief address storage circuit 113, and a match or mismatch is determined. The output from the comparison circuit 112 is input to the second timing adjustment circuit 125, but passes through the second timing adjustment circuit 125 because AL = 0 is fixed to low when AL = 0. Also in the first timing adjustment circuit 124, since ALE is fixed to low, the output from the column address counter 111 is passed through and input to the column predecoder 114. If the comparison results in the comparison circuit 112 match, the column predecoder 114 is deactivated by the output of the second timing adjustment circuit 125, and the redundant bit line is selected by the redundant column decoder 115. In the case of mismatch, the column predecoder 114 is activated by the output of the second timing adjustment circuit 125, the output of the first timing adjustment circuit 124 is predecoded by the column predecoder 114, and the output is output by the column decoder 116. The bit line is selected by decoding.

  At this time, the bit line selection condition is that the bit line is sufficiently amplified. When the bit line is selected, the data of the bit line is input to the reading circuit 117. Thereafter, the read data is further amplified by the read circuit 117 and sent to the output register 118. In the output register 118, data is sent to the output buffer 120 in accordance with the CAS latency information signal CL from the command decoder 102 and the clock QCLK1 output from the output clock generation circuit 119, and is output to the outside. At this time, in the double data rate synchronous DRAM of this embodiment, 2n-bit data is sent to the output buffer 120, and half n-bit data remains at the rising edge of the clock QCLK1, and also remains at the falling edge of QCLK1. N bits of data are output.

  In the read operation, the read circuit enable signal MAE and the output clock generation circuit enable signal ORE are output from the command decoder 102 in response to the READ command, and the delay register 201 in the delay control circuit 126 shown in FIG. The signals pass through the delay register 202 and are supplied to the reading circuit 117 and the output clock generation circuit 119 as MAE1 and ORE1, respectively. Here, since AL = 0, ALE is fixed low, so that MAE and ORE pass through the delay register 201 and the delay register 202 and are not delayed from the delay control circuit 126 to MAE1 and ORE1. Is output as

  As shown in FIG. 11, in the write operation when AL is 0, the row address is taken in at the same time as the ACTV command is input, and the row address is decoded and the word line is selected in the same manner as in the read operation. The data of the memory cell is output to the bit line. When the bit line potential is sufficiently opened, the sense amplifier is activated to amplify the bit line potential.

  Here, since AL = 0, the WRITE command is input after two cycles after the ACTV command is input, and the column address is taken in at the same time as this command is input. In addition, since the write enable signal WRE generated by the command decoder 102 in response to the WRITE command is enabled (high level), the column address is input by the column address latch 110 by the clock YCLK1 generated by the command decoder 102. Output after being delayed by one cycle. Thereafter, the column address is decoded and the bit line is selected in the same manner as in reading. At this time, since AL = 0, the input signals to the first timing adjustment circuit 124 and the second timing adjustment circuit 125 are passed through. Write data is fetched from the outside in one cycle (= AL + CAS latency-1) after the WRITE command is input.

  In the double data rate synchronous DRAM of this embodiment, write data is taken in by the input buffer 121, and the first n-bit data is received at the rising edge of the clock DCLK output from the command decoder 102 in response to the WRITE command. However, the next n-bit data is latched in the input register 122 at the falling edge of the clock DCLK, and becomes 2n-bit data. The fetched write data is sent to the memory cell array 123 through the write circuit 117, and further written into the memory cell through the selected bit line.

  In the write operation, the write circuit enable signal WBE is output from the command decoder 102 in response to the WRITE command, passes through the delay register 203 in the delay control circuit 126 shown in FIG. 2, and is sent to the write circuit 117 as WBE1. Entered. At this time, since AL = 0 and ALE is fixed low, WBE passes through the delay register 203 and is output from the delay control circuit 126 as WBE1.

  Next, the read operation when AL = 1, that is, when the ACTV command is input and the READ command is input after one cycle will be described. As shown in FIG. 12, the row address is taken in at the same time as the ACTV command is input, the row address is decoded and the word line is selected in the same way as when AL = 0, and the data of the memory cell is transferred to the bit line. Is output. When the bit line is sufficiently opened, the sense amplifier is activated, and the potential difference between the bit lines is amplified.

  When the READ command is input one cycle after the ACTV command is input, the column address is taken in by the address buffer 101 at the same time, and the address is received by the clock ACLK output from the command decoder 102 in response to the READ command. It is latched in the register 103. Further, the column address is latched in the column address latch 110 at the clock YCLK 1 output from the command decoder 102 in response to the READ command. At the time of reading, since the write register enable signal WRE generated by the command decoder 102 upon receiving the READ command is fixed to low, the column address is output from the column address latch 110 without being delayed by one cycle.

  Thereafter, the column address passes through the column address counter 111, is input to the column address comparison circuit 112, and is compared with the repair address stored in the column repair address storage circuit 113, and a match or mismatch is determined. Here, when AL = 1, ALE is fixed at a high level, so the output from the comparison circuit 112 is latched by the second timing adjustment circuit 125, and the output from the column address counter 111 is the first timing adjustment circuit. Latched at 124.

  Then, the clock YCLK3 and YCLK4 are generated from the command decoder 102 upon receiving a clock one cycle after the READ command is input, and are input to the first timing adjustment circuit 124 and the second timing adjustment circuit 125, respectively. In response to the rising edges of YCLK3 and YLCK4, the output of the column address counter 111 latched in the first timing adjustment circuit 124 and the output of the comparison circuit 112 latched in the second timing adjustment circuit 125 are Each is output. As a result, the output of the column address counter 111 and the output of the comparison circuit 112 are delayed by one cycle.

  Thereafter, if the comparison results in the comparison circuit 112 match, the column predecoder 114 is deactivated by the output of the second timing adjustment circuit 125, and the redundant bit line is selected by the redundant column decoder 115. On the other hand, in the case of mismatch, the column predecoder 114 is activated by the output of the timing adjustment circuit 125, the output of the first timing adjustment circuit 124 is predecoded by the column predecoder 114, and the output is output by the column decoder 116. The bit line is selected by decoding. At this time, since the column address path already includes a delay of one cycle, the bit line potential is sufficiently amplified, and correct data can be read out. Thereafter, by selecting a bit line, the data of the bit line is input to the read circuit 117, and the data is further amplified by the read circuit 117 and sent to the output register 118.

  In the output register 118, data is sent to the output buffer 120 in accordance with the CAS latency information signal CL from the command decoder 102 and the clock QCLK1 generated from the output clock generation circuit 119, and is output to the outside. At this time, as described with reference to FIG. 11, in the double data rate synchronous DRAM, data is output at the timing of both the rising edge and falling edge of the clock.

  At the time of reading, the read circuit enable signal MAE and the output clock generation circuit enable signal ORE are output from the command decoder 102 in response to the READ command, and the delay registers 201 and 202 in the delay control circuit 126 shown in FIG. As described above, MAE1 and ORE1 are input to the readout circuit 117 and the output clock generation circuit 119, respectively. However, since AL = 1 is fixed at a high level, MAE and ORE are one cycle in the delay registers 201 and 202. Delayed by one minute and output as MAE1 and ORE1.

  As shown in FIG. 13, in the write operation when AL is 1, the ACTV command is first input, and at the same time, the row address is taken in, and the row address is decoded and read in the same way as in reading. The line is selected, and the memory cell data is output to the bit line. When the potential difference between the bit lines is opened to some extent, the sense amplifier is activated and the potential difference between the bit lines is amplified.

  When the WRITE command is input after one cycle from the input of the ACTV command, the column address is taken in simultaneously with the input of the command. Next, in response to the WRITE command, the write register enable signal WRE generated by the command decoder 102 is enabled, and the column address is delayed by one cycle in the column address latch 110 by the clock BCLK generated by the command decoder 102 and output. Is done. Thereafter, the column address is decoded and the bit line is selected in the same manner as in reading. At this time, since ALE is fixed at a high level by AL = 1, the signals input to the first timing adjustment circuit 124 and the second timing adjustment circuit 125 are the first timing adjustment circuit 124 and the second timing adjustment circuit, respectively. The output is delayed by 125 for one cycle.

  Therefore, the delay time from when the WRITE command is input to when the bit line is selected is delayed by one cycle compared to when AL = 0. As a result, the write data can be fetched from outside in two cycles (= AL + CAS latency−1) after the WRITE command is input. At this time, in the double data rate synchronous DRAM, data is taken in at both the rising edge and falling edge of the clock. This write data is taken in by the input buffer 121 and is latched in the input register 122 by the clock DCLK output from the command decoder 102 in response to a clock one cycle after the WRITE command is input.

  Thus, as described above, even when the WRITE command is input in the cycle after the ACTV command is input with AL = 1, the delay time until the clock DCLK is generated is one cycle with respect to AL = 0. Since it is delayed by a minute, the write data can be taken in without any problem. Thereafter, the write data is sent to the memory cell array 123 through the write circuit 117, and further written to the memory cell through the selected bit line. The write circuit enable signal WBE is output from the command decoder 102 in response to the WRITE command, passes through the delay register 203 in the delay control circuit 126 shown in FIG. 2, and is input to the write circuit 117 as WBE1. Since AL = 1 and ALE is fixed at the high level, WBE is delayed by one cycle in the delay register 203 and output as WBE1. Therefore, even if the WRITE command is input one cycle earlier, data can be written to the memory cell without any problem.

  FIG. 14A shows the timings of the row and column signals in the read operation when the column command advance latency AL is 0. In FIG. 14, the time required from when the ACTV command is input until the potential of the bit line is sufficiently amplified is t0, and the time required from when the READ command is input until the column address is taken into the column address latch 110 by YCLK1. T1, the required time from the latch of the column address to the input to the column predecoder 114, t2, the required time from the latch of the column address to the output of the comparison result t2 ′, The required time from the output of the comparison circuit 112 until the address is decoded by the decoders 115 and 116 and the bit line is selected is t3, and the required time from the selection of the bit line to the output of the signal amplified by the readout circuit 117 T4, the position from the output of the readout circuit 117 to the input to the output register 118 The time required is t5, and the time required from the input to the output register 118 to the data output by the output buffer 120 is t6. As can be seen from the figure, when three cycles are required until the bit line potential is sufficiently amplified after the ACTV command is input, the bit line amplification is performed when the READ command is input two cycles after the ACTV command is input. The completion time (t0) and the bit line selection time (2tck + t1 + t2 ′ + t3) are the same.

  On the other hand, FIG. 14B shows the timing in the read operation when AL is 1. In this case, the READ command is input one cycle after the ACTV command is input, the generation of YCLK3 and YCLK4 is started after one cycle, YCLK3 and YCLK4 are output after t21 time, and the timing adjustment circuits 124 and 125 after time t22. Thus, the column address data and the output of the comparison circuit 112 are latched, and the bit line is selected after time t3. At this time, the required time (t21 + t22) until the generation of YCLK3 and YCLK4 and the latching of the timing adjustment circuits 124 and 125 is completed is the column address latch and comparison circuit after the READ command when AL = 0 is input. 112 is the same as the required time (t1 + t2 ′) from when the comparison result is output, that is, (t21 + t22) = (t1 + t2 ′), so that the required time from when the ACTV command is input until the bit line is selected. Since the time can be almost the same when AL = 0 and AL = 1, the data of the selected memory cell can be read correctly.

  FIG. 15A shows the timing of the row system and the column system in the read operation when AL = 0 when the time until the completion of the bit line amplification is relatively short. At the timing of FIG. 15A, the required time t0 ′ from when the ACTV command is input until the bit line is sufficiently amplified is the required time from when the ACTV command is input until the bit line is selected (2tck + t1 + t2). Shorter than '+ t3). In such a case, the cycle time is determined so that the required time (t1 + t2 + t3 + t4 + t5 + t6) until data is output after the READ command is input ends within two cycles (2tck). That is, the cycle time (tck) is limited by the column system pass. The optimum timing is when the bit line amplification completion point (the rear end of t0 ′) coincides with the column decode end point (the rear end of t3). In FIG. 15A, the completion of the bit line amplification is completed. It can be seen that the time indicated by the broken line t0 is wasted because it ends first. The phenomenon that the time until the completion of the bit line amplification is relatively short is caused between products due to process variations.

  In the product in which the time until the completion of the bit line amplification is relatively short as described above, a register that can delay the column address is inserted in the preceding stage of the column predecoder 114 as in the above embodiment, and the READ command As shown in FIG. 15 (B), the column address latch (t1 period) and the comparison of the comparison circuit 112 (t2 ′) are performed in the second cycle. From generation of YCLK 3 and 4 to decoding of the column address can be performed in the third cycle. In FIG. 15B, t21 ′ is the time required until YCLK3 and 4 are generated from the clock, t22 ′ is the time required until the output of the address delayed by the timing adjustment circuits 124 and 125 is determined, Although it is a necessary condition that (t21 ′ + t22 ′) is shorter than (t1 + t2 ′), this can be easily realized as a circuit.

  As a result, when AL = 1, since the bit line can be selected in accordance with the time when the bit line is amplified, the time difference until the completion of the bit line amplification is divided by “4” of all the required cycles (t0−t0). ') / 4 can shorten the cycle time. According to the timing control as shown in FIG. 14B, the time required from the generation of YCLK 3 and 4 to the output of data (t21 ′ + t22 ′ + t3 + t4 + t5 + t6) may be completed in two cycles. Is shorter, in principle, the cycle time Tck is determined by the later time of (t1 + t2 ′) or (t21 ′ + t22 ′ + t3 + t4 + t5 + t6) / 2, and compared to when AL = 0, {(t1 + t2 ′ + T3 + t4 + t5 + t6) / 2− (t1 + t2)} or {(t1 + t2 ′ + t3 + t4 + t5 + t6) / 2− (t21 ′ + t22 ′ + t3 + t4 + t5 + t6) / 2}.

  Next, how to set the column command advance latency AL in the double data rate synchronous DRAM shown in FIG. 1 and the operation when AL is set will be described.

  In the embodiment of FIG. 1, the CAS latency CL is set in the CL setting register 131 by the mode register set (MRS) command, and the column command advance latency AL is set in the AL in the command decoder by the extended mode register set (EMRS) command. Set in the register 132.

  FIG. 16 shows specific examples of the MRS command and the EMRS command. In this embodiment, a control signal CKE supplied from an external device such as a CPU is at a high level, / CS, / RAS, / CAS, / WE are at a low level, bank addresses BA1, BA0 (or addresses A14, A13) and an address. When the predetermined bit AP (for example, A10) is at a low level, an MRS command is issued, and various values are set according to the values of the addresses A8 to A0. Also, when CKE · BA0 (A14) is at high level, / CS, / RAS, / WE, BA1 (A13), and AP (A10) are at low level, an EMRS command is issued, and various values are set according to the address value. Value is set.

  When CKE, / RAS, / WE are at high level and / CS, / CAS, AP (A10) are at low level, a READ command for instructing reading is issued, CKE, / RAS are at high level, / CS, / CAS, When / WE, AP (A10) is at a low level, a WRITE command for instructing writing is started. ACTV commands for instructing activation of (memory array) are issued respectively.

  FIG. 17A shows an example of the relationship between the address and the set value in setting the CAS latency by the MRS command. As shown in the figure, in the DRAM of this embodiment, the burst length (BL) is set at addresses A0 to A2, the burst type (interleaved or sequential) is set at A3, and the CAS latency is set at A4 to A6. Then, the reset of the output clock generation circuit 119 is set at A8. With regard to CAS latency, for example, when (A4, A5, A6) = (0, 1, 0), the latency is “2”, and when (A4, A5, A6) = (1, 1, 0), the latency is Set to “3”.

  FIG. 17B shows an example of the relationship between the address and the set value in the column command advance latency setting by the EMRS command. As shown in the figure, in the DRAM of this embodiment, the activation / inactivation of the output clock generation circuit 119 is set at A0, and the column command advance latency AL is set at A1 to A3. As for the column command advance latency AL, for example, when (A1, A2, A3) = (0, 0, 0), the latency is “0”, and (A1, A2, A3) = (1, 0, 0). The latency is set to “2” when the latency is “1” and (A1, A2, A3) = (0, 1, 0).

  FIG. 18 shows a second embodiment of a double data rate synchronous DRAM to which the present invention is applied. In the second embodiment, the timing adjustment circuits 124 and 125 provided in the preceding stage of the column predecoder 114 in the first embodiment (FIG. 1) are arranged between the column address latch 110 and the column address counter 111. 224 is provided. Since other configurations are the same as those of the first embodiment, the same circuit blocks are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 19 shows a timing chart in a read operation when AL latency is 1 on the assumption that tRCD is 2 cycles and CAS latency is 2 cycles. FIG. 19 corresponds to FIG. 12 showing a timing chart in the first embodiment.

  As apparent from comparison with FIG. 12, in the DRAM of the second embodiment, the timing adjustment circuit 224 is in the preceding stage of the column address counter 111, so that the output of the column address counter 111 is higher than that in the case of the first embodiment. Although slow, the input timing to the column decoder 116 or the redundant column decoder 115 is substantially the same as that of the first embodiment. As a result, the same effect as the first embodiment can be obtained.

  The read operation and the write operation when AL = 0 in the DRAM of the second embodiment can be easily estimated from the read operation (FIG. 10) and the write operation (FIG. 11) in the first embodiment. Also, the write operation when AL = 1 can be easily estimated from the read operation (FIG. 19) and the write operation in the first embodiment (FIG. 13), and thus the description thereof is omitted here.

  The second embodiment has an advantage that the total number of bits of the timing adjustment circuit is less than half compared to the first embodiment. That is, the number of bits of the timing adjustment circuit 224 in the second embodiment is the same as that of the first timing adjustment circuit 124 in the first embodiment, for example, 9 × 4 = 36 bits. The second timing adjustment circuit 125 having the same number of bits as the number (for example, 32 × 4 = 128) is unnecessary. However, since the position of the timing adjustment circuit 224 is on the previous stage as compared with the first embodiment, the effect of shortening the cycle time is slightly reduced.

  That is, in FIG. 14B showing the timing of the first embodiment, the required time t1 from when the READ command in the second cycle is input until the column address is taken into the column address latch 110 by YCLK1 is In the second embodiment, it can be executed in the second cycle. In the first embodiment, the time t2 required until the column address in the second cycle is input to the column predecoder 114 is the same as that in the second embodiment. Since the third cycle is entered, the effect of shortening the cycle time is smaller than in the first embodiment.

  FIG. 20 shows a third embodiment of a double data rate synchronous DRAM to which the present invention is applied. In the third embodiment, the timing adjustment circuits 124 and 125 provided in the preceding stage of the column predecoder 114 in the first embodiment (FIG. 1) are arranged between the column address counter 111 and the column predecoder 114. 324 is provided. Since other configurations are the same as those of the first embodiment, the same circuit blocks are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 21 shows a timing chart in the read operation when the AL latency is 1 on the assumption that tRCD is 2 cycles and the CAS latency is 2 cycles. FIG. 21 corresponds to FIG. 12 showing a timing chart in the first embodiment.

  As is clear from comparison with FIG. 12, in the DRAM of the third embodiment, the timing adjustment circuit 324 is in the preceding stage of the column address comparison circuit 112, so that the output of the column address comparison circuit 112 is the case of the first embodiment. Although slower than that, the input timing to the column decoder 116 or the redundant column decoder 115 is substantially the same as that of the first embodiment. As a result, the same effect as the first embodiment can be obtained.

  The read operation and the write operation when AL = 0 in the DRAM of the third embodiment can be easily estimated from the read operation (FIG. 10) and the write operation (FIG. 11) in the first embodiment. Also, the write operation when AL = 1 can be easily estimated from the read operation (FIG. 21) and the write operation in the first embodiment (FIG. 13).

  In the present embodiment, compared with the first embodiment shown in FIG. 1, efficient time distribution cannot be performed when AL = 1. Further, even when the time from the ACTV command to the amplification of the bit line is shortened and the column path is rate-determined when AL = 0, the effect of shortening the cycle time is small. However, the number of timing adjustment circuits can be reduced by the number of comparison circuit outputs, which can contribute to chip size reduction. Compared to the second embodiment, more efficient time distribution can be achieved when AL = 1, and the time from the ACTV command until the bit line is amplified is shortened. The column path is rate-controlled when AL = 0. Cycle time can be shortened. The number of bits of the timing adjustment circuit 324 is the same as in the second embodiment.

  FIG. 22 shows a fourth embodiment of a double data rate synchronous DRAM to which the present invention is applied. In the fourth embodiment, the timing adjustment circuits 124 and 125 provided in the preceding stage of the column predecoder 114 in the first embodiment (FIG. 1) are provided as 424 and 425 in the subsequent stage of the column predecoder 114, respectively. Is. Since other configurations are the same as those of the first embodiment, the same circuit blocks are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 23 shows a timing chart in a read operation when AL latency is 1 on the assumption that tRCD is 2 cycles and CAS latency is 2 cycles. FIG. 23 corresponds to FIG. 12 showing a timing chart in the first embodiment.

  As is clear from comparison with FIG. 12, in the DRAM of the fourth embodiment, the timing adjustment circuits 424 and 425 are in the subsequent stage of the column predecoder 114, but the timing of the signal shown in FIG. This is exactly the same as the timing chart of FIG. As a result, the same effect as the first embodiment can be obtained.

  The read operation and the write operation when AL = 0 in the DRAM of the fourth embodiment can be easily estimated from the read operation (FIG. 10) and the write operation (FIG. 11) in the first embodiment. Also, the write operation when AL = 1 can be easily estimated from the read operation (FIG. 23) and the write operation in the first embodiment (FIG. 13), and thus the description thereof is omitted here.

  In the present embodiment, as in the first embodiment shown in FIG. 1, efficient time distribution can be performed when AL = 1. Further, when the time from the ACTV command to the amplification of the bit line is shortened and the column path is rate-determined when AL = 0, the cycle time can be shortened by the effect of pipelining when AL = 1 or more. However, the timing adjustment circuits 424 and 425 have more bits than in the first embodiment because the timing adjustment circuits have the same number of pre-decoded column addresses and the number of comparison circuit outputs.

  FIG. 24 shows a fifth embodiment of a double data rate synchronous DRAM to which the present invention is applied. In the fifth embodiment, in addition to the timing adjustment circuits 124 and 125 provided in the preceding stage of the column predecoder 114 in the first embodiment (FIG. 1), the column address counter 111 and A timing adjustment circuit 524 is also provided between the column address comparison circuit 112 and the column address comparison circuit 112. Since other configurations are the same as those of the first embodiment, the same circuit blocks are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 25 shows a timing chart in a read operation when AL latency is 2 on the assumption that tRCD is 3 cycles and CAS latency is 2 cycles.

  As shown in FIG. 25, in the read operation when AL = 2, the row address is taken in at the same time as the ACTV command is input, the row address is decoded, the word line is selected, and the memory The cell data is output to the bit line. When the bit line is sufficiently opened, the sense amplifier is activated and the bit line potential is amplified.

  When tRCD is 3 cycles and AL = 2, the READ command is input 1 cycle after the ACTV command is input. At the same time, the column address is taken in from the address buffer 101 and latched in the address register 103 by ACLK output from the command decoder 102 in response to the READ command. Further, the column address is latched in the column address latch 110 at YCLK1 output from the command decoder 102 in response to the READ command. Since the write register enable signal WRE generated by the command decoder 102 in response to the READ command is fixed to low, the column address is output from the column address latch 110 without being delayed by one cycle.

  Thereafter, the column address passes through the column address counter 111 and is input to the timing adjustment circuit 524 and latched. Upon receiving a clock one cycle after the READ command is input, YCLK5 is generated from the command decoder 102 and input to the timing adjustment circuit 524. In response to the rising edge of YCLK5, the column address latched in the timing adjustment circuit 524 is output. As a result, the column address is delayed by one cycle. Thereafter, it is input to the column address comparison circuit 112 and compared with the relief address stored in the column relief address storage circuit 113, and a match or mismatch is determined. When AL = 2, since ALE1 is fixed high, the output from the comparison circuit 112 is latched by the timing adjustment circuit 125, and the output from the timing adjustment circuit 524 (the output of the column address counter 111) is output from the timing adjustment circuit 124. Latched.

  Then, upon receiving a clock two cycles after the READ command is input, YCLK3 and YCLK4 are generated from the command decoder 102 and input to the timing adjustment circuits 124 and 125, respectively. In response to the rising edges of YCLK3 and YLCK4, the output of the column address counter 111 latched in the timing adjustment circuit 124 and the output of the comparison circuit 112 latched in the timing adjustment circuit 125 are output. As a result, the output of the column address counter 111 and the output of the comparison circuit 112 are delayed by one cycle.

  Thereafter, if the comparison results in the comparison circuit 112 match, the column predecoder 114 is deactivated by the output of the timing adjustment circuit 125, and the redundant bit line is selected by the redundant column decoder 115. If they do not match, the column predecoder 114 is activated by the output of the timing adjustment circuit 124, the output of the timing adjustment circuit 124 is predecoded by the column predecoder 114, and the output is decoded by the column decoder 116 to be a bit. A line is selected. At this time, since the column address path already includes a delay of two cycles, the bit line is sufficiently amplified and correct data can be read out. After that, when the bit line is selected, the bit line data is input to the read circuit 117, and the read circuit 117 amplifies the data again and sends it to the output register 118.

  In the output register 118, data is sent to the output buffer 120 in accordance with the CAS latency information signal CL from the command decoder 102 and QCLK1 generated from the output clock generation circuit 119, and is output to the outside. At this time, in the double data rate synchronous DRAM, data is output from both the rising edge and falling edge of the clock. The read circuit enable signal MAE and the output clock generation circuit enable signal ORE are output from the command decoder 102 in response to the READ command, and the first delay register 3201 and the second delay register in the delay control circuit 126 shown in FIG. 3202 and the third delay register 3211 and the fourth delay register 3212 are input to the read circuit 117 and the output clock generation circuit 119 as MAE1 and ORE1, respectively. When AL = 2 (because ALE1 and ALE2 are fixed high), MAE and ORE are in the first delay register 3201 and the second delay register 3202, and in the third delay register 3211 and the fourth delay register 3212, respectively. Are delayed by two cycles and output as MAE1 and ORE1.

  In this embodiment, as in the first embodiment shown in FIG. 1, efficient time distribution can be realized when AL = 2. Further, when the time from the ACTV command to the amplification of the bit line is shortened and the column path is rate-determined when AL = 0, the cycle time can be shortened by the effect of pipelining when AL = 1 or more. However, the circuit scale is slightly larger than that of the first embodiment.

  FIG. 27 shows a sixth embodiment of a double data rate synchronous DRAM to which the present invention is applied. In this embodiment, the timing adjustment circuit 524 provided immediately after the column address counter 111 is provided between the column address latch 110 and the column address counter 111 in the fifth embodiment (FIG. 24). is there. Further, in the double data rate synchronous DRAM of the sixth embodiment, not only read / write data but also command input has a double data rate.

  FIG. 28 shows a timing chart in the read operation when the AL latency is 1.5 on the assumption that tRCD is 2 cycles and the CAS latency is 2 cycles.

  As shown in FIG. 28, in the read operation when AL = 1.5, the row address is taken in at the same time when the ACTV command is input, the row address is decoded, and the word line is selected. The data of the memory cell is output to the bit line. When the bit line is sufficiently opened, the sense amplifier is activated and the bit line potential is amplified.

  When AL = 1.5, the READ command is input 0.5 cycle after the ACTV command is input. At the same time, the column address is taken in from the address buffer 101 and latched in the address register 103 by ACLK output from the command decoder 102 in response to the READ command. Further, the column address is latched in the column address latch 110 at YCLK1 output from the command decoder 102 in response to the READ command. At this time, since the write register enable signal WRE generated by the command decoder 102 in response to the READ command is fixed to low, the column address is output from the column address latch 110 without being delayed by one cycle, and is sent to the timing adjustment circuit 524. Latched.

  Then, upon receiving a clock one cycle after the READ command is input, YCLK 5 is generated from the command decoder 102 and input to the timing adjustment circuit 524. In response to the rising edge of YCLK5, the column address latched in the timing adjustment circuit 524 is output. As a result, the column address is delayed by 0.5 cycles. Thereafter, the column address is input to the column address comparison circuit 112 and compared with the repair address stored in the column repair address storage circuit 113, and a match or mismatch is determined. Since AL = 1.5, ALE1 is fixed high, so that the output from the comparison circuit 112 is latched by the timing adjustment circuit 125, and the output from the column address counter 111 is latched by the timing adjustment circuit 124.

  In response to a clock two cycles after the READ command is input, YCLK3 and YCLK4 are generated from the command decoder 102 and input to the timing adjustment circuits 124 and 125, respectively. In response to the rising edges of YCLK3 and YLCK4, the output of the column address counter 11 latched in the timing adjustment circuit 124 and the output of the comparison circuit 112 latched in the timing adjustment circuit 125 are output. As a result, the output of the column address counter 111 and the output of the comparison circuit 112 are delayed by one cycle.

  Thereafter, if the comparison results in the comparison circuit 112 match, the column predecoder 114 is deactivated by the output of the timing adjustment circuit 125, and the redundant bit line is selected by the redundant column decoder 115. If they do not match, the column predecoder 114 is activated by the output of the timing adjustment circuit 124, the output of the timing adjustment circuit 124 is predecoded by the column predecoder 114, and the output is decoded by the column decoder 116 to be a bit. A line is selected. At this time, since a delay of 1.5 cycles is already included in the signal path of the column address system, the bit line is sufficiently amplified and correct data can be read out. After that, when the bit line is selected, the data of the bit line is input to the read circuit 117, the data is further amplified by the read circuit 117, sent to the output register 118, and output to the outside of the chip by the output buffer 120. Is done.

  In the present embodiment, in addition to the effect of the fifth embodiment, there is an advantage that not only the read / write data but also the command input can cope with the double data rate.

  As described above, in the double data rate synchronous DRAM of the above embodiment, even if the column command input timing is advanced, the bit line is selected before the read data is amplified by the sense amplifier. Therefore, correct data can be read out. Furthermore, after the correct write data is input to the write circuit, the bit line is selected, and the correct data can be written.

  Even if the column command advance latency is changed, correct data can be read because the bit line is not selected before the read data is amplified by the sense amplifier. Furthermore, since the bit line is not selected before the correct write data is input to the write circuit, the correct data can be written.

  Furthermore, when the time from the activation of the active command to the amplification of the bit line is shortened, and the column command is advanced in latency by AL = 0 and the column system path determines the cycle time, the cycle becomes effective at AL = 1 due to the effect of pipelining. Data transfer speed can be increased by shortening the time.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the first embodiment (FIG. 1), the second embodiment (FIG. 18), the fourth embodiment (FIG. 22), the fifth embodiment (FIG. 24), and the sixth embodiment (FIG. 27). ), The column address counter 111 may be omitted. In each of the above embodiments, the cycle tRCD from the active command to the input of the column command is 2 cycles, and the column command advance latency is set to “0”, “1”, or “1.5”. However, for example, when tRCD is 3 cycles or more, the column command advance latency can be set to “2” or more. As such a case, for example, a memory configured to divide an address into three or more times and take it into the chip in a time division manner may be considered.

  In the above description, the case where the invention made by the present inventor is applied to the double data rate synchronous DRAM, which is the field of use behind the invention, has been described. However, the present invention is not limited thereto, and the semiconductor is not limited thereto. It can be used for a memory, particularly a clock synchronous semiconductor memory in general.

101: Address buffer,
102: Command decoder,
103: Address register,
104 ... row address latch,
105 ... row address comparison circuit,
106: row relief address storage circuit;
107 ... row predecoder,
108: Redundant row decoder,
109 ... row decoder,
110 ... column address register,
111 ... column address counter,
112 ... Column address comparison circuit,
113 ... Column relief address storage circuit,
114 ... column predecoder,
115 ... Redundant column decoder,
116 ... column decoder,
117 ... Read / write circuit,
118: Output register,
119: Output clock generation circuit,
120 ... output buffer,
121 ... Input buffer,
122... Input register,
123: Memory cell array,
124... First timing adjustment circuit,
125 ... second timing adjustment circuit,
126 ... delay control circuit,
224, 324, 424, 524 ... third timing adjustment circuit,
425: Fourth timing adjustment circuit.

Claims (6)

A semiconductor memory device capable of reading or writing data specified by a row address and a column address by inputting a column command after inputting an operation start command,
A memory cell array including a plurality of memory cells;
A register setting value that specifies the timing to before Symbol column command is turned on ahead is set,
A timing adjustment circuit having an input terminal to which the column address is input and an output terminal for delaying and outputting the column address by a delay time corresponding to the timing specified by the setting value of the register;
The timing adjustment circuit adjusts a delay amount and a latch circuit that delays the column address in synchronization with an internal clock that is connected in series between the input end and the output end and is generated based on at least the set value. It includes timing adjusting delay circuit for,
The timing adjustment circuit has a first path that passes through the latch circuit and the timing adjustment delay circuit, and a second path that does not pass through the latch circuit and the timing adjustment delay circuit,
The semiconductor memory device , wherein the timing adjustment circuit further includes a path selection circuit that selects the first path or the second path based on the set value .   2. The semiconductor memory device according to claim 1, wherein the delay circuit for timing adjustment is a circuit in which a plurality of delay elements are connected in series. 3. The semiconductor memory device according to claim 1, wherein the path selection circuit is provided in a front stage and a rear stage of a series circuit including the latch circuit and the timing adjustment delay circuit. 3. The semiconductor memory device according to claim 1, wherein the path selection circuit is provided before and after the latch circuit, and before and after the timing adjustment delay circuit. The internal clock, a semiconductor memory device according to at least any one of said column commands and claims 1 to 4, characterized in that it is produced on the basis of the set value. Said row address is input in synchronization with the operation start command, the column address is a semiconductor memory device according to any one of claims 1 to 5, characterized in that the input in synchronization with the column command .

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