JP5587530B2 - Engine / processor linkage system and linkage method - Google Patents

Description

  The present invention relates to an engine / processor cooperation technique, and more particularly, to an engine / processor cooperation system that outputs, as transmission data, a result of arithmetic processing performed on input commands and packets by hardware or software.

  If the configuration of an arithmetic system that performs some operation on the input of data from the outside and outputs the result to the outside is roughly classified, as shown in FIG. 12, a receiving unit that receives data from the outside, A transmission unit that transmits data to the transmission unit, and a calculation unit that performs arithmetic processing on the data received from the reception unit and outputs the data to the transmission circuit.

  As an example of an arithmetic system, a software arithmetic system using a processor as shown in FIG. 13 and a hardware arithmetic system as shown in FIG. 14 are common.

  The software operation system shown in FIG. 13 includes a reception circuit, a transmission circuit, a processor, a memory, other peripheral devices, and a processor bus that connects each module. By connecting all modules via a processor bus, this is a flexible architecture that allows modules that match the processor bus standard to be freely added.

  However, since it is necessary to transmit and receive data via the processor bus for access between all modules, the arithmetic processing performance is generally low. In particular, the processor itself performs processing by sequentially accessing the memory device. For this reason, generally, a software operation system can flexibly realize various processes, but has a feature that it is difficult to realize high performance.

  The hardware calculation system shown in FIG. 14 includes a reception circuit, a transmission circuit, and a hardware calculation processing unit. The data received from the receiving circuit is directly input to the hardware arithmetic unit, and after the hardware arithmetic processing unit performs the arithmetic processing, the data is output to the transmitting circuit, and the transmission data is output to the outside from the transmitting circuit. The

  In general, hardware computing systems are fixedly connected to each other, and processing necessary for computations can be performed in parallel and pipeline processing, enabling high-performance processing compared to software computing systems. . Conversely, because the processing is fixed, it is difficult to build a system flexibly, and it is necessary to design dedicated logic according to the processing, so the circuit scale increases and the development period increases. It is difficult to realize complicated logic.

  As described above, the software arithmetic system and the hardware arithmetic system have advantages and disadvantages, respectively, but an arithmetic system that makes use of both advantages has been proposed by Altera (Non-patent Document 1).

  FIG. 15 shows an example of C2H of Altera as Conventional Example 1 (Non-Patent Document 1).

  The arithmetic system of Conventional Example 1 includes a receiving circuit, a transmitting circuit, a processor, a memory, a DMA engine (DMA), and a hardware engine (HW Engine).

  The data input to the receiving circuit is once expanded on the general-purpose memory (Memory1) of the processor. When the processor determines that the received data is data that can be processed by the hardware engine, the processor uses the DMA engine to transfer the data to be processed from the memory to the hardware engine. When the data to be processed is input, the hardware engine executes arithmetic processing on the corresponding data, and transfers the arithmetic result to the memory (Memory2) accessible from the processor via the DMA engine.

  By using the arithmetic system of Conventional Example 1, it is possible to realize simple processing that is a bottleneck of processing with a hardware engine while using a processor for complicated processing, and flexibility by the processor And hardware engine can achieve both high speed.

  However, it is necessary to determine whether or not to use the hardware engine and to send data to the hardware engine via the processor for processing input from the receiving circuit. Processor processing is always required. Therefore, the performance is reduced as compared with the case where only the hardware engine is used.

  On the other hand, Patent Document 1 has been proposed as a processor / engine cooperation system different from the conventional example 1, and this technology includes a hardware processing unit and a software processing unit, This is a technology for determining which of the software processing unit is used for processing.

In Patent Literature 1, it is determined whether to perform hardware processing or software processing based on the type of session that can be identified from a TCP header or the like. Since the hardware process or the software process is identified for each session, it is not necessary to share a table for managing session information between the hardware processing unit and the software processing unit. On the other hand, it is difficult to realize a flexible process in which hardware processing and software processing are changed in the session according to the session state.
Altera C2H (http://www.altera.co.jp/products/ip/processors/nios2/tools/c2h/ni2-c2h.html, http://www.altera.co.jp/ss/product/product/ /Nios2/benefits/performance/ni2-acceleration.html, http://www.altera.co.jp/literature//wp/www-aghrdwr.pdf) JP 2002-354064 A

  The problem to be solved by the present invention is to solve the above-mentioned problem, which has both a processor (processing by software) and a high-speed engine (processing by hardware). It is an object of the present invention to provide an engine / processor cooperation system capable of flexibly changing execution in a processor.

  Another object of the present invention is to provide an engine / processor linkage system that synchronizes the contents of the session memory that holds the session status information between the processor and the high-speed engine, while maintaining the performance during high-speed engine operation. And

The present invention for solving the above-mentioned problems is an engine / processor cooperation system, which includes a session data memory that manages session data indicating the transmission / reception status of data for each session of a TCP session, and to which input data belongs. A reading unit that reads session data of a TCP session from the session data memory, a storage unit that stores the input data and the read session data, and the input data and session data that are stored A development unit that develops the data into a format that can be accessed by the processing unit, and refers to the developed data, and processes the stored input data with software or a hardware processing unit based on a predetermined calculation rule. A process determining unit that determines whether to process; When the processing determining unit determines to process with the hardware processing unit, it is determined that the hardware processing unit having a high-speed engine for processing the expanded input data and the processing determining unit to process with the software processing unit If the software processing unit for processing the input data being the storage, the processing of the input data is completed, it possesses an updating unit that updates the session data TCP sessions the input data belongs, the expansion portion Monitors whether the next input data is stored in the storage unit while the high-speed engine is processing the expanded data, and if the next input data is stored, When the processing completion notification is received from the high speed engine, the read input data is expanded .

The present invention for solving the above-described problem is a method for linking an engine and a processor, and is a method for linking an engine and a processor, which manages session data indicating a data transmission / reception status for each session of a TCP session. A read step for reading session data of a TCP session to which the input data belongs, a storage step for storing the input data and the read session data in a storage unit, and the stored data An expansion step for expanding input data and session data into a format accessible by a hardware processing unit, and the storage in the hardware processing unit with reference to the expanded data and based on a predetermined calculation rule Processed input data by software A processing decision step for deciding whether to process or a hardware processing unit, and a high-speed engine for processing the developed input data with a high-speed engine when it is decided at the processing step to be processed by a hardware processing unit When it is determined that the software processing unit processes the engine processing step and the processing step, the software processing step for processing the stored input data by software, and the processing of the input data is completed. And updating the session data of the TCP session to which the session belongs.

  In the engine / processor cooperation system of the present invention, the interface via the processor bus that the receiving circuit and the transmitting circuit can access from the software processing unit, and the high-speed hardware interface that can be accessed using the data developed from the hardware processing unit In the processing selection unit in the hardware processing unit, it is determined whether the software processing unit or the high-speed engine is to be processed, and the processing management unit has only one of the hardware processing unit and the software processing unit. , To ensure that arithmetic processing is performed.

  As a result, when the processing is realized by the hardware engine, the entire processing is performed without going through the software processing unit. Therefore, the hardware engine does not cause performance degradation due to the intervention of the software processing. It is feasible to use the maximum performance of.

  Furthermore, in the engine / processor cooperation system according to the present invention, the data expansion processing unit in the reception circuit unit expands the leading data in the reception data storage memory, delivers it to the hardware interface, and stores the next data in the reception data storage memory. When the command has arrived, the data is read from the received data storage memory in advance, the data is expanded in the data expansion processing unit, and as soon as the processing completion notification is input, the data is transferred to the hardware interface. By passing, the processing of the high-speed engine is accelerated.

  Furthermore, in the engine / processor cooperation system of the present invention, the processor can access the session data memory via the processor bus, and the data read by the session data read processing unit is only the data required by the processing selection unit and the high-speed engine. The data required by the processor is accessed from the session data memory. By reducing the amount of data required for reading by the session data read processing unit, it is possible to reduce the time required for reading session data in the session data read processing unit and the time required for developing read data in the data development processing unit. is there.

  According to the present invention, when the processing is realized by the hardware engine, the entire processing is performed without going through the software processing unit. It is possible to use the maximum performance of the wear engine.

  Further, according to the present invention, after the data expansion processing unit expands the head data in the reception data storage memory and delivers it to the hardware interface, the next command arrives in the reception data storage memory. The high-speed engine is configured to read data from the received data storage memory in advance, perform data expansion in the data expansion processing unit, and deliver the data to the hardware interface as soon as a processing completion notification is input. It is possible to speed up the process.

  Furthermore, the session data read processing unit reduces the amount of data required for reading, thereby reducing the time required for reading session data in the session data read processing unit and the time required for developing read data in the data development processing unit. Is possible.

  FIG. 1 shows a configuration example of an engine / processor cooperation system 8 of the present invention.

  The engine / processor cooperation system 8 includes a reception circuit 1, a transmission circuit 2 (session transmission circuit 2-1, external transmission circuit 2-2), a hardware processing unit 3, a software processing unit 4, a session memory management unit 5, and a processor bus. 6 and a MUX circuit 7.

  The hardware processing unit 3 includes a process selection unit 31, a process management unit 32, and a high speed engine 30.

  The software processing unit 4 includes a processor 40, a memory 41, and a peripheral circuit 42, and is connected to the processor bus 6 to perform various software processes.

  The session memory management unit 5 includes a session data write processing unit 53, a session data read processing unit 52, a session data memory 50, and a session lock memory 51.

  The session memory management unit 5 stores and manages unique data (session data) of each session in the session data memory 50.

  The session data stored in the session data memory 50 for each session is read out via the session data read processing unit 52 and updated via the session data write processing unit 53. .

  In the session lock memory 51, the session data of the same session is read before updating the session data by locking the reading of the session data until the writing process is executed after the reading of the session data. To prevent that. The session data memory 50 is also connected to the processor bus 6 so that the processor 40 can access the contents of the session data memory 50.

  The processor bus 6 is connected to the reception circuit 1, each transmission circuit 2, the processor 40, the memory 41, the peripheral circuit 42, the process management unit 32, and the session data memory 50. Thus, the processor 40 can access each block and execute software processing.

  The MUX circuit 7 selects one command from the packet and command received from the outside, and transfers the selected command to the session data read processing unit 52. As a reading method, there are a method of fixedly determining the priority order, a method of determining by round robin, and a method of reading in accordance with a reading ratio, and any method may be used.

  When the session data read processing unit 52 receives a command from the MUX circuit 7, the session data read processing unit 52 identifies the state of the session lock memory 51 and reads the session data from the session data memory 50 if the session data of the corresponding session is not locked. Do. When the session data of the corresponding session is locked, reading of the session data is stopped until the locked state is released. Release of the lock state of the session data of the corresponding session is executed when the session data write processing unit 53 receives a command from the session transmission circuit 2-1.

  When the session data read processing unit 52 reads the session data, the session data read processing unit 52 transfers the command data (packet command data) to the receiving circuit 1.

  The receiving circuit 1 temporarily holds data input from the session data read processing unit 52. The receiving circuit 1 provides an interface capable of reading the received command data and session data from both the hardware processing unit 3 and the software processing unit 4.

  The process selection unit 31 refers to the command and the session data stored in the reception circuit 1 and determines which of the high-speed engine 30 that processes by hardware and the processor 40 that processes by software.

  When processing is performed by the high-speed engine 30, the high-speed engine 30 is notified, and the high-speed engine 30 reads out data from the reception circuit 1, executes the processing, and then outputs the execution result to each transmission circuit 2. On the other hand, when processing is performed by the processor 40, the processor 40 identifies the target of command processing by the processor 40 via the processing management unit 32, executes the command processing, and sends the execution result to each transmission circuit 2. Output.

  The session transmission circuit 2-1 is connected to the session data write processing unit 53, receives the result of executing the command processing from the processor 40 or the high speed engine 30, and sends session data update information to the session transmission circuit 2. Output to -1.

  The session data write processing unit 53 updates the session data memory 50 based on the session data update information from the session transmission circuit 2-1 and releases the lock of the session lock memory 51.

  Here, the receiving circuit 1 will be described in detail.

  FIG. 2 is a configuration example of the receiving circuit 1.

  The reception circuit 1 includes a reception data storage memory 10, a reception data management unit 11, a reception software interface 12, and a data expansion processing unit 13.

  Packet command data and session data (input data) input to the receiving circuit 1 are stored in the received data storage memory 10.

  The reception data management unit 11 manages the input data stored in the reception data storage memory 10.

  The receiving circuit 1 has two hardware interfaces and a software interface as means for reading input data stored in the received data storage memory 10.

  The data expansion processing unit 13 reads the input data input to the received data storage memory 10 as data to be read, and expands it into a format that can be accessed at one time from the hardware interface. When the input data is expanded, the reception data management unit 11 outputs a reception packet notification signal to the hardware interface. When the processing in hardware is completed and a processing completion notification is input from the hardware interface unit, it is recognized that the processing of the read target data is completed, and the read target data is discarded. The received data storage memory 10 is monitored until a processing completion notification is input from the hardware interface unit. If there is next read target data, the next read target data is read from the received data storage memory 10 and expanded. .

  The reception software interface 12 is an interface that allows the software processing unit 4 to access input data stored in the reception data storage memory 10 via the processor bus 6. In the reception software interface 12, means for notifying whether or not the read target data exists in the reception data storage memory 10, the length of the read target data when there is read data, a read access means for the read target data, software processing The unit 4 provides a means for notifying the reception circuit 1 to the reception data management unit 11 that the processing of the data to be read is completed.

  As described above, in the receiving circuit 1, whether or not the data to be read exists for both the hardware interface and the software interface, the data length when there is, the access means to the data to be read, and the receiving circuit. 1 is provided with means for notifying that the processing of the data to be read is completed.

  Next, the transmission circuit 2-1 will be described.

  FIG. 3 is a configuration example of the transmission circuit 2-1.

  The transmission circuit 2-1 includes a transmission data storage memory 20, a transmission data management unit 21, a transmission software interface 22, and a decompressed data writing unit 23.

  The transmission circuit 2-1 temporarily stores the input data transmitted from the hardware interface or software interface in the transmission data storage memory 20, and outputs the input data in accordance with a notification signal indicating whether the input data can be received from the outside. I do. There are two types of notification signals to determine whether or not input data can be received from the outside: a method for finely controlling data reading from the outside, and a method for notifying reception by a back pressure signal only when a command cannot be received externally. In the present invention, either method may be used.

  The transmission data management unit 21 performs data management of the transmission data storage memory 20 and access management of the transmission data storage memory 20. The transmission data management unit 21 notifies the hardware interface unit and the transmission software interface 22 of the amount of free buffer in the transmission data storage memory 20.

  The high-speed engine 30 notifies the transmission of transmission data via the hardware interface unit. The high-speed engine 30 develops input data to be transmitted in advance and prepares it as decompressed data. When preparation of decompressed data is completed, the data length of the send target data is compared with the notified free buffer amount, and if the free buffer amount becomes larger than the data length of the send target data, the data length of the send target data Notify packet transfer.

  When the packet transfer notification is input, the decompressed data writing unit 23 writes the decompressed data in the transmission data storage memory 20. Normally, the data width that can be written to the transmission data storage memory 20 at a time is smaller than the data width of the expanded data, so the expanded data is written over a plurality of clocks.

  The transmission data management unit 21 ensures that the next expanded data is not written while the expanded data writing unit 23 writes the expanded data to the transmission data storage memory 20. In one implementation example, while the expanded data writing unit 23 is writing data, the free buffer notification amount is set to 0, and the hardware interface unit and the transmission software interface 22 are notified so as not to generate a new access request. It is to be.

  The transmission software interface 22 is an interface for requesting the software processing unit 4 to transfer transmission data via the processor bus 6. The transmission software interface 22 has means for confirming the amount of free buffer in the transmission data storage memory 20, means for setting the content of transmission data, and means for requesting transmission of transmission data.

  As described above, in the transmission circuit 2-1, for both the hardware interface and the software interface, means for confirming the free buffer amount of the transmission data storage memory 20, means for setting the contents of the transmission target data, actual data transmission Provide a means to request

  Next, the operation of the engine / processor cooperation system 8 of the present invention will be described.

  First, an operation example when input data is processed by the high-speed engine 30 is shown. FIG. 4 is a diagram for explaining the flow of input data when the input data is processed by the high-speed engine 30.

  When receiving the packet command data, the MUX circuit 7 transfers the command to the session data read processing unit 52.

  The session data read processing unit 52 reads the session data of the session from which the packet command data is transmitted from the session data memory 50, and outputs the read session data and packet command data to the receiving circuit 1.

  When receiving the packet command data and the session data, the receiving circuit 1 expands the received data by the data expansion processing unit 13 and then notifies the processing selection unit 31 of packet reception.

  The processing selection unit 31 refers to the expanded received data, determines whether the high speed engine 30 should perform processing or the software processing unit should perform processing based on a predetermined calculation rule, and a processing management unit 32.

  The processing management unit 32 sets the processing state to the processing state of the high-speed engine 30 so that when the software processing unit 4 checks the processing state of the processing management unit 32, there is no data to be processed by the software processing unit 4. To be notified.

  The processing selection unit 31 notifies the high-speed engine 30 that the high-speed engine 30 should process the expanded reception data, so that the high-speed engine 30 performs arithmetic processing on the expanded reception data. The data to be transmitted is determined based on the calculation result, and a data transmission notification is output to each transmission circuit 2.

  When the high-speed engine 30 outputs the data transmission notification, the high-speed engine 30 notifies the processing management unit 32 that the processing of the high-speed engine 30 is completed. However, in a system configuration in which the processing in the high speed engine 30 is determined to be completed in a fixed cycle, the processing management unit 32 may independently recognize the completion of the processing in the high speed engine 30.

  The process management unit 32 recognizes that the process of the current process target data is completed, and notifies the reception circuit 1 and the process selection unit 31 that the process is completed.

  The reception data management unit 11 of the reception circuit 1 relates to whether or not the next command is accumulated until the completion of command processing is notified. If the next command is stored, the data expansion processing unit 13 expands the received data again. After the completion of the command processing is notified, the process selection unit 31 is notified of packet reception.

  In the engine / processor cooperation system 8 of the present invention, only the software processing unit 4 executes low-speed software processing.

  When received data is processed by the high-speed engine 30, it operates only by hardware operation without going through a low-speed software processing unit, so that high-speed processing without software processing is possible. .

  Next, an operation example when input data is processed by the processor 40 of the software processing unit 4 will be described. 5 and 6 are diagrams for explaining the flow of input data when the input data is processed by the processor 40. FIG. 5 is a diagram in the case of notifying the reception circuit 1 of the completion of processing via the processing management unit 32, and FIG. 6 is a diagram in the case of notifying the reception circuit 1 of the completion of processing directly. is there.

  When receiving the packet command data, the MUX circuit 7 transfers the command to the session data read processing unit 52. The session data read processing unit 52 reads the session data from the session data memory 50 and outputs it to the receiving circuit 1.

  The receiving circuit 1 notifies the processing selection unit 31 that the input data has been received, and the processing selection unit 31 determines which of the high-speed engine 30 and the processor 40 of the software processing unit 4 should process, and the processing management unit The operation is the same up to the point of notification to 32.

  When the process selection unit 31 notifies that the input data is a software process target, the process management unit 32 changes the process state to a software processable state. The processor 40 in the software processing unit reads the processing status register of the processing management unit 32 by polling via the processor bus 6 and recognizes that the target data is a command to be executed by the software processing unit.

  The processor 40 reads the target data from the received data storage memory 10 via the reception software interface 12 of the reception circuit 1 and executes necessary arithmetic processing. After the calculation, the processor 40 notifies the reception software interface 12 of the reception circuit 1 that the processing has been completed via the processor bus 6 or the process management unit 32, and also to each transmission circuit 2 Notify the necessary command transmission process.

  When the processor 40 notifies that the processing is completed via the processor bus 6, the processor 40 notifies the processing management unit 32 of the completion of the processing of the target data.

  When the software processing unit 4 notifies the processing completion of the target data, the processing management unit 32 sets the processing state register in the idle state and notifies the processing selection unit 31 that the next command can be processed.

  Next, an example of operation timing when the high-speed engine 30 operates in the engine / processor cooperation system 8 of the present invention will be described.

  FIG. 7 is a diagram for explaining an example of operation timing when the high-speed engine 30 operates in the engine / processor cooperation system 8 of the present invention.

  When the high-speed engine 30 is operating, the packet command data is transmitted in the order of the MUX circuit 7, the session data read processing unit 52, the reception circuit 1, the processing selection unit 31, the high-speed engine 30, the session transmission circuit 2, and the session data write processing unit 53. Is processed. The numbers in the squares in FIG. 7 mean identification information for uniquely identifying a session.

  Each processing block is pipelined, and when a command for session 2 is received after reception of packet command data for session 1, each block can process packet command data continuously. The third command for session 1 waits for the session data read processing until the second command processing for session 1 is completed and session data write processing unit 53 unlocks the corresponding session.

  As described above, even when the processing of each block is pipelined, in a situation where commands of the same session are input at a short time interval, the processing performance deteriorates due to the waiting process in the session data read processing unit 52. .

  In order to prevent deterioration in processing performance, it is important to shorten the time from session data read processing unit 52 reading session data to session data write processing unit 53 updating session data. .

  Here, the session lock memory 51 will be described in more detail.

  The session lock memory 51 manages whether or not the session is locked for each session number that can uniquely identify the session.

  The session is in a locked state when the corresponding session data in the session data memory 50 is being read and new reading is prohibited. If the session is not locked, the corresponding session data can be read.

  The session data read processing unit 52 writes the corresponding session number in the session lock memory 51 in the locked state when reading the session data from the session data memory 50.

  When receiving a command related to the session number in the locked state, the session data read processing unit 52 waits until the locked state is released because reading of the corresponding session is prohibited. The locked state is released when the session data write processing unit 53 writes the updated session data entry to the session data memory 50.

  The session data read processing unit 52 transmits the updated session data as the session data together with the reception command to the receiving circuit at the timing when the locked state is released, and sets the corresponding session number in the session lock memory 51 to the locked state again. .

  In the example of FIG. 7, only when the third command for the session 1 is received, the session is in the locked state (value 1), so that a lock release waiting has occurred.

  Thus, in the engine processor cooperation system 8 of the present invention, the transmission circuit and the reception circuit 1 have a high-speed interface for transferring data developed for the hardware processing unit 3, and the transmission circuit is a high-speed interface. During command processing in the engine 30, the next command data is expanded in advance, thereby reducing the overall delay.

  Next, an embodiment of the engine / processor cooperation system of the present invention will be described.

  FIG. 8 is a configuration example of the server system 110 to which the TCP offload processing unit 110 using the engine / processor cooperation system 8 of the present invention is applied.

  The server device 100 includes a TCP offload processing unit 110, a CPU 101, a main memory 102, and a bus 103. The server device 100 is connected to an external network, and communicates with an opposite host (server, personal computer, etc.) using TCP. The CPU 101 transmits and receives a packet from the opposite host via the TCP offload processing unit 110.

  The TCP offload processing unit 110 includes a network transmission / reception unit 111, a packet reception unit 112, a packet transmission unit 113, a host connection unit 114, and an engine / processor cooperation system 8.

  An operation example when a TCP packet is transmitted from the opposite host to the server apparatus 100 will be described.

  A packet transmitted from the opposite host to the server device 100 is input to the packet receiving unit 112 via the network transmission / reception unit 111.

  The packet receiving unit 112 identifies to which session the received packet belongs. Specifically, in the case of a TCP session, the session is identified by a combination of a transmission IP address, a transmission TCP port, a reception IP address, and a reception TCP port. The server device manages the session by a session number for uniquely identifying the identified session. In the case of a new session, the packet receiving unit 112 assigns a new session number.

  The packet receiving unit 112 temporarily accumulates the received packets, extracts the TCP header, and transfers the session number, a flag indicating whether the session is new, and the TCP header to the engine / processor cooperation system 8 as one received packet command. To do.

  When the engine / processor cooperation system 8 receives the received packet command, the engine / processor cooperation system 8 executes processing for the corresponding received packet command and transfers the received packet processing result to the packet receiving unit 112.

  When receiving the received packet processing result from the engine / processor cooperation system 8, the packet receiving unit 112 transfers the payload data of the received packet to the main memory via the host connection unit 114 and the bus 102 according to the content of the received packet processing result. At the same time, it notifies the CPU 101 that data has been received as necessary. As a method of notifying the CPU 101, there are a method of using an interrupt, a method of writing data in a specific area of the main memory, and a method of polling access to the corresponding memory area from the CPU 101. .

  Next, an operation example when a TCP packet is transmitted from the server apparatus 100 to the opposite host will be described.

  The CPU 101 writes the transmission payload data in the main memory 102 and notifies the TCP offload processing unit 110 that a transmission request is made. This transmission request is input to the host connection unit 114 of the TCP offload processing unit 110 as a transmission request command. As a transmission method of the transmission request command, the CPU 101 directly transfers the command to the host connection unit 114, the command itself is written in the main memory 102, and the CPU 101 notifies the host connection unit 114 that the transmission request command exists. Thus, there is a method in which the host connection unit 114 reads the transmission request command from the main memory 102, but either of them may be used in the present invention.

  The transmission request command is input to the engine / processor cooperation system 8 of the present invention via the host connection unit 114.

  The engine / processor cooperation system 8 processes the transmission request command, determines payload data to be transmitted, and notifies the packet transmission unit 112 of the packet transmission request.

  When receiving the packet transmission request, the packet transmission unit 112 reads the requested payload data from the main memory 102 and generates a transmission packet, and transmits the transmission packet to the outside via the network transmission / reception unit 111.

  When the connection destination server device (opposite host) receives a packet with a payload from the server device 100, the server device 100 sends information indicating how far the packet has been received to the server device 100 as an ACK packet. The ACK packet transmitted from the opposite host to the server device 100 is input to the packet receiving unit 113 via the network transmission / reception unit 111.

  The packet receiving unit 113 resolves the session number in the same way as when receiving a normal data packet, and links the received packet command including the session number, new session flag (not new here), and TCP header to the engine and the processor. Output to system 8.

  The engine / processor cooperation system 8 determines how much payload data has been received by the opposite host from the contents of the TCP header for the session of the corresponding session number, and sends a transmission completion command to the main memory via the host connection unit 114. Write to 102 and notify the CPU 101.

  The CPU 101 refers to the transmission completion command to identify how far the transmission requested data has been transmitted, and releases the completed data. When the engine / processor cooperation system 8 receives a transmission request command from the CPU 101, the engine / processor cooperation system 8 does not always transmit all of the designated transmission payload data at a time. TCP has a flow control mechanism, and data that can be transmitted at a time is limited. Therefore, when the amount of data that can be sent is sent, when an ACK packet is input from the opposite host and a packet reception command is received, it is checked whether there is any new send payload data that can be sent. Reads out the payload data portion that can be sent out, packetizes it, and sends it to the opposite host.

  FIG. 9 shows an example of entry of session data held in the session data memory 50.

The session data memory 50 manages the following session data for each session identified by the session number.
• state: Session state. Session probability in progress (SYN_RECEIVED, SYN_SENT), session establishment status (SYN_ESTABLISHED), session disconnection, etc., session unused status (CLOSED)
-Rcv_nxt: Shows how much data has been received from the opposite host-rcv_wnd: Shows how much data can be received in addition to rcv_nxt-snd_una: How far the opposite host receives the transmission target data of the server device 100 Indicates whether or not
Snd_nxt: indicates how far the transmission target data of the server apparatus 100 has been transmitted.
-Snd_wnd: Data size that can be sent (Strictly speaking, it is a value determined by the complex factors of several parameters, but it is simplified to one parameter)
Snd_req: Data end position of the transmission target data of the server apparatus 100

  FIG. 10 shows a relationship image diagram of session data parameters.

  First, transmission data management parameters will be described.

  Applying the example of session number 3 in the session data memory in Fig. 9, the data up to the 399th byte in the 1500byte (0-1499byte) transmission request data has been received by the opposite host, from the 400th byte to the 999th byte This means that ACK has not been returned yet, but the data from 1000 bytes to 1499 bytes is not transmitted yet. The reason why only 600 bytes up to 400-999 bytes are sent is that the amount of data that can be sent is limited to 600 bytes by snd_wnd.

  Next, received data management parameters will be described. Data is received up to the 699th byte, and waiting for reception after the 700th byte. Since 400 bytes of data can be received, it can be seen that 699 + 4000 = 4699 bytes can be received. Note that these session data parameters are relative values corresponding to TCP SEQ numbers and ACK numbers, and their initial values do not always start from zero.

  Note that the above is only part of the session data included in the TCP session, and there are actually more types of session data.

  FIG. 11 shows an example of updating the entry of the session data memory in the reception process. FIG. 11 shows an example of updating the session data memory entry when the session data memory 50 receives a TCP packet of session number 3 from the outside.

  The process selection unit 31 selects the process in the high-speed engine 30 only when the rcv_nxt and the first byte position of the received TCP header match, and selects the process in the processor 40 when they do not match.

  In the state of the session data memory in FIG. 9, with session number 3, data is received up to the 699th byte, and reception is awaited after the 700th byte.

  Assume that the first received TCP packet contains data up to 700-1199 bytes.

  The TCP packet command including the TCP header and the session data read via the session data read processing unit 52 are input to the receiving circuit 1.

  The process selection unit 31 selects that the high-speed engine 30 processes the command because the value of the leading byte position of the TCP packet matches the value of rcv_nxt.

  The high-speed engine 30 identifies that the 700-1199th byte has been received, notifies the session transmission circuit 2-1 to update to rcv_nxt = 1200, rcv_wnd = 3500, and receives the 700-1199th byte via the external transmission circuit 2-2. That the data is transferred to the main memory 102.

  New session data is transmitted from the session transmission circuit 2-1, and the session data write processing unit 53 updates the session data.

  Next, it is assumed that the received TCP packet includes data up to 900-1399bye.

  Similarly, the TCP header and the updated session data are input to the processing selection unit 31 via the receiving circuit 1.

  The process selection unit 31 selects the process in the processor 40 because the value of the leading byte position of the TCP packet does not match the value of rcv_nxt.

  The processor 40 recognizes that the 900-1199 bytes portion of the received packet is already received data, and the data from 1200 to 1399 bytes are newly received data.

  The update to rcv_nxt = 1400 and rcv_wnd = 3300 is transmitted to the session transmission circuit 2-1, and notification is made that only the data of 1200-1399 bytes are transferred to the main memory 102 via the external transmission circuit 2-2.

  Next, it is assumed that a command indicating that the reception area can be extended by 1000 bytes is input from the CPU 101 as a reception area expansion command.

  The reception area extension command and the session data are input to the process selection unit via the reception circuit, and the process selection unit 31 selects processing in the high speed engine 30 (the reception area extension command is set to always be processed in the high speed engine) Suppose)

  The high-speed engine 30 extends the value of rcv_wnd to 4300 and updates the session data entry via the session transmission circuit.

  As described above, according to the present invention, when the processing is realized by the hardware engine, the entire processing is performed without going through the software processing unit. It is possible to use the maximum performance of the hardware engine without incurring.

  Further, according to the present invention, after the data expansion processing unit expands the head data in the reception data storage memory and delivers it to the hardware interface, the next command arrives in the reception data storage memory. The high-speed engine is configured to read data from the received data storage memory in advance, perform data expansion in the data expansion processing unit, and deliver the data to the hardware interface as soon as a processing completion notification is input. It is possible to speed up the process.

  Furthermore, the session data read processing unit reduces the amount of data required for reading, thereby reducing the time required for reading session data in the session data read processing unit and the time required for developing read data in the data development processing unit. Is possible.

FIG. 1 is a block diagram of an engine / processor cooperation system according to the present invention. FIG. 2 is a block diagram of the receiving circuit. FIG. 3 is a block diagram of the transmission circuit. FIG. 4 is a diagram for explaining the flow of input data when processing is performed by hardware. FIG. 5 is a diagram for explaining the flow of input data when processing is performed by software. FIG. 6 is a diagram for explaining the flow of input data when processing is performed by software. FIG. 7 is an example of operation timing in the present invention. FIG. 8 is a block diagram of an apparatus to which the present invention is applied. FIG. 9 is a diagram illustrating an example of session data. FIG. 10 is an image diagram for explaining the relationship between session data parameters. FIG. 11 is a diagram for explaining an example of updating an entry in the session data memory in the reception process. FIG. 12 is a block diagram of a conventional arithmetic system. FIG. 13 is a block diagram of a conventional software computing system. FIG. 14 is a block diagram of a conventional hardware calculation system. FIG. 15 is a block diagram of the first conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reception circuit 2 Transmission circuit 2-1 Session transmission circuit 2-2 External transmission circuit 3 Hardware processing part 4 Software processing part 5 Session data read-out processing part 6 Processor bus 7 MUX circuit 8 Engine processor cooperation system 10 Received data storage memory DESCRIPTION OF SYMBOLS 11 Reception data management part 12 Reception software interface 13 Data expansion | deployment process part 20 Transmission data storage memory 21 Transmission data management part 22 Transmission software interface 23 Expansion | deployment data writing part 30 High speed engine 31 Process selection part 32 Process management part 40 Processor 41 Memory 42 Peripheral circuit 50 Session data memory 51 Session lock memory 52 Session data read processor 53 Session data write processor

Claims (5)

An engine-processor linkage system,
A session data memory managing session data indicating the transmission / reception status of data for each TCP session;
A reading unit for reading session data of a TCP session to which the input data belongs, from the session data memory;
An accumulation unit for accumulating the input data and the read session data;
A developing unit that expands the stored input data and session data into a format accessible by a hardware processing unit;
A processing determination unit that refers to the expanded data and determines whether the stored input data is processed by software or a hardware processing unit based on a predetermined calculation rule; and the processing A hardware processing unit having a high-speed engine for processing the expanded input data when the determination unit determines to process in the hardware processing unit;
A software processing unit for processing the stored input data when the processing determination unit determines to process with a software processing unit;
An update unit that updates session data of a TCP session to which the input data belongs when the processing of the input data is completed;
The expansion unit monitors whether the next input data is stored in the storage unit, if the next input data is accumulated read it, expand, processing completion notification from the high-speed engine The engine / processor cooperation system , wherein the expanded input data is transferred to the hardware processing unit upon receipt of . The input data includes a command related to packet transmission and reception,
2. The engine / processor cooperation system according to claim 1, wherein the hardware processing unit and the software processing unit process the input command.   The reading unit does not read session data of a session to which the input data belongs while the input data stored in the high-speed engine or the software processing unit is being processed. The engine / processor cooperation system according to claim 2.   The said expansion | deployment part expand | deploys the head data of the said accumulation | storage part, and it is comprised so that it can access at once from a hardware processing part, The Claim 1 characterized by the above-mentioned. Engine / processor linkage system.   The said software processing part accesses the said session data memory directly via a processor bus | bath in order to access the session data which has not been read, when processing the said input data. 5. The engine / processor cooperation system according to any one of 4).

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