JP5586267B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a so-called POP (Package On Package) structure semiconductor device in which two packages are stacked.

  Since the semiconductor device having the POP structure is configured by combining individual packages that are inspected at the package level and whose operation is guaranteed, it has an advantage that a decrease in yield due to chip defects can be suppressed. It is superior to the so-called MCP (Multi Chip Package) in which two chips are mounted in one package.

  As a document describing a POP semiconductor device in which a memory chip and a data processing chip such as a microcomputer are mounted, there is, for example, Patent Document 1. This provides a structure in which when a plurality of SDRAM chips are mounted in a DDR type SDRAM package, the wiring paths from each SDRAM chip to the microcomputer are of equal length. In Patent Document 2, a data signal is used to improve signal quality such as a data signal by reducing wiring impedance on a module substrate when a plurality of DDR SDRAMs are mounted on a module substrate together with a microcomputer. In addition, the arrangement of the memory interface circuit of the microcomputer is determined so that the data system signal can be wired closer to the SDRAM chip than the address command system signal so that the signals such as the data strobe signal can be easily organized in functional units. Is described.

JP 2008-16519 A JP 2006-237385 A

  However, in the POP structure, depending on the relationship between the terminal arrangement of the package substrate disposed above and the terminal arrangement of the microcomputer chip on the circuit board on which the package substrate is mounted, the microcomputer chip and the package terminal are connected correspondingly. It has been studied by the present inventor that the wiring route on the circuit board to be complicated is complicated. For example, when the memory interface terminal of a microcomputer chip is locally arranged on the edge of the chip, the routing of wiring to the package terminal that is generally unevenly distributed in the SDRAM package arranged above becomes complicated. Along with this, there is a problem that it becomes difficult to route wiring connected to other data processing terminals of the microcomputer chip, and there is a possibility that analog signal wiring and high-speed digital wiring are mixed, which may cause malfunction. The problem arises that the substrate must be enlarged.

  An object of the present invention is to shorten a wiring path for connecting a data processing semiconductor chip and a memory semiconductor chip on a wiring substrate on which the data processing semiconductor chip is mounted in a semiconductor device having a POP structure.

  Another object of the present invention is to reduce the size of a wiring substrate on which a data processing semiconductor chip is mounted and a package substrate for a memory semiconductor chip is mounted thereon in a semiconductor device having a POP structure.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the arrangement of the data system package terminal group and the address command system package terminal group of the package board on which the memory semiconductor chip is mounted, and the data system chip terminal group and address command of the data processing semiconductor chip on the wiring board on which the memory semiconductor chip is mounted The data command chip terminal group is divided and arranged in different areas on the edge of the data processing semiconductor chip corresponding to the arrangement of the data package terminal group, and the address command chip A POP structure is adopted in which the terminal group is arranged at the edge of the data processing semiconductor chip corresponding to the arrangement of the previous address command system package terminal group.

  As a result, the spatial positional relationship between the package terminal group of each of the data system and the address command system and the chip terminal group is associated, the length of the wiring path connecting the corresponding terminals is shortened, and a plurality of bits are operated in parallel. The data system chip terminal group is divided and arranged so as not to obstruct wiring connection to other chip terminals of the data processing semiconductor chip, and contributes to the miniaturization of the wiring board.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the wiring path for connecting the data processing semiconductor chip and the memory semiconductor chip can be shortened on the wiring board on which the data processing semiconductor chip is mounted in the semiconductor device having the POP structure, and the wiring board can be made smaller. Can contribute.

1 is a cross-sectional view taken along line AA in FIG. FIG. 2 is a longitudinal sectional view illustrating a semiconductor device having a POP structure according to an embodiment of the invention. FIG. 3 is a plan view specifically illustrating the main terminal arrangement of the data system package terminal group and the address command system package terminal group. FIG. 4 is a plan view specifically illustrating the main terminal arrangement of the data system chip terminal group and the address command system chip terminal group. FIG. 5 is an explanatory diagram illustrating the connection correspondence on the circuit board between the data system chip terminal group and address command system chip terminal group and the data system package terminal group and address command system package terminal group. 6 is a cross-sectional view taken along line BB in FIG. FIG. 7 is a longitudinal sectional view illustrating a semiconductor device having a POP structure according to another embodiment of the invention. FIG. 8 is a partial plan view of a POP structure according to a comparative example.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (1, 2) according to a typical embodiment of the present invention includes a wiring board and a data processing semiconductor chip (101, 301) mounted on the wiring board (100, 300). ), A package substrate (200, 400) mounted on the wiring substrate over the data processing semiconductor chip, and a memory semiconductor chip (201, 401) built in the package substrate. The package substrate is connected to the memory semiconductor chip and disposed outside the outer periphery of the data processing semiconductor chip, and includes a data system package terminal group (210, 211, 410) including a data terminal and a data strobe terminal. 413) and address command system package terminal groups (212, 414) including address terminals and command terminals, and the data system package terminal groups are divided and arranged in different regions of the package substrate. The data processing semiconductor chip includes a data system chip terminal group (110, 111, 310 to 313) including a memory control data terminal and a data strobe terminal, and an address command system chip terminal group (112) including an address terminal and a command terminal. 314), and the data system chip terminal group is divided and arranged in different regions on the edge of the data processing semiconductor chip corresponding to the arrangement of the data system package terminal group, and the address command system chip terminal group Are arranged at the edge of the data processing semiconductor chip corresponding to the arrangement of the previous address command system package terminal group.

  As a result, the spatial positional relationship between the package terminal group of each of the data system and the address command system and the chip terminal group is associated, and the length of the wiring path connecting the corresponding terminals is shortened. Further, the data system chip terminal group in which a plurality of bits are operated in parallel is divided and does not interfere with the wiring connection to the other chip terminals of the data processing semiconductor chip. Therefore, it contributes to the miniaturization of the wiring board.

  [2] In the semiconductor device of item 1, the terminal pitch of the chip terminal group is smaller than the terminal pitch of the package terminal group (FIGS. 1 and 6). The relationship of the terminal pitch further congests the wiring connected to the chip terminal, so that the superiority of the means is increased.

  [3] In the semiconductor device according to item 1 or 2, the divided data system chip terminal groups are arranged close to the corner of the data processing semiconductor chip (FIGS. 1 and 6). If the data system chip terminal group is arranged close to the corner of the data processing semiconductor chip, there are many chip terminals on the same side, and wiring to other chip terminals on the same side is free. The degree increases.

  [4] In the semiconductor device according to item 1 or 2, terminals other than the data system chip terminals are disposed between the divided data system chip terminal groups (FIGS. 1 and 6). It is possible to prevent the possibility that the number of data system chip terminal groups that are arranged in parallel becomes too large and the degree of freedom of wiring to other chip terminals existing on the same side is significantly hindered.

  [5] In the semiconductor device according to any one of Items 1 to 4, each of the divided data system chip terminal groups is synchronized with at least a data strobe terminal (LPBDQS0...) And a data strobe signal of the data strobe terminal. It includes a pair with data terminals (LPBDQ0 to LPBDQ7...) Assigned to the data to be changed. From the viewpoint of memory control, it becomes easy to ensure the integrity of data and data strobe control for the data when the data system chip terminal group is dividedly arranged. In short, the configuration of the memory control circuit is not complicated.

  [6] In the semiconductor device of [5], the data terminals of each of the divided data system chip terminal groups have a bit number that is an integral multiple of 8 bits. For example, it is 8 bits or 16 bits.

  [7] In the semiconductor device according to any one of [1] to [6], the chip terminal includes an analog terminal group (315, 316), and the analog terminal group disposed along the same side of the data processing semiconductor chip; Each of the divided data system chip terminal groups (310 to 313) is arranged separately at different corners of the data processing semiconductor chip or along different sides across the corner of the data processing semiconductor chip. Arranged. As a result, the wiring connected to the analog terminal group can be easily separated from the wiring connected to the data system chip terminal group.

  [8] In the semiconductor device according to any one of items 1 to 7, the package terminal group of the package substrate is a BGA terminal (202, 402).

  [9] In the semiconductor device according to any one of items 1 to 8, the memory semiconductor chip is a synchronous DRAM, and the data processing semiconductor chip is a microcomputer.

  [10] A semiconductor device according to another embodiment of the present invention includes a wiring board, a data processing semiconductor chip mounted on the wiring board, and the wiring board overlaid on the data processing semiconductor chip. A package substrate mounted thereon; and a memory semiconductor chip embedded in the package substrate. The wiring board has the data processing semiconductor chip mounted on one surface, connected to a predetermined chip terminal of the mounted data processing semiconductor chip, and a stack terminal disposed on the one surface outside the data processing semiconductor chip. And a mounting terminal connected to a predetermined chip terminal of the data processing semiconductor chip on the other surface. The package substrate has the memory semiconductor chip mounted thereon, and has an external connection package terminal connected to a memory chip terminal of the mounted memory semiconductor chip, and the external connection package terminal corresponds to the corresponding stack terminal. Combined with each other. The package terminal includes a data system package terminal group including a data terminal and a data strobe terminal, and an address command system package terminal group including an address terminal and a command terminal, and the data system package terminal group is a different area of the package substrate. It is divided and arranged. The chip terminal includes a data system chip terminal group including a data terminal for data control and a data strobe terminal, and an address command system chip terminal group including an address terminal and a command terminal, and the data system chip terminal group includes the data system The data processing semiconductor chip is divided and arranged in different areas corresponding to the arrangement of the package terminal group, and the address command chip terminal group corresponds to the arrangement of the previous address command package terminal group. The semiconductor chip is disposed on the edge of the semiconductor chip.

  As a result, the spatial positional relationship between the package terminal group of each of the data system and the address command system and the chip terminal group is associated, and the length of the wiring path connecting the corresponding terminals is shortened. Further, the data system chip terminal group in which a plurality of bits are operated in parallel is divided and does not interfere with the wiring connection to the other chip terminals of the data processing semiconductor chip. Therefore, it contributes to the miniaturization of the wiring board.

  [11] In the semiconductor device of item 10, a terminal pitch of the chip terminal group is smaller than a terminal pitch of the package terminal group.

  [12] In the semiconductor device of item 11, each of the divided data system chip terminal groups is arranged close to a corner portion of the data processing semiconductor chip.

  [13] In the semiconductor device as described in [11], terminals other than data system chip terminals are arranged between the divided data system chip terminal groups.

  [14] In the semiconductor device of item 12 or 13, each of the divided data system chip terminal groups is assigned to at least a data strobe terminal and data changed in synchronization with a data strobe signal of the data strobe terminal. Including pairs with data terminals.

  [15] In the semiconductor device of item 14, the data terminals of each of the divided data system chip terminal groups have a bit number that is an integral multiple of 8 bits.

  [16] In the semiconductor device of items 10 to 15, the chip terminal includes an analog terminal group, and the analog terminal group arranged along the same side of the data processing semiconductor chip and the divided data system chip terminals. Each of the groups is arranged separately from different corner portions of the data processing semiconductor chip or arranged along different sides with the corner portion of the data processing semiconductor chip interposed therebetween.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 2 is a vertical cross-sectional view of a semiconductor device having a POP structure according to an embodiment of the present invention.

  The semiconductor device 1 includes a wiring board 100, a microcomputer chip (MCU) 101 as a data processing semiconductor chip mounted on the wiring board 100, and the wiring board 100 overlaid on the microcomputer chip 101. A package substrate 200 mounted on the package substrate 200 and a SDRAM (Synchronous Dynamic Random Access Memory) chip (MRY) 201 in a DDR (Double Data Rate) form, for example, as a memory semiconductor chip built in the package substrate 200.

  The wiring board 100 has a plurality of wiring layers and is made of glass epoxy resin or the like, and a plurality of lands on which the microcomputer chip 101 is mounted and wirings connected to them are formed on the first main surface thereof. On the outside of the microcomputer chip 101, a stack terminal 103 is formed on which a package terminal 202 formed on the package substrate 200 of the SDRAM 201 is mounted and coupled. The package terminals 202 are formed in a BGA (Ball Grid Array) shape by solder bump electrodes, and the stack terminals 103 are formed by lands. Mounting terminals 102 for mounting the semiconductor device 1 on a mother board (not shown) are formed on the second main surface of the wiring board 100. The mounting terminal 102 is configured in a BGA shape by, for example, solder bump electrodes. Although not particularly limited, the main body of access to the SDRAM chip 201 is the microcomputer chip 101, and the SDRAM interface terminal of the microcomputer chip 101 is connected to the corresponding stack terminal 103 via the wiring of the surface layer wiring layer. The other interface terminals are connected to the corresponding mounting terminals 102 via wiring and vias of a predetermined wiring layer.

  A part of the mounting terminal 102 is allocated for power supply of power supply voltage and ground voltage, and these are connected to the power supply and ground terminals of the microcomputer chip 101 through wiring and vias of a predetermined wiring layer. , Connected to the power supply and ground terminals of the SDRAM chip 201. A test land (not shown) as an external test terminal is exposed at the center of the second main surface of the wiring board 100 and connected to the stack terminal 103 to be sampled for the test.

  FIG. 1 shows a cross section taken along line AA in FIG.

  The package terminal 202 of the SDRAM chip 201 is a terminal connected to the memory chip terminal of the SDRAM chip 201, and the package substrate 200 is configured by, for example, WPP (Wafer Process Package) or CSP (Chip Size Package). For example, when assuming a DDR2-SDRAM having a parallel data bit number of 32 bits as an SDRAM chip, the main terminal arrangement of the package terminal 202 includes data system package terminal groups 210 and 211 including a data terminal and a data strobe terminal, and an address terminal. And an address command package terminal group 212 including command terminals.

  A specific example of the terminal arrangement is shown in FIG. 3 is aligned with the orientation of FIG. 1 by reversing the top and bottom and the left and right.

  The data system package terminal group 210 includes a first data byte system package terminal group (MRYD_FST) 210A and a third data byte system package terminal group (MRYD_TRD) 210B. The data system package terminal group 211 includes a second data byte system package terminal group (MRYD_SCD) 211A and a fourth data byte system package terminal group (MRYD_FRT) 211B. The respective data system package terminal groups 210 and 211 are divided and arranged in different regions of the package substrate 200.

  The first data byte system package terminal group (MRYD_FST) 210A includes byte data DQ7 to DQ0 (DQ [7: 0]), a data strobe signal DQS0 which is an input / output synchronization signal of the byte data DQ [7: 0], and inverted data. Each terminal of the data mask signal DM0 for selectively performing input / output masking of the strobe signal DQS0B and the byte data DQ [7: 0] is provided. The third data byte system package terminal group (MRYD_TRD) 210B includes byte data DQ23 to DQ16 (DQ [23:16]), a data strobe signal DQS2 which is an input / output synchronization signal of the byte data DQ [23:16], and inverted data. Each terminal has a strobe signal DQS2B and a data mask signal DM2.

  The second data byte system package terminal group (MRYD_SCD) 211A includes byte data DQ15 to DQ8 (DQ [15: 8]), a data strobe signal DQS1 which is an input / output synchronization signal of byte data DQ [15: 8], and inverted data. Each terminal of the data mask signal DM1 for selectively performing input / output masking of the strobe signal DQS1B and the byte data DQ [15: 8] is provided. The fourth data byte system package terminal group (MRYD_FRT) 211B includes byte data DQ31 to DQ24 (DQ [31:24]), a data strobe signal DQS3 which is an input / output synchronization signal of the byte data DQ [31:24], and inverted data. Each terminal has a strobe signal DQS3B and a data mask signal DM3.

  The address command system package terminal group 212 includes terminals of address signals CA9 to CA0 (CA [9: 0]), a clock enable signal CKE, a chip select signal CSB, a clock signal CK, and an inverted clock signal CKB of the clock signal CK. .

  Note that power supply terminals and ground terminals are unevenly distributed in the data system package terminal groups 210 and 211 and the address command system package terminal group 212 so that necessary power supply capability to each part of the SDRAM chip 201 can be secured. Has been taken into account.

  In response to the arrangement of the package terminal groups 210 and 211 of the SDRAM chip 200, the chip terminal of the microcomputer chip includes a data terminal for memory control and a data strobe terminal as illustrated in FIG. A terminal group 110 and 111; and an address command system chip terminal group 112 including an address terminal and a command terminal. The data system chip terminal group 110 and 111 correspond to the arrangement of the data system package terminal groups 210 and 211. The address command system chip terminal group 112 is divided and arranged on the edge of the microcomputer chip 101 in correspondence with the arrangement of the previous address command system package terminal group 212. . 150 is a generic name for signal wiring for connecting the data system chip terminal group 110 to the data system package terminal group 210, and 151 is for connecting the data system chip terminal group 111 to the data system package terminal group 211. Signal wiring is generically referred to, and 152 is a generic designation for wiring that connects the address command chip terminal group 112 to the address command package terminal group 212.

  A specific example of the terminal arrangement of the data system chip terminal groups 110 and 111 and the address command system chip terminal group 112 is shown in FIG. 4 is aligned with the orientation of FIG. 1 by turning it upside down. FIG. 4 is based on the configuration of the package terminal of FIG.

  A large number of chip terminals 160 composed of pad electrodes are arranged on the outermost peripheral edge of the microcomputer chip 101, and an input / output circuit 170 such as an input / output buffer is arranged on the inner side thereof. A logic circuit such as a central processing unit (CPU) 131 and a memory controller (DDRCNT) 130 that performs memory control of the SDRAM chip 201, an analog circuit (not shown), and the like are arranged.

  The data system chip terminal group 110 includes a first data byte system chip terminal group (MCUD_FST) 110A and a second data byte system package terminal group (MCUD_SCD) 110B. An input / output circuit group 120 is connected to the data system chip terminal groups 110A and 110B. The data system chip terminal group 111 includes a third data byte system chip terminal group (MCUD_TRD) 111A and a fourth data byte system package terminal group (MCUD_FRT) 111B. Reference numeral 121 denotes an input / output circuit group connected to the data system chip terminal groups 111A and 111B. Each of the data system chip terminal groups 110 and 111 is divided and arranged in regions on different sides of the wiring board 100.

  The first data byte group chip terminal group (MCUD_FST) 110A includes byte data LPBDQ7 to LPBDQ0 (LPBDQ [7: 0]), data strobe signal LPBDQS0 which is an input / output synchronization signal of byte data LPBDQ [7: 0], and inverted data. Each terminal of the data mask signal LPBDM0 that selectively performs input / output masking of the strobe signal DQS0B and the byte data LPBDQ [7: 0]. The second data byte group chip terminal group (MCUD_SCD) 110B includes byte data LPBDQ15 to LPBDQ8 (LPBDQ [15: 8]), a data strobe signal LPBDQS1, which is an input / output synchronization signal of byte data LPBDQ [15: 8], and inverted data. Each terminal has a strobe signal LPBDQS1B and a data mask signal LPBDM1.

  The fourth data byte system package terminal group (MRYD_FRT) 111B includes byte data LPBDQ31 to LPBDQ24 (LPBDQ [31:24]), data strobe signal LPBDQS3 which is an input / output synchronization signal of byte data LPBDQ [31:24], and inverted data. Each terminal of the data mask signal LPBDM3 for selectively performing input / output masking of the strobe signal LPBDQS3B and the byte data LPBDQ [31:24] is provided. The third data byte system package terminal group (MRYD_TRD) 111A includes byte data LPBDQ23 to DQ16 (LPBDQ [23:16]), data strobe signal LPBDQS2 which is an input / output synchronization signal of byte data LPBDQ [23:16], and inverted data. Each terminal has a strobe signal LPBDQS2B and a data mask signal LPBDM2.

  The address command system chip terminal group 212 includes terminals of address signals LPBCA9 to CA0 (LPBCA [9: 0]), a clock enable signal LPBCKE, a chip select signal LPBCSB, a clock signal LPBCK, and an inverted clock signal LPBCKB of the clock signal LPBCCK. .

  FIG. 5 illustrates connection correspondence on the circuit board 100 with the data system chip terminal groups 110 and 111 and the address command system chip terminal group 112, the data system package terminal groups 210 and 211, and the address command system package terminal group 212. The As is apparent from the physical arrangement relationship of the terminals in FIGS. 3 and 4, the second data byte system package terminal group (MCUD_SCD) 110B is transferred to the third data byte system package terminal group (MRYD_TRD) 210B. The byte system chip terminal group (MCUD_TRD) 111A is connected to the second data byte system package terminal group (MRYD_SCD) 211A. Such a permutation coupling of data system terminals in byte units has no problem in operation. This is because the byte data and the corresponding data strobe signal are included in the same byte data system terminal group in byte units.

  The data system chip terminal group to be divided and arranged as described above is not particularly limited, but is a 2-byte data system unit as indicated by 110 and 111, and is not a 1-byte data system unit. This is because when the DDR operation is controlled, when the logic of the input / output circuit is partially shared by the data system unit of 2 bytes with respect to the data system unit of the byte unit, This assumes the case where the circuit scale increases when the logic is subdivided. Therefore, theoretically, it is possible to divide and arrange the data system of data bits in which the data strobe signal is shared as a minimum unit.

  According to the said Embodiment 1, the following effects are obtained.

  (1) As shown in FIG. 1, the spatial positional relationship between the package terminal groups 210, 211, and 212 of the data system and the address command system and the chip terminal groups 110, 111, and 112 corresponds, and the corresponding terminals are connected. The wiring path length to be shortened. As shown in FIG. 8 showing a comparative example, the data system chip terminal groups of D0-15 and D16-32 and the AC address command system chip terminal group are arranged in a line, and one side of the microcomputer chip is arranged as a memory control terminal. If it is assigned to the layout of the path and the interface circuit therefor, it becomes difficult to form wiring for memory control in the portions 500 and 501, and wiring other than the memory interface may be difficult in the portions 502 and 503.

  (2) Since the data system chip terminal group in which a plurality of bits are operated in parallel is divided and arranged, it does not obstruct wiring connection to other chip terminals of the microcomputer chip.

  (3) The above contributes to the miniaturization of the wiring board 100.

  (4) The terminal pitch relationship that the terminal pitch of the chip terminal group is smaller than the terminal pitch of the package terminal group further congests the wiring connected to the chip terminals. The advantage is further increased.

  (5) The divided data system chip terminal groups are arranged close to the corner of the microcomputer chip. If the data system chip terminal group is arranged close to the corner of the microcomputer chip, there are many chip terminals on the same side, and the flexibility of wiring to other chip terminals on the same side is increased. Increase.

  (6) Terminals other than the data system chip terminals are disposed between the divided data system chip terminal groups. It is possible to prevent the possibility that the number of data system chip terminal groups that are arranged in parallel becomes too large and the degree of freedom of wiring to other chip terminals existing on the same side is significantly hindered.

  (7) Each of the divided data system chip terminal groups includes a pair of at least a data strobe terminal and a data terminal assigned to data changed in synchronization with the data strobe signal of the data strobe terminal. From the viewpoint of memory control, it becomes easy to ensure the integrity of data and data strobe control for the data when the data system chip terminal group is dividedly arranged. Therefore, even if the data terminal names do not completely match between the respective package terminal groups and chip terminal groups of the data system, it is sufficient if the spatial positional relationship of the terminals in byte units corresponds, and the POP In obtaining the structure, the degree of freedom between the arrangement of the package terminals and the arrangement of the memory control chip terminals of the microcomputer chip can be increased. For the microcomputer chip, it is not necessary to complicate the configuration of the memory controller 130 due to the POP structure.

<< Embodiment 2 >>
FIG. 7 shows a POP structure semiconductor device according to an embodiment of the present invention in a longitudinal section.

  The semiconductor device 2 includes a wiring board 300, a data processing semiconductor chip mounted on the wiring board 300, for example, a microcomputer chip (MCU) 301, and an overlay on the microcomputer chip 301 on the wiring board 300. A package substrate 400 mounted on the package substrate, and a SDRAM (Synchronous Dynamic Random Access Memory) chip (MRY) 401 in the form of a DDR (Double Data Rate), for example, as a memory semiconductor chip built in the package substrate 400.

  The wiring board 300 has a plurality of wiring layers and is made of glass epoxy resin or the like, and a plurality of lands on which the microcomputer chip 301 is mounted and wirings connected to them are formed on the first main surface thereof. On the outside of the microcomputer chip 301, a stack terminal 303 is formed on which the package terminal 402 formed on the package substrate 400 of the SDRAM 401 is mounted and coupled. The package terminal 402 is configured like a BGA (Ball Grid Array) by solder bump electrodes, and the stack terminal 303 is configured by lands. A mounting terminal 302 for mounting the semiconductor device 2 on a mother board (not shown) is formed on the second main surface of the wiring board 300. The mounting terminal 302 is configured in a BGA shape by, for example, solder bump electrodes. Although not particularly limited, the main body of access to the SDRAM chip 401 is the microcomputer chip 301, and the SDRAM interface terminal of the microcomputer chip 301 is connected to the corresponding stack terminal 303 via the wiring of the surface layer wiring layer. The other interface terminals are connected to the corresponding mounting terminals 302 through wiring and vias of a predetermined wiring layer.

  A part of the mounting terminal 302 is allocated for power supply of the power supply voltage and the ground voltage, and these are connected to the power supply and ground terminals of the microcomputer chip 301 through wiring and vias of a predetermined wiring layer. , Connected to the power supply and ground terminals of the SDRAM chip 401. Further, a test land as an external test terminal is exposed at the center of the second main surface of the wiring board 300 and is connected to the stack terminal 103 to be sampled for the test.

  FIG. 6 shows a cross section taken along line BB in FIG.

  The package terminal 402 of the SDRAM chip 401 is a terminal connected to the memory chip terminal of the SDRAM chip 401, and the package substrate 400 is composed of, for example, WPP (Wafer Process Package) or CSP (Chip Size Package). For example, when a DDR2-SDRAM having a parallel data bit number of 64 bits is assumed as an SDRAM chip, the main terminal array of the package terminals 402 is a data system package terminal group 410, 411, 412 and 423 including data terminals and data strobe terminals. And an address command system package terminal group 414 including an address terminal and a command terminal. Although the terminal arrangement of the individual terminal groups of the package terminal group is not shown here, the terminal arrangement of the byte data system in FIG. 3 is basically extended by a plurality of bytes.

  The terminal group of the microcomputer chip 301 corresponding to the data system package terminal groups 410, 411, 412, 423 and the address command system package terminal group 414 of the SDRAM chip 401 is the data system chip terminal group (D15-0) 310, the data system. A chip terminal group (D31-16) 311, a data system chip terminal group (D47-16) 312, a data system chip terminal group (D64-48) 313, and an address command system chip terminal group (Addrcmd) 314 are obtained. These terminal arrangements are not shown here, but basically have a configuration in which the terminal configuration of the byte data system in FIG. 4 is extended by a plurality of bytes. Reference numerals 350 to 354 denote wirings on the wiring board 300 for connecting the package terminal groups 410 to 414 to the chip terminal groups 310 to 314.

  In the microcomputer chip 301, a large number of chip terminals constituted by pad electrodes are arranged on the outermost peripheral edge, an input / output circuit such as an input / output buffer is arranged inside thereof, and a central processing as a program processing circuit is arranged inside thereof. A logic circuit such as a memory controller (DDRCNT) 330 that performs memory control of the device (CPU) 331 and the SDRAM chip 401, analog circuits (ANLG) 332, 333, and the like are arranged. The input / output circuits 320 to 324 correspond to the chip terminal groups 310 to 314. Reference numerals 315 and 316 denote analog chip terminals connected to analog circuits (ANLG) 332 and 333, which are connected to predetermined mounting terminals 302 via wiring on the circuit board 300 (not shown).

  Each of the data system chip terminal groups 310 to 313 is composed of a pair of data byte system chip terminal groups as in the first embodiment, although not particularly shown. As apparent from FIG. 6, each of the data system chip terminal groups 310 to 313 is arranged close to the corner portion of the microcomputer chip 301. If the data system chip terminal group is arranged close to the corner of the microcomputer chip, there are many chip terminals on the same side, and the flexibility of wiring to other chip terminals on the same side is increased. Increase. In particular, the data system chip terminal groups 310 to 313 arranged separately with respect to the analog terminal groups 315 and 316 are arranged at different corner portions of the microcomputer chip 301 or sandwiched between the corner portions of the microcomputer chip 301. Arranged along different sides. As a result, the wiring connected to the analog terminal group can be easily separated from the wiring connected to the data system chip terminal group. For example, in the area indicated by 355, 356, it is easy to pass analog wiring away from memory data wirings 352, 353, 350, etc., which are expected to be changed cyclically and frequently in parallel with a plurality of bits. Become. In addition, the same operational effects as those of the first embodiment can be obtained also in the present embodiment.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory semiconductor chip is not limited to a DDR-SDAM having a DRAM interface or a DDR-SDRAM having a pseudo SRAM interface, and may be another memory such as a flash memory. The semiconductor chip for data processing is not limited to the microcomputer chip, and may be various semiconductor chips having a memory control function for performing data processing by program processing or a dedicated logic circuit. The terminal structure of the circuit board or the package board is not limited to GBA, and other terminal structures can be adopted. The data terminals of the data system chip terminal group are not limited to 8 bits or 16 bits, and may be any number of bits as long as the data strobe signals are shared. The analog terminal may be an appropriate terminal such as an analog input terminal to the AD converter or an interface terminal for analog communication.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 100 Wiring board 101 As a data processing semiconductor chip, for example, a microcomputer chip (MCU)
200 Package substrate 201 Memory semiconductor chip such as SDRAM chip (MRY)
202 Package terminal 103 Stack terminal 103
102 Mounting terminals 210, 211 Data system package terminal group 212 Address command system package terminal group 210A First data byte system package terminal group (MRYD_FST)
210B Third data byte package terminal group (MRYD_TRD)
211A Second data byte system package terminal group (MRYD_SCD)
211B Fourth data byte system package terminal group (MRYD_FRT)
DQ7 to DQ0 (DQ [7: 0]) Byte data DQS0 Data strobe signal DQ23 to DQ16 (DQ [23:16]) Byte data DQS2 Data strobe signal DQ15 to DQ8 (DQ [15: 8]) Byte data DQS1 Data strobe Signals DQ15 to DQ8 (DQ [31:24]) Byte data DQS3 Data strobe signals CA9 to CA0 (CA [9: 0]) Address signal CKE Clock enable signal CSB Chip select signal 110, 111 Data system chip terminal group 112 Address command Chip terminal group 110A first data byte chip terminal group (MCUD_FST)
110B Second data byte system package terminal group (MCUD_SCD)
111A Third data byte system chip terminal group (MCUD_TRD)
111B 4th data byte system package terminal group (MCUD_FRT)
LPBDQ7 to LPBDQ0 (LPBDQ [7: 0]) byte data LPBDQS0 data strobe signal LPBDQ15 to LPBDQ8 (LPBDQ [15: 8]) byte data LPBDQS1 data strobe signal LPBDQ31 to LPBDQ24 (LPBDQ [31: B] data D Signal LPBDQ23 to DQ16 (LPBDQ [23:16]) Byte data LPBDQS2 Data strobe signal LPBCA9 to CA0 (LPBCA [9: 0]) Address signal LPBCKE Clock enable signal LPBCSB Chip select signal 2 Semiconductor device 300 Wiring board 301 Semiconductor for data processing As a chip, for example, a microcomputer chip (MCU)
400 Package substrate 401 SDRAM chip as memory semiconductor chip 402 Package terminal 303 Stack terminal 302 Mounting terminal 410, 411, 412, 423 Data system package terminal group 414 Address command system package terminal group 310, 311, 312, 313 Data system chip terminal Group 314 Address command system chip terminal group 331 Central processing unit (CPU)
330 Memory Controller (DDRCNT)
332,333 Analog circuit (ANLG)
315,316 Analog chip terminal

Claims (14)

A wiring substrate; a data processing semiconductor chip mounted on the wiring substrate; a package substrate mounted on the wiring substrate overlying the data processing semiconductor chip; and a memory provided on the package substrate A semiconductor chip,
The package substrate is connected to the memory semiconductor chip and disposed outside the outer periphery of the data processing semiconductor chip, and includes a data system package terminal group including a data terminal and a data strobe terminal, an address terminal, and a command. An address command system package terminal group including terminals, and the data system package terminal group is divided and arranged in different regions of the package substrate,
The data processing semiconductor chip includes a data system chip terminal group including a data terminal for data control and a data strobe terminal, and an address command system chip terminal group including an address terminal and a command terminal. Corresponding to the arrangement of the data system package terminal group, the data processing semiconductor chip is divided and arranged in different regions on the edge, and the address command system chip terminal group corresponds to the arrangement of the previous address command system package terminal group. A semiconductor device disposed on an edge of the data processing semiconductor chip,
The data system chip terminal group is divided and disposed along a first side of the data processing semiconductor chip and a second side opposite thereto, and the address command system chip terminal group is arranged on the first side and the second side. are placed along the third side of the vertical third side and fourth side,
The data system package terminal group is disposed across two corners of the wiring board corresponding to the first side and the fourth side of the data processing semiconductor chip, and the data processing semiconductor chip. The wiring board is disposed across two corners of the wiring board corresponding to the second side and the fourth side of the chip and straddling the corner, and the address command system package terminal group is the first side of the data processing semiconductor chip. A semiconductor device arranged along one side of the wiring board corresponding to three sides.   The semiconductor device according to claim 1, wherein a terminal pitch of the chip terminal group is smaller than a terminal pitch of the package terminal group.   3. The semiconductor device according to claim 2, wherein terminals other than data system chip terminals are disposed between the divided data system chip terminal groups.   4. Each of the divided data system chip terminal groups includes a pair of at least a data strobe terminal and a data terminal assigned to data changed in synchronization with a data strobe signal of the data strobe terminal. The semiconductor device described.   4. The semiconductor device according to claim 3, wherein the data terminals of each of the divided data system chip terminal groups have a bit number that is an integer multiple of 8 bits. The chip terminal includes an analog terminal group,
Each of the analog terminal group arranged along the same side of the data processing semiconductor chip and the divided data system chip terminal group are arranged separately at different corners of the data processing semiconductor chip, or The semiconductor device according to claim 1, wherein the semiconductor device is disposed along different sides across a corner portion of the data processing semiconductor chip.   The semiconductor device according to claim 1, wherein the package terminal group of the package substrate is a BGA terminal.   The semiconductor device according to claim 1, wherein the memory semiconductor chip is a synchronous DRAM, and the data processing semiconductor chip is a microcomputer. A wiring substrate; a data processing semiconductor chip mounted on the wiring substrate; a package substrate mounted on the wiring substrate overlying the data processing semiconductor chip; and a memory provided on the package substrate A semiconductor chip,
The wiring board has the data processing semiconductor chip mounted on one surface, connected to a predetermined chip terminal of the mounted data processing semiconductor chip, and a stack terminal disposed on the one surface outside the data processing semiconductor chip. Having a mounting terminal connected to a predetermined chip terminal of the data processing semiconductor chip on the other surface,
The package substrate has the memory semiconductor chip mounted thereon, and has an external connection package terminal connected to a memory chip terminal of the mounted memory semiconductor chip, and the external connection package terminal corresponds to the corresponding stack terminal. Joined together,
The package terminal includes a data system package terminal group including a data terminal and a data strobe terminal, and an address command system package terminal group including an address terminal and a command terminal, and the data system package terminal group is a different area of the package substrate. Divided into
The chip terminal includes a data system chip terminal group including a data terminal for data control and a data strobe terminal, and an address command system chip terminal group including an address terminal and a command terminal, and the data system chip terminal group includes the data system The data processing semiconductor chip is divided and arranged in different areas corresponding to the arrangement of the package terminal group, and the address command chip terminal group corresponds to the arrangement of the previous address command package terminal group. A semiconductor device disposed on the edge of the semiconductor chip for
The data system chip terminal group is divided and disposed along a first side of the data processing semiconductor chip and a second side opposite thereto, and the address command system chip terminal group is arranged on the first side and the second side. are placed along the third side of the vertical third side and fourth side,
The data system package terminal group is disposed across two corners of the wiring board corresponding to the first side and the fourth side of the data processing semiconductor chip, and the data processing semiconductor chip. The wiring board is disposed across two corners of the wiring board corresponding to the second side and the fourth side of the chip and straddling the corner, and the address command system package terminal group is the first side of the data processing semiconductor chip. A semiconductor device arranged along one side of the wiring board corresponding to three sides.   The semiconductor device according to claim 9, wherein a terminal pitch of the chip terminal group is smaller than a terminal pitch of the package terminal group.   11. The semiconductor device according to claim 10, wherein terminals other than data system chip terminals are disposed between the divided data system chip terminal groups.   12. Each of the divided data system chip terminal groups includes a pair of at least a data strobe terminal and a data terminal assigned to data changed in synchronization with a data strobe signal of the data strobe terminal. The semiconductor device described.   12. The semiconductor device according to claim 11, wherein the data terminals of each of the divided data system chip terminal groups have a bit number that is an integer multiple of 8 bits. The chip terminal includes an analog terminal group,
Each of the analog terminal group arranged along the same side of the data processing semiconductor chip and the divided data system chip terminal group are arranged separately at different corners of the data processing semiconductor chip, or The semiconductor device according to claim 9, wherein the semiconductor device is disposed along different sides across a corner portion of the data processing semiconductor chip.

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