JP5579982B2 - 半導体装置の中間構造体及び中間構造体の製造方法 - Google Patents
半導体装置の中間構造体及び中間構造体の製造方法 Download PDFInfo
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- JP5579982B2 JP5579982B2 JP2008318699A JP2008318699A JP5579982B2 JP 5579982 B2 JP5579982 B2 JP 5579982B2 JP 2008318699 A JP2008318699 A JP 2008318699A JP 2008318699 A JP2008318699 A JP 2008318699A JP 5579982 B2 JP5579982 B2 JP 5579982B2
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000007789 sealing Methods 0.000 claims description 140
- 239000011347 resin Substances 0.000 claims description 96
- 229920005989 resin Polymers 0.000 claims description 96
- 238000000034 method Methods 0.000 claims description 51
- 238000000465 moulding Methods 0.000 claims description 27
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 description 52
- 239000000047 product Substances 0.000 description 41
- 230000008569 process Effects 0.000 description 40
- 239000000945 filler Substances 0.000 description 18
- 238000009826 distribution Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 10
- 230000007423 decrease Effects 0.000 description 8
- 238000007493 shaping process Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Description
図1〜図7を参照して、本発明の第1の実施形態に係るBGA(Ball Grid Array)型半導体装置の製造方法について説明する。
図8は、本発明の第2の実施の形態に係るBGA型半導体装置の封止工程を示す断面図、図9は第2の実施の形態の封止工程により形成した中間構造体の概略構成を示す平面図及び断面図である。以下、図8及び図9を参照して、第2の実施の形態に係る半導体装置の封止工程について説明する。
図10は、第3の実施の形態に係るBGA型半導体装置の封止工程を示す断面図、図11は第3の実施の形態の封止工程により形成した中間構造体の概略構成を示す平面図及び断面図である。図10及び図11を参照して、第3の実施の形態に係る半導体装置の封止工程について説明する。
図12は、第4の実施の形態の封止工程により形成した中間構造体の概略構成を示す平面図である。
101 製品形成部
102a,102b エリア
103 接続パッド
104 ランド
105 配線
106 枠部
107 位置決め孔
108 ダイシングライン
109 半導体チップ
110 ワイヤ
300 成型装置
301 上型
302 下型
303 キャビティ
304 凹部
305 ゲート
306 タブレット
307 封止樹脂
308 プランジャー
309 ランナー
310 カル
311 段差部
400 中間構造体
Claims (16)
- 配線基板と、
配線基板に搭載された複数の半導体チップと、
複数の半導体チップを一括的に封止し、かつ厚さの異なる部位を有する封止体を有し、
前記封止体は、ゲート側の厚さがエアベント側の厚さより薄くなるように形成されていることを特徴とする半導体装置の中間構造体。 - 前記厚さの異なる部位は、前記配線基板及び前記半導体装置の少なくとも一つの反りを低減するために形成されていることを特徴とする請求項1に記載の中間構造体。
- 前記封止体は、前記ゲート側から前記エアベント側に向かって、段階的に又は連続的に厚さが大きくなるように形成されていることを特徴とする請求項1に記載の中間構造体。
- 前記配線基板は、製品形成エリアと製品形成エリアの外側に設けられた周辺部とを有し、
前記封止体は、前記周辺部の厚さが前記製品形成エリアの厚さより薄くなるように形成されていることを特徴とする請求項1に記載の中間構造体。 - 前記製品形成エリアには、それぞれ一つの前記半導体チップが配置された複数の製品形成部が設けられており、
前記周辺部は、前記配線基板の枠部に設けられていることを特徴とする請求項4に記載の中間構造体。 - 複数の製品形成部を有する配線基板を用意し、
各製品形成部に半導体チップを搭載し、
深さが異なるキャビティを有する成型装置を使用して、キャビティ内に樹脂を注入して複数の半導体チップを一括的に封止し、これにより樹脂厚の異なる部位を有する封止体を形成し、
前記キャビティは、ゲート側の深さがエアベント側の深さより浅く形成されており、
前記キャビティ内に前記樹脂を注入することにより、前記封止体を、前記ゲート側の樹脂厚が前記エアベント側の樹脂厚より薄くなるように形成することを特徴とする半導体装置の中間構造体の製造方法。 - 前記樹脂厚の異なる部位は、前記配線基板及び前記半導体装置の少なくとも一つの反りを低減するために形成されていることを特徴とする請求項6に記載の中間構造体の製造方法。
- 前記キャビティは、前記ゲート側の深さが前記エアベント側の深さより段階的又は連続的に浅く形成されており、
前記封止体は、前記ゲート側から前記エアベント側に向かって、段階的に又は連続的に樹脂厚が大きくなるように形成されていることを特徴とする請求項6に記載の中間構造体の製造方法。 - 前記製品形成部の外側には周辺部が形成されており、
前記キャビティは、前記周辺部の深さが前記製品形成部の深さより浅く形成されており、
前記キャビティ内に前記樹脂を注入することにより、前記封止体を、前記周辺部の樹脂厚が前記製品形成部の樹脂厚より薄くなるように形成することを特徴とする請求項6又は7に記載の中間構造体の製造方法。 - 前記封止体は、前記キャビティの両端部の近傍部位を含めて略等間隔で配置された複数のゲートから前記樹脂を注入することにより形成されることを特徴とする請求項6及至9のいずれか1項に記載の中間構造体の製造方法。
- 請求項6及至10のいずれか1項に記載の製造方法により得られた前記中間構造体をダイシングすることにより、複数の半導体装置を得ることを特徴とする半導体装置の製造方法。
- 請求項6及至10のいずれか1項に記載の製造方法で使用された深さが異なる前記キャビティを有する成型装置。
- 配線基板と、
配線基板に搭載された複数の半導体チップと、
複数の半導体チップを一括的に封止し、かつ厚さの異なる部位を有する封止体を有し、
前記封止体は、略長方形状に構成されており、短辺側の周辺部位の厚さが長辺側の周辺部位の厚さより薄く形成されていることを特徴とする半導体装置の中間構造体。 - 配線基板と、
配線基板に搭載された複数の半導体チップと、
複数の半導体チップを一括的に封止し、かつ厚さの異なる部位を有する封止体を有し、
前記封止体は、略長方形状に構成されており、短辺側の周辺部位の厚さの薄い領域が、長辺側の厚さの薄い領域より広く形成されていることを特徴とする半導体装置の中間構造体。 - 複数の製品形成部を有する配線基板を用意し、
各製品形成部に半導体チップを搭載し、
深さが異なるキャビティを有する成型装置を使用して、キャビティ内に樹脂を注入して複数の半導体チップを一括的に封止し、これにより樹脂厚の異なる部位を有する封止体を形成し、
前記封止体は略長方形状に形成され、短辺側の周辺部位の樹脂厚が長辺側の周辺部位の樹脂厚より薄く形成されていることを特徴とする半導体装置の中間構造体の製造方法。 - 複数の製品形成部を有する配線基板を用意し、
各製品形成部に半導体チップを搭載し、
深さが異なるキャビティを有する成型装置を使用して、キャビティ内に樹脂を注入して複数の半導体チップを一括的に封止し、これにより樹脂厚の異なる部位を有する封止体を形成し、
前記封止体は、略長方形状に形成され、短辺側の周辺部位の樹脂厚の薄い領域が、長辺側の樹脂厚の薄い領域より広く形成されていることを特徴とする半導体装置の中間構造体の製造方法。
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