JP5579435B2 - Nitride-based semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor device and a method for manufacturing the same, and more particularly to a nitride semiconductor device having a quantum well structure and supplying a source gas to form a p-type semiconductor layer and a method for manufacturing the same.

A nitride-based semiconductor device made of a group III nitride-based semiconductor is used for a light emitting diode (LED). Examples of group III nitride semiconductors include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). A typical group III nitride semiconductor is represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

  A nitride semiconductor device using a group III nitride semiconductor includes, for example, an n-type group III nitride semiconductor layer (n-type semiconductor layer), an active layer (light emitting layer), and a p-type group III on a substrate. It has a structure in which nitride-based semiconductor layers (p-type semiconductor layers) are stacked in this order. Then, light generated by recombination of holes supplied from the p-type semiconductor layer and electrons supplied from the n-type semiconductor layer in the active layer is output to the outside (see, for example, Patent Document 1). .

  As the active layer, a multi-quantum well (MQW) structure in which a plurality of well layers (well layers) are sandwiched between barrier layers (barrier layers) having a larger band gap than the well layers can be employed. (For example, refer to Patent Document 2).

In addition, examples in which the p-type semiconductor layer is formed in a two-layer structure or a three-layer structure for the purpose of reducing the forward voltage (Vf) and improving the light emission efficiency are also disclosed (for example, Patent Document 3 and Patent). Reference 4).
Japanese Patent Laid-Open No. 10-284802 JP 2004-55719 A Japanese Patent No. 3250438 Japanese Patent No. 331466

  When the p-type semiconductor layer is formed in a multilayer structure, it is necessary to grow at a low temperature in order to reduce thermal damage to the active layer, and at the same time, it is necessary to reduce the forward voltage (Vf) and improve the luminous efficiency. .

Conventionally, in forming a p-type semiconductor layer doped with a p-type dopant, a carrier gas containing hydrogen (H ₂ ) and nitrogen (N ₂ ) has been used to supply a source gas. However, when the p-type semiconductor layer is formed with a carrier gas containing hydrogen, the p-type dopant is hardly activated by hydrogen atoms taken together with the p-type dopant, and the p-type semiconductor layer is prevented from being made p-type. Cause. Therefore, after forming the p-type semiconductor layer, it is necessary to perform annealing for removing hydrogen atoms from the p-type semiconductor layer, resulting in an increase in the manufacturing process.

  In view of the above-described problems, the present invention provides a nitride-based semiconductor that forms a p-type semiconductor layer at a low temperature to reduce thermal damage to the active layer, lower the forward voltage (Vf), and improve luminous efficiency. Providing equipment.

  The present invention provides a method for manufacturing a nitride-based semiconductor device that does not require an annealing step of removing hydrogen atoms from a p-type semiconductor layer.

According to one aspect of the present invention for achieving the above object, an active layer comprising a multiple quantum well containing indium, a first nitride-based semiconductor layer disposed on the active layer and containing a p-type impurity, A second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the first nitride-based semiconductor layer; and the second nitride-based semiconductor layer A third element is disposed on the semiconductor layer and includes a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer and a lower concentration than the p-type impurity of the first nitride-based semiconductor layer. A nitride-based semiconductor layer; and a fourth nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer; wherein the p-type of the first nitride semiconductor layer to fourth nitride semiconductor layer not Things, the nitride-based semiconductor device is Mg is provided.

According to another aspect of the present invention, a step of forming an n-type semiconductor layer, a step of forming an active layer on the n-type semiconductor layer, a first layer disposed on the active layer and including a p-type impurity. A nitride-based semiconductor layer, and a second nitride-based semiconductor layer that is disposed on the first nitride-based semiconductor layer and includes a p-type impurity at a concentration lower than that of the p-type impurity of the first nitride-based semiconductor layer; , Disposed on the second nitride semiconductor layer, having a higher concentration than the p-type impurity of the second nitride semiconductor layer and a lower concentration than the p-type impurity of the first nitride semiconductor layer. a third nitride-based semiconductor layer including a p-type impurity; and a third nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer and including a p-type impurity having a lower concentration than the p-type impurity of the third nitride-based semiconductor layer. Forming a p-type semiconductor layer by laminating a 4-nitride-based semiconductor layer, and a hydrogen-free key. The raw material gas was supplied by Riagasu, at least a portion is formed, said first nitride of the first to third nitride semiconductor layer of the first nitride semiconductor layer to fourth nitride semiconductor layer There is provided a method for manufacturing a nitride-based semiconductor device , wherein the p-type impurity of the material-based semiconductor layer to the fourth nitride-based semiconductor layer is Mg .

  According to the nitride semiconductor device of the present invention, a p-type semiconductor layer can be formed at a low temperature to reduce thermal damage to the active layer, to reduce the forward voltage Vf, and to improve luminous efficiency.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the nitride type semiconductor device which does not require the annealing process which removes a hydrogen atom from a p-type semiconductor layer can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional structure diagram of a nitride-based semiconductor device according to a first embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a nitride-based semiconductor device portion, and (b) an enlargement of an active layer portion. The typical cross-section figure made. 1A is a schematic cross-sectional structure diagram of a nitride-based semiconductor device according to a modification of the first embodiment of the present invention, and FIG. 1A is a schematic cross-sectional structure diagram of a nitride-based semiconductor device portion, and FIG. FIG. 2 is an enlarged schematic cross-sectional structure diagram. 1 is a schematic cross-sectional structure diagram formed up to a p-side electrode and an n-side electrode of a nitride-based semiconductor device according to a first embodiment of the present invention. The figure which shows the relationship between the light emission output and the number of quantum well pairs in the nitride-type semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 3 is a schematic diagram of a band structure for explaining a light emission phenomenon in the MQW layer in the nitride semiconductor device according to the first embodiment of the present invention. In the nitride semiconductor device according to the first embodiment of the present invention, a band structure for explaining a light emission phenomenon in the MQW layer, (a) a schematic diagram of a band structure in the case where the MQW layer has 5 pairs, (B) Schematic diagram of band structure when MQW layer is 8 pairs, (c) Schematic diagram of band structure when MQW layer is 12 pairs. (A) The figure which shows temperature distribution at the time of forming the p-type semiconductor layer (41-44) of a 4 layer structure in the nitride type semiconductor device which concerns on the 1st Embodiment of this invention, (b) Hydrogen gas The figure explaining the conditions of a flow, (c) The figure explaining another condition of hydrogen gas flow, (d) The figure explaining another condition of hydrogen gas flow, (e) The further another condition of hydrogen gas flow FIG. (A) The temperature distribution at the time of forming the p-type semiconductor layer (41-44) of a four-layer structure in the nitride-type semiconductor device which concerns on the 1st Embodiment of this invention, (b) Nitrogen gas The figure explaining the conditions of a flow, (c) The figure explaining the conditions of ammonia gas flow. The schematic diagram which shows the example of the nitride type semiconductor device manufactured by the manufacturing method of the nitride type semiconductor device which concerns on the 2nd Embodiment of this invention. The schematic diagram which shows the structural example of the active layer of the nitride semiconductor device manufactured by the manufacturing method of the nitride semiconductor device which concerns on the 2nd Embodiment of this invention. The figure which shows the gas flow pattern in the crystal growth of the active layer shown in FIG. It is a figure for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on the 2nd Embodiment of this invention, (a) The figure which shows the temperature profile at the time of p-type semiconductor layer formation, (b) p-type semiconductor The table | surface which shows the growth conditions of a layer. The IV characteristic view which shows the electric current which flows into a n side electrode from a p side electrode when a voltage is applied between a p side electrode and a n side electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... N-type semiconductor layer 3 ... Active layer 4 ... P-type semiconductor layer 5 ... Oxide electrode 6 ... Buffer layer 7 ... Block layer 31 ... Barrier layer (GaN layer)
32 ... Well layer (InGaN layer)
41 ... first nitride semiconductor layer 42 ... second nitride semiconductor layer 43 ... third nitride semiconductor layer 44 ... fourth nitride semiconductor layer 100 ... p-side electrode 200 ... n-side electrode 310 ... final barrier Layers 311-31n ... Barrier layers 321-32n ... Well layers

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the embodiment of the present invention. In the embodiment of the present invention, the arrangement of each component is described below. It is not something specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
A schematic cross-sectional structure of the nitride-based semiconductor device according to the first embodiment of the present invention is represented as shown in FIG. 1A, and an enlarged schematic cross-sectional structure of the active layer portion is shown in FIG. It is expressed as shown in (b).

  As shown in FIG. 1, the nitride semiconductor device according to the first embodiment includes a substrate 1, a buffer layer 6 disposed on the substrate 1, a buffer layer 6, and an n-type impurity. An n-type semiconductor layer 2 doped with impurities, a block layer 7 disposed on the n-type semiconductor layer 2 and doped with n-type impurities at a lower concentration than the n-type semiconductor layer 2, and disposed on the block layer 7. An active layer 3, a p-type semiconductor layer 4 disposed on the active layer 3, and an oxide electrode 5 disposed on the p-type semiconductor layer 4.

  As shown in FIG. 1B, the active layer 3 has a laminated structure in which barrier layers 311 to 31n and 310 and well layers 321 to 32n having a smaller band gap than the barrier layers 311 to 31n and 310 are alternately arranged. Have. Hereinafter, the first barrier layer 311 to the nth barrier layer 31n included in the active layer 3 are collectively referred to as “barrier layer 31”. Further, all well layers included in the active layer 3 are collectively referred to as “well layers 32”.

  The film thickness of the final barrier layer 310 in the uppermost layer of the stacked structure is larger than the thicknesses of the other barrier layers (the first barrier layer 311 to the nth barrier layer 31n) included in the stacked structure other than the final barrier layer 310. It may be formed.

  In the nitride-based semiconductor device shown in FIG. 1, the concentration of the p-type dopant in the final barrier layer 310 is from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 in the film thickness direction of the final barrier layer 310. There is no p-type dopant in the second main surface that gradually decreases along the first main surface.

  As the substrate 1, for example, a c-plane (0001), 0.25 ° off sapphire substrate can be employed. The n-type semiconductor layer 2, the active layer 3, and the p-type semiconductor layer 4 are each made of a group III nitride semiconductor, and the buffer layer 6, the n-type semiconductor layer 2, the block layer 7, the active layer 3, and the p-type are formed on the substrate 1. Semiconductor layers 4 are sequentially stacked.

(Buffer layer)
The buffer layer 6 is formed of, for example, an AlN layer having a thickness of about 10 to 50 angstroms. When the AlN buffer layer 6 is crystal-grown, for example, it is grown at a high temperature in a temperature range of about 900 ° C. to 950 ° C. By supplying trimethylaluminum (TMA) used as an Al raw material for the AlN buffer layer 6 and ammonia (NH ₃ ) used as an N raw material to the reaction chamber alternately using H ₂ gas as a carrier, an AlN buffer is obtained. Layer 6 is crystal grown. For example, the number of cycles may be about 3-5.

By supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber alternately with H ₂ gas as a carrier, a thin AlN buffer layer 6 having a thickness of about 10 to 50 Å is formed. It can be grown at high speed, and can be formed while maintaining good crystallinity.

  According to the nitride semiconductor device according to the first embodiment, the crystallinity and surface morphology of the group III nitride semiconductor formed on the high-temperature AlN buffer layer can be improved.

(Block layer)
The block layer 7 disposed between the n-type semiconductor layer 2 and the active layer 3 is a group III nitride semiconductor having a thickness of about 50 nm doped with Si as an n-type impurity at a ^{concentration of} less than 1 × 10 ¹⁷ cm ^−3. For example, a GaN layer can be employed.

In the nitride-based semiconductor device shown in FIG. 1, for example, when Si is doped with about 3 × 10 ¹⁸ cm ^{−3 in the} n-type semiconductor layer 2, Si is doped with about 8 × 10 ¹⁶ cm ^−3. By disposing the block layer 7 between the n-type semiconductor layer 2 and the active layer 3, the diffusion of Si from the n-type semiconductor layer 2 to the active layer 3 in the formation process of the active layer 3 and the manufacturing process after that process is performed. Can be prevented.

  That is, Si does not diffuse into the active layer 3 and a reduction in the luminance of light generated in the active layer 3 is prevented. Furthermore, when a bias is applied between the n-type semiconductor layer 2 and the p-type semiconductor layer 4 to cause the active layer 3 to emit light, electrons supplied from the n-type semiconductor layer 2 to the active layer 3 cause the active layer 3 to Overflow that passes through and reaches the p-type semiconductor layer 4 can be prevented, and a decrease in luminance of light output from the nitride-based semiconductor device can be prevented.

The Si concentration of the block layer 7 is less than 1 × 10 ¹⁷ cm ⁻³ . This is because, when the Si concentration of the block layer 7 is too high, electrons supplied from the n-type semiconductor layer 2 overflow the active layer 3 to the p-type semiconductor layer 4, and the holes in the p-type semiconductor layer 4 This is because recombination occurs, the recombination rate in the active layer 3 decreases, and the luminance of light generated in the active layer 3 decreases. On the other hand, when the Si concentration of the block layer 7 is too low, the carrier density of electrons injected from the type semiconductor layer 2 into the active layer 3 cannot be increased. Therefore, the Si concentration of the block layer 7 is preferably about 5 × 10 ¹⁶ to less than 1 × 10 ¹⁷ cm ⁻³ .

  As described above, in the nitride-based semiconductor device according to the first embodiment, the block layer 7 is arranged between the n-type semiconductor layer 2 and the active layer 3, so that the n-type semiconductor in the manufacturing process is arranged. The diffusion of Si from the layer 2 to the active layer 3 and the overflow of electrons from the n-type semiconductor layer 2 to the p-type semiconductor layer 4 during light emission can be prevented, and the light output from the nitride-based semiconductor device can be prevented. Decrease in luminance can be prevented. As a result, deterioration of the quality of the nitride semiconductor device shown in FIG. 1 can be prevented.

(N-type semiconductor layer)
The n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies holes to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3.

  The n-type semiconductor layer 2 may be a group III nitride semiconductor having a thickness of about 1 to 6 μm doped with an n-type impurity such as silicon (Si), for example, a GaN layer.

(P-type semiconductor layer)
As the p-type semiconductor layer 4, a group III nitride semiconductor having a thickness of about 0.05 to 1 μm doped with a p-type impurity, such as a GaN layer, can be employed. As the p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

  A configuration example of the p-type semiconductor layer 4 is as follows in more detail. That is, as shown in FIG. 1A, the p-type semiconductor layer 4 is disposed on the active layer 3, and includes a first nitride-based semiconductor layer 41 containing a p-type impurity, and a first nitride-based semiconductor layer. 41, a second nitride-based semiconductor layer 42 containing a p-type impurity at a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 41, and a second nitride-based semiconductor layer 42. , A third nitride-based semiconductor layer 43 containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42, and the third nitride-based semiconductor layer 43 disposed on the third nitride-based semiconductor layer 43. And a fourth nitride semiconductor layer 44 containing a p-type impurity having a lower concentration than the p-type impurity of the system semiconductor layer 43.

  The thickness of the second nitride-based semiconductor layer 42 is formed to be greater than the thickness of the first nitride-based semiconductor layer 41 or the third nitride-based semiconductor layer 43 to the fourth nitride-based semiconductor layer 44.

Here, the material and thickness of each layer will be specifically described. The first nitride-based semiconductor layer 41 including p-type impurities disposed on the active layer 3 is, for example, a p-type GaN layer of about 2 × 10 ²⁰ cm ⁻³ doped with Mg and having a thickness of about 50 nm. Formed with.

The second nitride semiconductor layer 42 disposed on the first nitride semiconductor layer 41 and containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride semiconductor layer 41 is doped with, for example, Mg. The p-type GaN layer is about 4 × 10 ¹⁹ cm ⁻³ and about 100 nm thick.

The third nitride-based semiconductor layer 43 disposed on the second nitride-based semiconductor layer 42 and containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42 is doped with, for example, Mg. The p-type GaN layer is about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick.

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the nitride-based semiconductor device according to the first embodiment of the present invention, the p-type semiconductor layer 4 formed on the active layer 3 made of a multiple quantum well containing indium has an Mg concentration as described above. It consists of p-type GaN layers with different four-layer structures, and is doped at the above concentrations. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 3.

  The first nitride semiconductor layer 41 closest to the active layer 3 has a higher emission intensity as the Mg concentration is higher. Therefore, the higher the Mg concentration, the better.

The second nitride-based semiconductor layer 42 has a Mg concentration of about 10 ¹⁹ cm ⁻³ because the crystal defects due to Mg increase and the resistance of the film increases when Mg is excessively doped. It is desirable.

  Since the third nitride semiconductor layer 43 is a layer that determines the amount of holes injected into the active layer 3, it is desirable that the Mg concentration be slightly higher than that of the second nitride semiconductor layer 42.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the oxide electrode 5 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al as the oxide electrode 5 is used, the forward voltage Vf of the nitride-based semiconductor device is most reduced. Mg is added to the fourth nitride-based semiconductor layer 44 so that the Mg concentration becomes the same.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Further, the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42 close to the active layer 3 do not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 3 is made of N ₂ carrier gas. The crystal is grown by the extension of the growth. When these p-type GaN layers are grown, a film having a lower resistance can be grown by increasing the V / III ratio as much as possible, and the forward voltage (Vf) of the light emitting element can be lowered.

  According to the nitride-based semiconductor device according to the first embodiment, the p-type semiconductor layer is formed at a low temperature to reduce thermal damage to the active layer, and to reduce the forward voltage (Vf). Can be improved.

(Active layer)
As shown in FIG. 1B, the active layer 3 includes a first well layer 321 to an nth well layer 32n sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, respectively. It is a quantum well (MQW) structure (n: natural number). That is, the active layer 3 has a quantum well structure in which the well layer 32 is sandwiched between the barrier layers 31 having a larger band gap than the well layer 32 in a unit pair structure, and this unit pair structure is stacked n times. Have

  Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer 313. The The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 3 is disposed on the n-type semiconductor layer 2 via the buffer layer 6, and the p-type semiconductor layer 4 (41 to 44) is disposed on the final barrier layer 310 of the active layer 3. Is done.

The well layers 321 to 32n are formed by, for example, In _x Ga _1-x N (0 <x <1) layers, and the barrier layers 311 to 31n and 310 are formed by, for example, GaN layers. The number of pairs of the multiple quantum well layers is, for example, 6 to 11. The ratio of indium (In) to gallium (Ga) in the well layers 321 to 32n {x / (1-x)} is appropriately set according to the wavelength of light to be generated.

  Further, the thickness of the well layers 321 to 32n is, for example, about 2 to 3 nm, preferably about 2.8 nm, and the thickness of the barrier layers 311 to 31n is about 7 to 18 nm, preferably about It is about 16.5 nm.

  In the nitride-based semiconductor device according to the first embodiment, the relationship between the light emission output and the number of quantum well pairs is expressed as shown in FIG.

  In the nitride semiconductor device according to the first embodiment, the band structure for explaining the light emission phenomenon in the active layer 3 is schematically represented as shown in FIG.

  FIG. 6 shows a band structure for explaining a light emission phenomenon in the active layer 3 in the nitride semiconductor device according to the first embodiment. FIG. 6A shows a band when MQW is 5 pairs. FIG. 6B is a schematic diagram of the structure, FIG. 6B is a schematic diagram of the band structure when the MQW is 8 pairs, and FIG. 6C is a schematic diagram of the band structure when the MQW is 12 pairs.

  In the conventional structure, since 4 to 5 MQW pairs are used, as shown in FIG. 6A, electrons supplied from the n-type semiconductor layer 2 jump over the active layer 3 and become p-type. It flows to the semiconductor layer 4. At this time, holes supplied from the p-type semiconductor layer 4 are recombined with electrons before reaching the active layer 3, and the hole concentration reaching the active layer 3 decreases. Thereby, the brightness | luminance of LED will reduce. This is because the effective mass of holes is higher than that of electrons, so the mobility of injected holes from the p-type semiconductor layer 4 is low, and electrons reach the p-type semiconductor layer 4 before the holes reach the active layer 3. This is because they recombine with holes.

  On the other hand, when the number of MQW pairs is larger than 12 pairs, as shown in FIG. 6C, the active layer 3 is thick, so that the electrons supplied from the n-type semiconductor layer 2 are within the active layer 3. Can not drive enough. At this time, the holes supplied from the p-type semiconductor layer 4 cannot sufficiently travel in the active layer 3. For this reason, electrons and holes are not sufficiently recombined in the active layer 3, thereby reducing the luminance of the LED.

  On the other hand, when the number of MQW pairs is about 8 pairs, the thickness of the active layer 3 is optimized and supplied from the n-type semiconductor layer 2 as shown in FIGS. The electrons that are generated travel sufficiently in the active layer 3, and at the same time, the holes supplied from the p-type semiconductor layer 4 can also travel sufficiently in the active layer 3. And hole recombination occur sufficiently, thereby increasing the brightness of the LED.

  In a case where a sufficient injection amount of holes from the p-type semiconductor layer 4 to the active layer 3 is secured and a sufficient injection amount of electrons from the n-type semiconductor layer 2 to the active layer 3 is secured. The MQW in the active layer 3 contributing to the light emission phenomenon may be 2 to 3 pairs counted from the p-type semiconductor layer 4. Since the electron mobility is higher than the hole mobility, the MQW in the active layer 3 contributing to the light emission phenomenon is several pairs close to the p-type semiconductor layer 4 side.

As shown in FIG. 4, when the number of MQW pairs is 8, the light emission output P shows the maximum value P ₂ , while when the number of MQW pairs is 5 or 12, the light emission output P is P ₁ (P ₁ <P _{When the} number of MQW pairs is smaller than 5 or larger than 12, it is difficult to secure a sufficient light output P.

  In the nitride semiconductor device according to the first embodiment, the electrons supplied from the n-type semiconductor layer 2 and the holes supplied from the p-type semiconductor layer 4 are efficiently recombined in the active layer 3. The number of MQW pairs in the active layer 3 can be optimized.

(Final barrier layer)
The final barrier layer 310 is formed thicker than the Mg diffusion distance from the p-type semiconductor layer 4 to the active layer 3.

  In the nitride semiconductor device shown in FIG. 1, the concentration of the p-type impurity in the final barrier layer 310 is from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 in the film thickness direction of the final barrier layer 310. There is no p-type impurity in the second main surface that gradually decreases along the first main surface and faces the first main surface.

  The film thickness d0 of the final barrier layer 310 of the nitride-based semiconductor device shown in FIG. 1 is such that the p-type impurity diffused from the p-type semiconductor layer 4 to the active layer 3 after the formation process of the p-type semiconductor layer 4 and after that process. The active layer 3 is set so as not to reach the well layer 32. That is, the p-type impurity diffused from the p-type semiconductor layer 4 to the final barrier layer 310 is a second main surface (the final barrier layer 310 is a well) facing the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4. The film thickness d0 is set to a thickness that does not reach the layer 32n).

The Mg concentration on the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is, for example, about 2 × 10 ²⁰ cm ⁻³ , and the second concentration of the final barrier layer 310 facing the first main surface is about 2 × 10 ²⁰ cm ⁻³ . The Mg concentration gradually decreases toward the main surface, and the Mg concentration does not have an influence of about 10 ¹⁶ cm ⁻³ or less at a distance of about 7 to 8 nm from the first main surface, and is below the lower limit of detection in the analysis. . That is, by setting the film thickness d0 of the final barrier layer 310 to about 10 nm, Mg does not diffuse to the second main surface of the final barrier layer 310, and therefore, the second barrier layer 310 in contact with the active layer 3 has a second thickness. There is no Mg on the main surface. That is, Mg does not diffuse into the n-th well layer 32n, and a reduction in the luminance of light generated in the active layer 3 is prevented.

  The film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n may be the same. However, the thicknesses d1 to dn are such that holes injected from the n-type semiconductor layer 2 into the active layer 3 reach the nth well layer 32n, and light emission due to recombination of electrons and holes occurs in the nth well layer 32n. It is necessary to set a thickness that can be generated. This is because if the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are too thick, the movement of holes in the active layer 3 is hindered and the light emission efficiency is lowered.

  For example, the film thickness d0 of the final barrier layer 310 is about 26.5 nm, the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are about 7 to 18 nm, and the first well layer 321. The film thickness of the nth well layer 32n is about 2 to 3 nm.

  As described above, in the nitride semiconductor device according to the first embodiment, the film thickness d0 of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is diffused from the p-type semiconductor layer 4 to the active layer 3. The thickness of the p-type dopant that does not reach the well layer 32 of the active layer 3 is set. That is, according to the nitride semiconductor device shown in FIG. 1, by setting the film thickness d0 of the final barrier layer 310 to be thicker than the Mg diffusion distance, the increase in the film thickness of the entire active layer 3 is suppressed, The diffusion of p-type impurities from the p-type semiconductor layer 4 to the well layer 32 of the active layer 3 can be prevented. As a result, it is possible to manufacture a nitride-based semiconductor device in which deterioration of the quality of the nitride-based semiconductor device is suppressed without lowering the luminance of light due to the diffusion of p-type impurities into the well layer 32.

(Electrode structure)
As shown in FIG. 3, the nitride semiconductor device according to the first embodiment includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 2 and a p-side that applies a voltage to the p-type semiconductor layer 4. An electrode 100 is further provided. As shown in FIG. 3, the p-type semiconductor layer 4, the active layer 3, the block layer 7, and a partial region of the n-type semiconductor layer 2 are exposed on the n-type semiconductor layer 2 by mesa etching. An electrode 200 is disposed.

  The p-side electrode 100 is disposed on the p-type semiconductor layer 4 via the oxide electrode 5. Alternatively, the p-side electrode 100 may be disposed directly on the p-type semiconductor layer 4. The transparent electrode made of the oxide electrode 5 disposed on the fourth nitride semiconductor layer 44 includes, for example, any of ZnO, ITO, or ZnO containing indium.

  The n-side electrode 200 is, for example, an aluminum (Al) film, a multilayer film of Ti / Ni / Au or Al / Ti / Au, Al / Ni / Au, Al / Ti / Ni / Au, or Au—Sn / Ti from the upper layer. The p-side electrode 100 is made of, for example, an Al film, a palladium (Pd) -gold (Au) alloy film, a Ni / Ti / Au multilayer film, or an Au—Sn / It consists of a multilayer film of Ti / Au. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 2, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 4 via the oxide electrode 5.

  In order to mount the nitride semiconductor device according to the first embodiment of the present invention in a flip-chip structure, the height of the surface of the p-side electrode 100 and the surface of the n-side electrode 200 measured from the substrate 1 is the same. You may form so that it may become height.

A transparent conductive film ZnO may be formed as the oxide electrode 5 and the ZnO may be covered with a reflective laminated film that reflects the wavelength λ of the emitted light. The reflective laminated film has a laminated structure of λ / 4n ₁ and λ / 4n ₂ (n ₁ and n ₂ are refractive indexes of the laminated layers). As a material used for the laminated structure, for example, λ = 450 nm for blue light On the other hand, a laminated structure composed of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) can be used. In this case, the thickness of each layer is set such that ZrO ₂ is about 53 nm and SiO ₂ is about 77 nm, for example. As another material for forming the laminated structure, TiO ₂ , Al ₂ O ₃ or the like can be used.

  According to the nitride semiconductor device according to the first embodiment, the light emitted in the active layer 3 by the reflective laminated film can be extracted outside without being absorbed by the n-side electrode 100. Luminous efficiency can be improved.

(Production method)
An example of the method for manufacturing the nitride semiconductor device according to the first embodiment shown in FIG. 1 will be described below. The nitride semiconductor device manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other manufacturing methods including this modification. Here, an example in which a sapphire substrate is applied to the substrate 1 will be described.

(A) First, an AlN buffer layer 6 is grown on the sapphire substrate 1 by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, at a high temperature of about 900 ° C. to 950 ° C., trimethylaluminum (TMA) and ammonia (NH ₃ ) are supplied to the reaction chamber alternately and pulsed by using H ₂ gas as a carrier. A thin AlN buffer layer 6 of about 10 to 50 angstroms is grown in a short time.

(B) Next, a GaN layer to be the n-type semiconductor layer 2 is grown on the AlN buffer layer 6 by MOCVD or the like. For example, after the substrate 1 on which the AlN buffer layer 6 is formed is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 2 doped with n-type impurities on the AlN buffer layer 6 is set to 1 Grow about ~ 5 μm. For the n-type semiconductor layer 2, for example, a GaN film doped with Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ can be employed. When Si is added as an impurity, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form the n-type semiconductor layer 2.

(C) Next, as the block layer 7 on the n-type semiconductor layer 2, for example, a GaN film doped with Si at a concentration of less than 1 × 10 ¹⁷ cm ⁻³ , for example, about 8 × 10 ¹⁶ cm ⁻³ , Grow about 200 nm. At this time, the same source gas as in the case where the n-type semiconductor layer 2 is formed can be applied.

(D) Next, the active layer 3 is formed on the n-type semiconductor layer 2. For example, the active layer 3 is formed by alternately laminating barrier layers 31 made of GaN films and well layers 32 made of InGaN films. Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 are grown alternately and continuously, and the barrier layers 31 and the well layers 32 are stacked. Thus formed active layer 3 is formed. That is, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a stacked structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

  For example, the barrier layer 31 is formed at the substrate temperature Ta, and the well layer 32 is formed at the substrate temperature Tb (Ta> Tb). That is, the first barrier layer 311 is formed at times t10 to t11 when the substrate temperature is set to Ta. Next, the substrate temperature is set to Tb at time t11, and the first well layer 321 is formed at time t11 to time t20. Similarly, the second barrier layer 312 is formed at the substrate temperature Ta from time t20 to t21, and the second well layer 322 is formed at the substrate temperature Tb from time t21 to time t30. Then, the nth barrier layer 31n is formed at the substrate temperature Ta at the time tn0 to tn1, the nth well layer 32n is formed at the substrate temperature Tb at the time tn1 to the time te, and the barrier layers 31 and the well layers 32 are alternately stacked. The laminated structure completed is completed.

In the case of forming the barrier layer 31, as source gases, for example, TMG gas is supplied to a film forming processing apparatus at a flow rate of 300 sccm (standard cc / min) and NH ₃ gas at a flow rate of 20 slm (standard L / min). On the other hand, when forming the well layer 32, as source gases, for example, TMG gas is supplied to the processing apparatus at a flow rate of 300 sccm, trimethylindium (TMI) gas is 280 sccm, and NH ₃ gas is supplied at a flow rate of 20 slm. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

  An active layer 3 shown in FIG. 1 is formed by forming a non-doped GaN film of about 10 nm as the final barrier layer 310 on the formed laminated structure. As already described, the film thickness d0 of the final barrier layer 310 is set to a thickness at which the p-type dopant diffused from the p-type semiconductor layer 4 to the active layer 3 does not reach the well layer 32 of the active layer 3.

(E) Next, the substrate temperature is set to about 800 ° C. to 900 ° C., and the p-type semiconductor layer 4 doped with p-type impurities is formed on the final barrier layer 310 to about 0.05 to 1 μm.

The p-type semiconductor layer 4 is formed, for example, in a four-layer structure in which Mg is added as a p-type impurity. The first nitride-based semiconductor layer 41 disposed on the active layer 3 is formed of a p-type GaN layer having a thickness of approximately 2 × 10 ²⁰ cm ⁻³ and a thickness of approximately 50 nm, and the second nitride-based semiconductor layer 42 is formed. Is formed of a p-type GaN layer having a thickness of about 4 × 10 ¹⁹ cm ⁻³ and a thickness of about 100 nm. The third nitride semiconductor layer 43 has a thickness of about 1 × 10 ²⁰ cm ⁻³ and a thickness of about 40 nm, for example. The fourth nitride semiconductor layer 44 is formed of a p-type GaN layer having a thickness of about 8 × 10 ¹⁹ cm ⁻³ and a thickness of about 10 nm.

In the case where Mg is added as an impurity, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ 2Mg) gas are supplied as source gases to form the p-type semiconductor layer 4 (41 to 44). Mg is diffused from the p-type semiconductor layer 4 (41 to 44) to the active layer 3 during the formation of the p-type semiconductor layer 4 (41 to 44), but the Mg is diffused into the well layer 32 of the active layer 3 by the final barrier layer 310. It is prevented from spreading.

  Here, the process of forming the p-type semiconductor layer 4 will be described in more detail.

  In the nitride semiconductor device according to the first embodiment, the temperature distribution when forming the p-type semiconductor layers (41 to 44) having the four-layer structure is expressed as shown in FIG. Moreover, the figure explaining the conditions of hydrogen gas flow is represented as shown in FIG.7 (b). Moreover, the figure explaining another condition of hydrogen gas flow is represented as shown in FIG.7 (c). Moreover, the figure explaining another condition of hydrogen gas flow is represented as shown in FIG.7 (d). Moreover, the figure explaining another condition of a hydrogen gas flow is represented as shown in FIG.7 (e).

  In the nitride semiconductor device according to the first embodiment of the present invention, the temperature distribution when forming the p-type semiconductor layers (41 to 44) having the four-layer structure is expressed as shown in FIG. Is done. Moreover, the figure explaining the conditions of nitrogen gas flow is represented as shown in FIG.8 (b). Moreover, the figure explaining the conditions of ammonia gas flow is represented as shown in FIG.8 (c).

  In the temperature distribution shown in FIGS. 7A and 8A, a period T1 from time t1 to t2 is a period in which the first nitride-based semiconductor layer 41 is formed, and a period T2 from time t2 to t3 is This is a period for forming the second nitride semiconductor layer 42, a period T3 from time t3 to t4 is a period for forming the third nitride semiconductor layer 43, and a period T4 from time t4 to t5 is the fourth period. This is a period in which the nitride-based semiconductor layer 44 is formed. A period T5 between times t5 and t6 is a period during which the substrate temperature is cooled from 850 ° C. to 350 ° C.

  In the method for manufacturing a nitride-based semiconductor device according to the first embodiment of the present invention, the step of forming n-type semiconductor layer 2, the step of forming active layer 3 on n-type semiconductor layer 2, and the activity Forming a nitride-based semiconductor layer (41-44) at a low temperature of about 800 ° C. to 900 ° C. by stacking a plurality of p-type GaN layers each containing a p-type impurity on the layer 3; A source gas is supplied by a carrier gas not containing any of the plurality of p-type GaN layers to form at least a part.

  When the p-type semiconductor layer 4 is formed with a carrier gas containing hydrogen, the Mg atoms are hardly activated by the hydrogen atoms taken together with the Mg, and the p-type semiconductor layer 4 is prevented from being made p-type. Therefore, after forming the p-type semiconductor layer 4, it is necessary to perform annealing (hereinafter referred to as “p-type annealing”) for removing the hydrogen atoms and making the p-type semiconductor layer 4 p-type.

  However, according to the method for manufacturing the nitride semiconductor device according to the first embodiment, at least one of the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 does not contain hydrogen. The step of p-type annealing can be omitted by forming the source gas of Mg by gas. Which part of the p-type semiconductor layer 4 is formed by a carrier gas not containing hydrogen can be arbitrarily set. For example, the first nitride semiconductor layer 41 to the third nitride semiconductor layer 43 do not contain hydrogen. It may be formed by a carrier gas, and only the fourth nitride semiconductor layer 44 may be formed by a carrier gas containing hydrogen.

  For example, as shown in FIG. 7B, among the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44, the second nitride semiconductor layer 42 having a large film thickness or a high Mg concentration. Forming the first nitride-based semiconductor layer 41 with a carrier gas not containing hydrogen is preferable in that the step of p-type annealing is omitted. For example, FIG. 7C shows that the first nitride-based semiconductor layer 41 to the third nitride-based semiconductor layer 43 among the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 are replaced with hydrogen. It is an example formed by a carrier gas not included. FIG. 7D shows an example in which the first nitride-based semiconductor layer 41 and the third nitride-based semiconductor layer 43 are formed using a carrier gas that does not contain hydrogen. FIG. 7E shows an example in which the second nitride-based semiconductor layer 42 and the third nitride-based semiconductor layer 43 are formed using a carrier gas that does not contain hydrogen.

  On the other hand, as shown in FIGS. 7B to 7E, the fourth nitride semiconductor layer 44 in contact with the p-side electrode 100 is formed of Mg by a carrier gas containing hydrogen in order to improve the crystal state as much as possible. It is preferable to form by supplying the raw material gas. In general, when the source gas of Mg is supplied by a carrier gas containing hydrogen, the crystal state of the p-type semiconductor layer doped with Mg is higher than when the source gas of Mg is formed by a carrier gas not containing hydrogen. Because it is good.

  The p-type film forming method in the method for manufacturing a nitride semiconductor device according to the first embodiment will be described below. Note that the p-type film forming method described below is an example, and it is needless to say that it can be realized by various other methods including this modification. Here, Mg is employed as the p-type impurity, and as shown in FIG. 7B, the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed by a carrier gas not containing hydrogen, A case where the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 are formed using a carrier gas containing hydrogen will be described as an example.

  As shown in FIGS. 7 to 8, the substrate temperature Tp for forming the p-type semiconductor layer 4 is set to 850 ° C. and the pressure is set to 200 Torr.

In (step 1) Time t1~ time t2 supply, by supplying N ₂ gas as a carrier gas, NH ₃ gas as a raw material gas, TMG gas, each processor biscyclopentadienyl magnesium (Cp ₂ Mg) gas Thus, the first nitride semiconductor layer 41 is formed. The first nitride-based semiconductor layer 41 having a film thickness = 50 nm and an Mg concentration = 2 × 10 ²⁰ cm ⁻³ is formed with a time interval between time t1 and time t2.

(Step 2) From time t2 to time t3, N ₂ gas is supplied as a carrier gas, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively, and the second nitride semiconductor Layer 42 is formed. The second nitride-based semiconductor layer 42 having a film thickness = 100 nm and an Mg concentration = 4 × 10 ¹⁹ cm ⁻³ is formed with a time interval between time t2 and time t3 being 21 minutes.

(Step 3) From time t3 to time t4, H ₂ gas and N ₂ gas are supplied as carrier gases, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively. A nitride-based semiconductor layer 43 is formed. The third nitride-based semiconductor layer 43 having a film thickness = 40 nm and an Mg concentration = 1 × 10 ²⁰ cm ⁻³ is formed with a time period from time t3 to time t4 being 1 minute.

(Step 4) From time t4 to time t5, H ₂ gas and N ₂ gas are supplied as carrier gases, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively. A nitride-based semiconductor layer 44 is formed. The fourth nitride semiconductor layer 44 having a film thickness = 10 nm and an Mg concentration = 8 × 10 ¹⁹ cm ⁻³ is formed with a time interval between time t4 and time t5 being 3 minutes.

(Step 5) At time t5 to time t6, the substrate temperature is lowered from the temperature Tp (850 ° C.) to the temperature Td (350 ° C.) or lower while supplying N ₂ gas as the carrier gas. That is, p-type annealing performed at 400 ° C. or higher is not performed.

The p-type semiconductor layer 4 including the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is formed by the steps 1 to 5 described above. Since the first nitride-based semiconductor layer 41 with a high Mg concentration and the second nitride-based semiconductor layer 42 with a large film thickness are formed by a carrier gas not containing H ₂ gas, p-type annealing is not performed. A p-type semiconductor layer 4 is obtained as a p-type semiconductor. In addition, the fourth nitride semiconductor layer 44 is improved in crystal state by being formed by supplying a carrier gas containing H ₂ gas. That is, the crystal state of the surface in contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good, and the contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good.

According to the formation process of the p-type semiconductor layer 4 as described above, the carrier gas containing no H ₂ gas is supplied to form the p-type semiconductor layer 4, thereby bringing the p-type semiconductor layer 4 together with the p-type impurities. H ₂ is not taken into Therefore, p-type annealing for removing H ₂ from the p-type semiconductor layer 4 becomes unnecessary, and the manufacturing process of the nitride-based semiconductor device can be shortened.

(F) Next, the oxide electrode 5 is formed on the p-type semiconductor layer 4 by vapor deposition, sputtering technique or the like. As the oxide electrode 5, for example, any one of ZnO, ITO, or ZnO containing indium can be used. Further, an n-type impurity such as Ga or Al may be added at a high concentration up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(G) Next, after patterning the oxide electrode 5, a reflective laminated film 8 that reflects the wavelength λ of the emitted light is formed so as to cover the oxide electrode 5 by vapor deposition, sputtering technique, or the like. As the material used for the reflective laminated film 8, for example, a laminated structure made of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) is used for blue light with λ = 450 nm. The thickness of each layer is, for example, about 53 nm for ZrO ₂ and about 77 nm for SiO ₂ .

(H) Next, the reflective laminated film 8 and the middle of the p-type semiconductor layer 4 to the n-type semiconductor layer 2 are removed by mesa etching using an etching technique such as reactive ion etching (RIE). Then, the surface of the n-type semiconductor layer 2 is exposed.

(I) Next, n-side electrodes 200 and 300 are formed on the exposed surface of the n-type semiconductor layer 2 by vapor deposition, sputtering technique, or the like. Also on the oxide electrode 5 on the p-type semiconductor layer 4, the p-side electrode 100 is formed by vapor deposition, sputtering technique or the like after pattern formation, and the nitride semiconductor device shown in FIG. 3 is completed.

(Modification)
A schematic cross-sectional structure of a nitride-based semiconductor device according to a modification of the first embodiment is represented as shown in FIG. 2A, and an enlarged schematic cross-sectional structure of the active layer portion is shown in FIG. It is expressed as shown in (b).

  As shown in FIG. 2, the nitride semiconductor device according to the modification of the first embodiment is disposed on the substrate 1, the buffer layer 6 disposed on the substrate 1, the buffer layer 6, and n An n-type semiconductor layer 2 doped with a type impurity, a block layer 7 disposed on the n-type semiconductor layer 2 and doped with an n-type impurity at a lower concentration than the n-type semiconductor layer 2, and on the block layer 7 An active layer 3 disposed on the active layer 3, a p-type semiconductor layer 4 disposed on the active layer 3, and an oxide electrode 5 disposed on the p-type semiconductor layer 4.

  The nitride-based semiconductor device according to the modification of the first embodiment includes a third nitride-based semiconductor layer 43 that includes a p-type impurity disposed on the active layer 3, and a third nitride-based semiconductor layer. A fourth nitride-based semiconductor layer containing a p-type impurity at a concentration lower than that of the third nitride-based semiconductor layer, and a fourth nitride-based semiconductor layer, and the oxide electrode 5 And a transparent electrode.

In addition, the transparent electrode includes any one of ZnO doped with impurities up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al, ITO, or ZnO containing indium.

  In the nitride semiconductor device according to the modification of the first embodiment, the p-type semiconductor layer 4 is directly disposed on the active layer 3 due to the structure of the nitride semiconductor device according to the first embodiment. A third nitride-based semiconductor layer, and a fourth nitride-based semiconductor disposed on the third nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer It is formed in a two-layer structure consisting of layers.

The third nitride-based semiconductor layer 43 disposed directly on the active layer 3 is formed of, for example, a p-type GaN layer of about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick doped with Mg. .

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the nitride semiconductor device according to the second embodiment, the p-type semiconductor layer 4 formed on the active layer 3 made of a multiple quantum well containing indium is composed of two layers having different Mg concentrations as described above. It consists of a p-type GaN layer with a structure and is doped at the above concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 3.

  Since the third nitride semiconductor layer 43 closest to the active layer 3 is a layer that determines the amount of holes injected into the active layer 3, the higher the Mg concentration, the higher the emission intensity. For this reason, the higher the Mg concentration, the better.

  The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the oxide electrode 5 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 19 to 5 × 10 21 cm −3 of Ga or Al is used as the oxide electrode 5, the Mg concentration when the forward voltage Vf of the nitride semiconductor device is lowered most Thus, Mg is added to the fourth nitride semiconductor layer 44 as an impurity.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Alternatively, the third nitride-based semiconductor layer 43 close to the active layer 3 does not need to increase the amount of H ₂ gas in the carrier gas, and is crystallized as an extension of the active layer 3 grown with N ₂ carrier gas. It may be grown.

  Also in the nitride-based semiconductor device according to the modification of the first embodiment, the AlN buffer layer 6, the n-type semiconductor layer 2, the block layer 7, the active layer 3, the p-type semiconductor layer 4, the final barrier layer 310, and the reflective stacked layer Since the film 8 and the electrode structure are the same as those of the nitride-based semiconductor device according to the first embodiment, description thereof is omitted.

  According to the nitride-based semiconductor device according to the first embodiment and the modification thereof, the p-type semiconductor layer is formed at a low temperature to reduce thermal damage to the active layer, and to reduce the forward voltage Vf. Luminous efficiency can be improved.

[Second Embodiment]
The method for manufacturing a nitride semiconductor device according to the second embodiment of the present invention includes a step of forming an n-type semiconductor layer, a step of forming an active layer on the n-type semiconductor layer, forming a p-type semiconductor layer by laminating a plurality of nitride-based semiconductor layers each containing a p-type dopant, and supplying a source gas with a carrier gas not containing hydrogen, thereby providing a plurality of nitride-based semiconductor layers At least a part of.

  An example of a nitride-based semiconductor device manufactured by the above manufacturing method is shown in FIG. The nitride semiconductor device shown in FIG. 9 includes a substrate 1, an n-type semiconductor layer 2 disposed on the substrate 1, an active layer 3 disposed on the n-type semiconductor layer 2, and an active layer 3. A nitride semiconductor device including the p-type semiconductor layer 4 formed. As shown in FIG. 9, the p-type semiconductor layer 4 includes a first nitride-based semiconductor layer 41 to a fourth nitride-based semiconductor layer 44. Details of the structure of the p-type semiconductor layer 4 will be described later.

  The nitride-based semiconductor device shown in FIG. 9 further includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 2 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 4. The n-side electrode 200 is disposed on the surface of the n-type semiconductor layer 2 in which partial regions of the p-type semiconductor layer 4, the active layer 3, and the n-type semiconductor layer 2 are exposed by mesa etching. The p-side electrode 100 is disposed on the p-type semiconductor layer 4. The n-side electrode 200 is made of, for example, an aluminum (Al) film, and the p-side electrode 100 is made of, for example, a titanium (Ti) film, a nickel (Ni) film, an indium tin oxide (ITO) film, or a zinc oxide (ZnO) film. Or the like, or a palladium (Pd) -gold (Au) alloy film. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 2, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 4.

  In the nitride semiconductor device shown in FIG. 9, the n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies holes to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3.

  As the substrate 1, for example, a sapphire substrate or the like can be employed. As the n-type semiconductor layer 2, a group III nitride semiconductor having a thickness of about 0.2 to 5 μm doped with silicon (Si) as an n-type dopant, for example, a GaN layer or the like can be used.

  The active layer 3 has a quantum well structure in which the well layer 32 is sandwiched between barrier layers 31 having a larger band gap than the well layer 32. The active layer 3 may have a quantum well structure in which a well layer is sandwiched between barrier layers as a unit structure, and may have a multiple quantum well (MQW) structure in which this unit structure is stacked n times (n: natural number). In the case of the MQW structure, the active layer 3 includes, for example, a first well layer 321 to an nth well layer sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, as shown in FIG. 32n. Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer (not shown) is the second barrier layer 312 and the third barrier layer (not shown). ). The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 3 is disposed on the n-type semiconductor layer 2, and the first nitride-based semiconductor layer 41 of the p-type semiconductor layer 4 is disposed on the final barrier layer 310 of the active layer 3.

  The barrier layer 31 is made of, for example, a GaN film, and the well layer 32 is made of, for example, an indium gallium nitride (InGaN) film. Note that the ratio of indium (In) to gallium (Ga) in the well layer 32 is appropriately set according to the wavelength of light to be generated. As the barrier layer 31, an InGaN film having a smaller In composition than the well layer 32 may be employed.

  The p-type semiconductor layer 4 may be a group III nitride semiconductor doped with a p-type dopant, such as a GaN layer. As the p-type dopant, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used. Hereinafter, a case where Mg is doped as a p-type dopant will be described as an example.

The p-type semiconductor layer 4 shown in FIG. 9 includes a first nitride-based semiconductor layer 41, a second nitride-based semiconductor layer 42, a third nitride-based semiconductor layer 43, and a fourth nitride-based semiconductor layer 44 in this order. It has a laminated structure. Examples of the film thickness and Mg concentration of the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 when Mg is doped as a p-type dopant are shown below:
(1) First nitride semiconductor layer 41: film thickness = 50 nm, Mg concentration = 2 × 10 ²⁰ cm ⁻³
(2) Second nitride semiconductor layer 42: film thickness = 100 nm, Mg concentration = 4 × 10 ¹⁹ cm ⁻³
(3) Third nitride semiconductor layer 43: film thickness = 40 nm, Mg concentration = 1 × 10 ²⁰ cm ⁻³
(4) Fourth nitride semiconductor layer 44: film thickness = 10 nm, Mg concentration = 8 × 10 ¹⁹ cm ⁻³
As already described, when the p-type semiconductor layer 4 is formed by a carrier gas containing hydrogen, the hydrogen atoms taken together with Mg are difficult to activate, and the p-type semiconductor layer is prevented from becoming p-type. Cause. Therefore, after forming the p-type semiconductor layer 4, it is necessary to perform p-type annealing for removing the hydrogen atoms and making the p-type semiconductor layer 4 p-type.

  However, according to the method of manufacturing the nitride semiconductor device according to the second embodiment, at least one of the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 does not contain hydrogen. The step of p-type annealing can be omitted by forming the source gas of Mg by gas. For example, the second nitride-based semiconductor layer 42 having a large thickness among the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 or the first nitride-based semiconductor layer 41 having a high Mg concentration may be replaced with hydrogen. It is preferable to use a carrier gas that does not contain any p-type annealing step.

  On the other hand, the fourth nitride semiconductor layer 44 in contact with the p-side electrode 100 is preferably formed by supplying an Mg source gas with a carrier gas containing hydrogen in order to improve the crystal state as much as possible. This is because, in general, when the Mg source gas is supplied by a carrier gas containing hydrogen, the crystal state of the nitride-based semiconductor layer doped with Mg is larger than when the carrier gas does not contain hydrogen. Because it is good.

  Hereinafter, a method for manufacturing a nitride-based semiconductor device according to the second embodiment will be described using the case of manufacturing the nitride-based semiconductor device shown in FIG. 9 as an example. The nitride semiconductor device manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other manufacturing methods including this modification. Here, Mg is adopted as the p-type dopant, the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42 are formed by a carrier gas not containing hydrogen, and the third nitride semiconductor layer 43 and the second nitride semiconductor layer 43 are formed. An example in which the 4-nitride semiconductor layer 44 is formed using a carrier gas containing hydrogen will be described.

As a manufacturing method, GaN is grown on a substrate 1 such as a sapphire substrate by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, after the substrate 1 is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 2 on the substrate 1 is doped with, for example, Si at a concentration of about 3 × 10 ¹⁸ cm ^−3. The film is grown about 1 to 5 μm. At this time, trimethylgallium (TMG), ammonia (NH ₃ ) and silane (SH ₄ ) are supplied as source gases to form the n-type semiconductor layer 2.

  Next, for example, barrier layers 31 made of a GaN film and well layers 32 made of an InGaN film are alternately stacked to form an active layer 3 on the n-type semiconductor layer 2. Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 having a larger band gap than the well layers 32 are grown alternately and continuously. The active layer 3 formed by laminating the layer 31 and the well layer 32 is formed. When the active layer 3 has an MQW structure, the step of laminating the barrier layer 31 and the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, an MQW structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

  FIG. 11 shows an example in which the barrier layer 31 and the well layer 32 are stacked. The barrier layer 31 is formed at the substrate temperature Ta shown in FIG. 11, and the well layer 32 is formed at the substrate temperature Tb. That is, the first barrier layer 311 is formed at times t10 to t11 when the substrate temperature is set to Ta. Next, the substrate temperature is lowered until the substrate temperature Tb is reached at times t11 to t12. From time t12 to time t13, the first well layer 321 is formed at the substrate temperature Tb. Thereafter, the substrate temperature is increased until the substrate temperature Ta is reached at times t13 to t20, and the second barrier layer 312 is formed at times t20 to t21. Similarly, the barrier layers 31 and the well layers 32 are alternately formed at the substrate temperature Ta and the substrate temperature Tb, respectively. Then, the nth barrier layer 31n is formed at time tn0 to tn1, the substrate temperature is lowered until the substrate temperature Tb is reached at time tn1 to tn2, and the nth well layer 32n is formed at time tn2 to time tn3. Then, the substrate temperature is raised until the substrate temperature Ta is reached at times tn3 to te0, and the final barrier layer 310 is formed at times te0 to te1 to complete the active layer 3. When the substrate temperature is raised or lowered, the barrier layer 31 or the well layer 32 can be grown or the growth can be interrupted.

In the case of forming the barrier layer 31, as source gases, for example, TMG gas is supplied to a film forming processing apparatus at a flow rate of 300 sccm (standard cc / min) and NH ₃ gas at a flow rate of 20 slm (standard L / min). On the other hand, when forming the well layer 32, as source gases, for example, TMG gas is supplied to the processing apparatus at a flow rate of 300 sccm, trimethylindium (TMI) gas is 280 sccm, and NH ₃ gas is supplied at a flow rate of 20 slm. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

  Next, a p-type semiconductor layer 4 doped with Mg as a p-type dopant is formed on the active layer 3. FIG. 12A and FIG. 12B show examples of conditions for stacking the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 as the p-type semiconductor layer 4. 12A shows a temperature profile when the p-type semiconductor layer 4 is formed, and FIG. 12B shows the growth conditions of the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44. As shown in FIGS. 12A and 12B, the substrate temperature Tp for forming the p-type semiconductor layer 4 is commonly set to 800 to 900 ° C. and the pressure is set to 100 to 300 Torr. 12A and 12B, the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed by a carrier gas not containing hydrogen, and the first nitride-based semiconductor layer 42 is formed by a carrier gas containing hydrogen. The case where the 3 nitride system semiconductor layer 43 and the 4th nitride system semiconductor layer 44 are formed is illustrated.

(Step 1) From time t0 to time t1, N ₂ gas is supplied as a carrier gas at a flow rate of ₂ to 10 slm, and NH ₃ gas, TMG gas, and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are used as source gases. Are respectively supplied to the processing apparatus, and the first nitride-based semiconductor layer 41 is formed. The first nitride-based semiconductor layer 41 having a film thickness = 50 nm and an Mg concentration = 2 × 10 ²⁰ cm ⁻³ is formed with a time interval from time t0 to time t1 being 5 minutes.

(Step 2) From time t1 to time t2, N ₂ gas is supplied as a carrier gas at a flow rate of ₂ to 10 slm, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied to the processing apparatus as source gases, respectively. A second nitride-based semiconductor layer 42 is formed. The second nitride-based semiconductor layer 42 with a film thickness = 100 nm and an Mg concentration = 4 × 10 ¹⁹ cm ⁻³ is formed with the time t1 to time t2 being 21 minutes.

(Step 3) From time t2 to time t3, H ₂ gas is supplied as a carrier gas at a flow rate of 10 to 20 slm and N ₂ gas is supplied at a flow rate of ₂ to 10 slm, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases. Are supplied to the processing apparatus, and the third nitride-based semiconductor layer 43 is formed. The third nitride semiconductor layer 43 having a film thickness = 40 nm and an Mg concentration = 1 × 10 ²⁰ cm ⁻³ is formed with the time period from time t2 to time t3 being 1 minute.

In (Step 4) Time t3~ time t4, 10～20Slm of H2 gas as a carrier gas, by supplying N2 gas at a flow rate of 2~10slm, NH ₃ gas as a raw material gas, TMG gas, Cp ₂ Mg gas, respectively The fourth nitride-based semiconductor layer (p-type layer) 44 is formed by supplying the processing apparatus. The fourth nitride semiconductor layer 44 with a film thickness = 10 nm and an Mg concentration = 8 × 10 ¹⁹ cm ⁻³ is formed with the time period from time t3 to time t4 being 3 minutes.

(Step 5) From time t4 to time t5, the substrate temperature is lowered from the temperature Tp (850 ° C.) to the temperature Td (350 ° C.) or lower, for example, room temperature while supplying N ₂ gas as a carrier gas at a flow rate of 20 slm. . That is, p-type annealing performed at 400 ° C. or higher is not performed.

The p-type semiconductor layer 4 including the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is formed by the steps 1 to 5 described above. Since the first nitride-based semiconductor layer 41 having a high Mg concentration and the second nitride-based semiconductor layer 42 having a large film thickness are formed using a carrier gas that does not contain H ₂ , the p-type annealing is not performed. A p-type semiconductor layer 4 is obtained as a p-type semiconductor. In addition, the fourth nitride semiconductor layer 44 is improved in crystal state by being formed by supplying a carrier gas containing H ₂ . That is, the crystal state of the surface in contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good, and the contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good.

  Next, part of the p-type semiconductor layer 4 to the n-type semiconductor layer 2 is removed by mesa etching by reactive ion etching or the like, and the surface of the n-type semiconductor layer 2 is exposed. After that, the n-side electrode 200 is formed by vapor deposition on the exposed surface of the n-type semiconductor layer 2, and the p-side electrode 100 is formed by vapor deposition on the p-type semiconductor layer 4, so that the nitride-based semiconductor device shown in FIG. Is completed.

FIG. 13 shows a current If that flows from the p-side electrode 100 to the n-side electrode 200 when the voltage Vf is applied between the p-side electrode 100 and the n-side electrode 200. In FIG. 13, a characteristic A is an If-Vf characteristic when the p-type semiconductor layer 4 is formed by the above-described steps 1 to 5 and p-type annealing is not performed, and a characteristic B is a carrier gas containing H _2. If-Vf characteristics are shown when p-type semiconductor layer 4 is formed by supplying and p-type annealing is performed. From FIG. 13, it can be seen that even when p-type annealing is not performed, a forward voltage equal to or lower than that when p-type annealing is performed can be obtained.

According to the nitride-based semiconductor device and the manufacturing method thereof according to the second embodiment as described above, the p-type semiconductor layer 4 is formed by supplying the carrier gas not containing H ₂ to form the p-type semiconductor. Layer 4 does not incorporate H ₂ with the p-type dopant. Therefore, p-type annealing for removing H ₂ from the p-type semiconductor layer 4 becomes unnecessary, and the manufacturing process of the nitride-based semiconductor device can be shortened.

[Other embodiments]
As described above, the present invention has been described with reference to the first to second embodiments. However, the discussion and the drawings that form a part of this disclosure are exemplary and limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the embodiment already described, the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed using a carrier gas not containing hydrogen, and the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 43 are formed. The case where the nitride-based semiconductor layer 44 is formed using a carrier gas containing hydrogen has been described. However, it is possible to arbitrarily set which part of the p-type semiconductor layer 4 is formed by the carrier gas not containing hydrogen. For example, the first nitride-based semiconductor layer 41 to the third nitride-based semiconductor layer 43 may be made of hydrogen. It may be formed with a carrier gas that does not contain, and only the fourth nitride semiconductor layer 44 may be formed with a carrier gas containing hydrogen.

  As described above, the present invention includes various embodiments not described herein.

  The nitride semiconductor device of the present invention can be used for all nitride semiconductor devices such as LED elements and LD elements having a quantum well structure.

Claims (12)

An active layer composed of multiple quantum wells containing indium;
A first nitride-based semiconductor layer disposed on the active layer and including a p-type impurity;
A second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the first nitride-based semiconductor layer;
P disposed on the second nitride-based semiconductor layer, having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer and a lower concentration than the p-type impurity of the first nitride-based semiconductor layer. A third nitride-based semiconductor layer containing a type impurity;
A fourth nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer and containing a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer;
The nitride semiconductor device, wherein the p-type impurity of the first nitride semiconductor layer to the fourth nitride semiconductor layer is Mg.   The thickness of the second nitride-based semiconductor layer is formed to be thicker than the thickness of the first nitride-based semiconductor layer or the third to fourth nitride-based semiconductor layers. 2. The nitride semiconductor device according to 1.   The nitride-based semiconductor device according to claim 1, further comprising a transparent electrode disposed on the fourth nitride-based semiconductor layer and made of an oxide electrode.   The nitride-based semiconductor device according to claim 3, wherein the transparent electrode includes any one of ZnO, ITO, or ZnO containing indium. The transparent electrode includes any one of ZnO, ITO, or ZnO containing Ga doped with impurities with an impurity concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^−3. 4. The nitride semiconductor device according to 3.   The nitride according to any one of claims 1 to 5, wherein each of the first to fourth nitride-based semiconductor layers is formed of GaN by low-temperature growth at 800 ° C to 900 ° C. Semiconductor device.   forming an n-type semiconductor layer;
  Forming an active layer on the n-type semiconductor layer;
  A first nitride-based semiconductor layer including a p-type impurity disposed on the active layer, and disposed on the first nitride-based semiconductor layer, and lower than the p-type impurity of the first nitride-based semiconductor layer. A second nitride-based semiconductor layer containing a p-type impurity at a concentration; and a second nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer, having a higher concentration than the p-type impurity in the second nitride-based semiconductor layer; A third nitride-based semiconductor layer containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer; and the third nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer Forming a p-type semiconductor layer by stacking a fourth nitride-based semiconductor layer containing a p-type impurity at a lower concentration than the p-type impurity;
  At least a part of the first to third nitride-based semiconductor layers of the first to fourth nitride-based semiconductor layers by supplying a source gas with a carrier gas that does not include hydrogen. Form the
  The method of manufacturing a nitride semiconductor device, wherein the p-type impurity in the first nitride semiconductor layer to the fourth nitride semiconductor layer is Mg. The nitriding according to claim 7, wherein the source gas is supplied by a carrier gas containing hydrogen to form another part of the first to fourth nitride semiconductor layers. Method for manufacturing a physical semiconductor device. A step of forming a p-side electrode on the p-type semiconductor layer, wherein the nitride-based semiconductor layer in contact with the p-side electrode among the first nitride-based semiconductor layer to the fourth nitride-based semiconductor layer; 9. The method of manufacturing a nitride semiconductor device according to claim 8, wherein the source gas is supplied by a carrier gas containing hydrogen. 10. The nitride-based semiconductor device according to claim 7, wherein the active layer is formed by alternately laminating barrier layers and well layers having a band gap smaller than that of the barrier layers. Production method. The method for manufacturing a nitride semiconductor device according to claim 7, wherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are formed of a group III nitride semiconductor. . The method for manufacturing a nitride semiconductor device according to claim 7, wherein the p-type dopant is magnesium.

Images