JP5576546B2 - Wiring board manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board suitable for mounting, for example, a semiconductor element by flip chip connection.

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is a semiconductor element, there is a so-called area array type semiconductor integrated circuit element in which a large number of electrode terminals are arranged in a lattice pattern over substantially the entire main surface.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, a method of connecting by flip chip connection is employed. The flip chip connection means that the upper surface of the semiconductor element connection pad provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element, and the exposed upper surface of the semiconductor element connection pad and the semiconductor integrated circuit element are exposed. This electrode terminal is opposed to each other and electrically connected via conductive bumps made of solder, gold, or the like.

  FIG. 19 is a schematic cross-sectional view showing an example of a conventional wiring board on which area array type semiconductor integrated circuit elements as semiconductor elements are mounted by flip-chip connection.

  As shown in FIG. 19, the conventional wiring board 110 has a core for the inside and the surface of an insulating base 103 in which a plurality of build-up insulating layers 102 are laminated on the upper and lower surfaces of the core insulating plate 101. A wiring conductor 104 and a build-up wiring conductor 105 are deposited, and a protective solder resist layer 106 is deposited on the outermost surface thereof. In addition, a semiconductor element mounting portion 103A on which the semiconductor integrated circuit element E is mounted is provided at the center of the upper surface of the insulating base 103.

  A plurality of through holes 107 are formed from the upper surface to the lower surface of the core insulating plate 101, and the core wiring conductor 104 is attached to the inner surface of the through hole 107. Further, the through hole 107 is filled with a hole filling resin 108, and the core wiring conductor 104 is also attached to the upper and lower surfaces of the insulating plate 101 including the hole filling resin 108. A part of the core wiring conductor 104 forms a land pattern 104 </ b> A for covering the through hole 107 and connecting to the build-up wiring conductor 105.

  In addition, a plurality of via holes 109 are formed in each of the build-up insulating layers 102, and build-up wiring conductors 105 are deposited on the surface of each insulating layer 102 and the inner surfaces of the via holes 109. ing. The build-up wiring conductor 105 is connected to the land pattern 104 </ b> A in the core wiring conductor 104 through the via hole 109. Further, a part of the build-up wiring conductor 105 deposited on the outermost insulating layer 102 on the upper surface side of the wiring substrate 110 is an electrode terminal of the semiconductor integrated circuit element E in the semiconductor element mounting portion 103A. Circular semiconductor element connection pads 105A that are electrically connected to T by flip-chip connection via conductive bumps B1 are formed, and a plurality of these semiconductor element connection pads 105A are formed in a lattice pattern. . These semiconductor element connection pads 105A are covered with the solder resist layer 106 at the outer periphery thereof, and the central part of the upper surface is exposed from the solder resist layer 106. The electrode terminal T of the circuit element E is electrically connected through a conductive bump B1 made of solder, gold or the like.

  On the other hand, a part deposited on the outermost insulating layer 102 on the lower surface side of the wiring board 110 is a circular external connection pad 105B that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 105B are formed side by side in a grid pattern. The external connection pad 105B is covered with a solder resist layer 106 at the outer periphery thereof, and the center portion of the lower surface is exposed from the solder resist layer 106. An external electric circuit (not shown) is exposed on the exposed portion of the external connection pad 105B. The wiring conductor of the board is electrically connected via the solder ball B2. The solder resist layer 106 protects the outermost wiring conductor 105 and defines exposed portions of the semiconductor element connection pads 105A and the external connection pads 105B.

  A method for manufacturing such a conventional wiring board 110 will be described with reference to FIGS. First, as shown in FIG. 20A, a double-sided copper-clad plate 112 in which a copper foil 111 is laminated on the upper and lower surfaces of an insulating plate 101 made of an electrically insulating material such as glass-epoxy resin is prepared. The thickness of the insulating plate 101 is, for example, about 50 to 800 μm, and the thickness of the copper foil 111 is, for example, about 2 to 18 μm.

  Next, as shown in FIG. 20B, a through hole 107 is formed by drilling or laser processing from the upper surface to the lower surface of the double-sided copper-clad plate 112. The diameter of the through hole 107 is about 50 to 300 μm.

  Next, as shown in FIG. 21 (c), the first electroless copper plating layer 113a and the first electrolytic copper plating layer 113b are sequentially deposited over the entire inner wall of the through hole 107 and the entire surface of the copper foil 111. A first conductor layer 113 is formed. The thickness of the first electroless copper plating layer 113a is about 0.1 to 1.0 μm, and the thickness of the first electrolytic copper plating layer 113b is about 5 to 30 μm.

  Next, as shown in FIG. 21D, a hole filling resin 108 is filled into the through hole 107 to which the first conductor layer 113 is deposited.

  Next, as shown in FIG. 22 (e), the upper and lower ends of the hole-filling resin 108 and the surface of the first conductor layer 113 are polished so that the copper foil 111 layer remains on the upper and lower surfaces of the insulating plate 101. And flatten. At this time, the thickness of the copper foil 111 remaining on the insulating plate 101 is about 2 to 8 μm.

  Next, as shown in FIG. 22 (f), the second electroless copper plating layer 114 a is formed over the entire surface of the remaining copper foil 111, the end surface of the first conductor layer 113, and the end surface of the hole-filling resin 108. And the 2nd conductor layer 114 formed by depositing the 2nd electrolytic copper plating layer 114b in order is formed. The thickness of the second electroless copper plating layer 114a is about 0.1 to 1.0 μm, and the thickness of the second electrolytic copper plating layer 114b is about 10 to 30 μm.

  Next, as shown in FIG. 23G, an etching resist layer 115 having a predetermined pattern including a mask pattern for land formation covering the through hole 107 in the second conductor layer 114 and the region corresponding to the periphery thereof is formed. It is deposited on the surface of the second conductor layer 114.

  Next, as shown in FIG. 23H, the second conductor layer 114 exposed from the etching resist layer 115 and the underlying copper foil 111 layer are removed by etching. As a result, the wiring conductor 104 having a shape corresponding to the etching resist layer 115 is formed.

  Next, as shown in FIG. 24I, the etching resist layer 115 is peeled off from the second conductor layer 114. As a result, the core insulating plate 101 having the core wiring conductor 104 having a predetermined pattern including the land pattern 104A covering the through hole 107 is formed.

  Next, as shown in FIG. 25J, build-up insulating layers 102 are laminated on the upper and lower surfaces of the core insulating plate 101 on which the wiring conductors 104 are formed. The insulating layer 102 is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm.

  Next, as shown in FIG. 25 (k), a via hole 109 having the core wiring conductor 104 as a bottom surface is formed by laser processing the build-up insulating layer 102.

  Next, as shown in FIG. 25L, a build-up wiring conductor 105 composed of a third conductor layer connected to the land pattern 104A is formed in the via hole 109 and on the surface of the insulating layer 102. The wiring conductor 105 made of the third conductor layer is formed by sequentially depositing an electroless plating layer and an electrolytic copper plating layer, and is formed using a known semi-additive method.

  Next, as shown in FIG. 25 (m), a predetermined number of layers of insulating layers 102 and wiring conductors 105 are formed as necessary, and finally, as shown in FIG. A solder resist layer 106 is deposited on the layer 102 and the wiring conductor 105 to complete the conventional wiring substrate 110.

  In recent years, the semiconductor integrated circuit element E has been rapidly integrated, and a wiring board on which the semiconductor integrated circuit element E is mounted is required to have high-density fine wiring with a width and interval of 20 μm or less. . In order to meet the demand for such high-density fine wiring, not only the build-up wiring conductor 105 to which the semiconductor element integrated circuit element E is connected, but also the core wiring conductor 104 has a width and interval of 30 μm. There is an increasing demand for making the following fine, and there is an increasing demand for increasing the density of wiring by forming a via hole 109 for build-up immediately above the through hole 107 formed in the insulating plate 101 for the core. Yes.

  However, in the above-described conventional wiring substrate 110, the pattern on the insulating plate 101 including the land pattern 104A in the core wiring conductor 104 is a copper foil 111 having a thickness of about 2 to 18 μm laminated on the insulating plate 101. After a second conductor layer having a thickness of about 15 to 30 μm is deposited on this layer, the copper foil 111 layer and the second conductor layer 114 exposed from the etching resist layer 115 formed thereon are etched. Since it is formed by removing, the layer of the copper foil 111 and the second conductor layer 114 are etched extremely greatly in the lateral direction according to the thickness at the time of etching. For example, the width and the adjacent interval are 20 μm or less. It is difficult to form the core wiring conductor 104 including the fine wiring pattern.

JP-A-11-274730

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board having a high-density fine wiring whose width and interval are 20 μm or less not only in a build-up wiring conductor but also in a core wiring conductor in a wiring board on which a semiconductor element is mounted. It is in providing the manufacturing method of.

The manufacturing method of the wiring board of the present invention includes:
Inner layer conductors made of copper foil are arranged between the two-sided copper-clad plates in which copper foils are laminated on the upper and lower surfaces of the core insulating plate or the laminated plates in which a plurality of core insulating plates are laminated. A step of preparing a multilayer board in which copper foil is laminated on the upper and lower surfaces, and
Forming a plurality of through holes from the upper surface to the lower surface of the double-sided copper-clad plate or multilayer plate;
Forming a first conductive layer formed by sequentially depositing a first electroless plating layer and a first electrolytic plating layer over the entire inner surface of the through hole and the upper and lower surfaces of the copper foil;
Filling the through hole with the first conductor layer deposited thereon with a filling resin;
Polishing and flattening the upper and lower ends of the hole-filling resin and the surface of the first conductor layer so that the copper foil layer remains on the upper and lower surfaces;
Etching the copper foil layer remaining on the upper and lower surfaces to reduce the thickness of the copper foil layer;
Depositing a second electroless plating layer over the surface of the copper foil layer with reduced thickness, the end surface of the first conductor layer, and the entire surface of the hole filling resin;
A plating resist layer having a predetermined pattern including an opening pattern for land formation that exposes a region corresponding to the through hole and the periphery thereof in the second electroless plating layer is formed on the second electroless plating layer. Process,
Depositing a second electrolytic plating layer on the second electroless plating layer exposed from the plating resist layer;
After the plating resist layer was peeled and removed from the second electroless plating layer, the second electroless plating layer exposed on the upper and lower surfaces and the copper foil layer thereunder were removed by etching. The first conductor in the through hole covers the periphery of the through hole and the periphery thereof by the second conductor layer comprising the copper foil layer, the second electroless plating layer, and the second electrolytic plating layer. Forming a core wiring conductor having a land pattern connected to the layer;
Forming a build-up insulating layer over the entire surface of the second conductor layer and the exposed upper and lower surfaces, and forming a via hole in the insulating layer with the center of the land pattern as a bottom surface;
Forming a wiring conductor for build-up consisting of a third conductor layer of a predetermined pattern connected to the land pattern in the via hole and on the surface of the insulating layer;
Are sequentially performed.

  According to the method for manufacturing a wiring board of the present invention, the upper and lower ends of the hole-filling resin filled in the through-hole on which the first conductor layer is deposited, the upper and lower surfaces of the core insulating plate, or a plurality of cores After polishing and planarizing the surface of the first conductor layer deposited on the copper foil layers on the upper and lower surfaces of the laminated plate in which insulating plates are laminated, the copper foil layer remains, The thickness of the copper foil layer is reduced by etching the copper foil layer, and then the second surface is formed over the entire surface of the copper foil layer having the reduced thickness, the end surface of the first conductor layer, and the entire surface of the hole filling resin. After the electroless plating layer is deposited, a predetermined pattern of the plating resist layer including the opening pattern for land formation exposing the region corresponding to the through hole and the periphery thereof in the second electroless plating layer is formed. On the electroless plating layer, and then the plating resist layer After the second electrolytic plating layer is deposited on the exposed second electroless plating layer, the plating resist layer is peeled and removed from the second electroless plating layer, and the second exposed on the upper and lower surfaces. By etching away the electroless plating layer and the underlying copper foil layer, the copper foil layer remaining on the upper and lower surfaces, the second electroless plating layer, and the second electroplating layer thereon are formed. Since the second conductor layer having a predetermined pattern is formed by the two conductor layers, fine wirings can be formed at high density on the upper and lower surfaces and the through hole. This is because when the second electroless plating layer exposed on the insulating plate for the core and the copper foil layer thereunder are removed by etching, the thickness of the second electroless plating layer and the thin copper foil thereunder are removed. This is because the second electrolytic plating layer is not greatly etched in the lateral direction because only the thickness of this layer needs to be etched. Therefore, according to the method for manufacturing a wiring board of the present invention, a via hole for build-up can be formed immediately above the through hole formed in the insulating plate for the core, and the width and interval of the core wiring conductor are 30 μm. It is possible to provide a method for manufacturing a wiring board including the following high-density fine wiring.

FIG. 1 is a schematic cross-sectional view showing an example of a wiring board manufactured by the manufacturing method of the present invention. (A), (b) is a schematic sectional drawing for demonstrating the example of one Embodiment in the manufacturing method of the wiring board of this invention. (C), (d) is a schematic sectional drawing for demonstrating the example of one Embodiment in the manufacturing method of the wiring board of this invention. (E), (f) is a schematic sectional drawing for demonstrating the example of 1 embodiment in the manufacturing method of the wiring board of this invention. (G), (h) is a schematic sectional drawing for demonstrating the example of 1 embodiment in the manufacturing method of the wiring board of this invention. (I), (j) is a schematic sectional drawing for demonstrating the example of one Embodiment in the manufacturing method of the wiring board of this invention. (K) is a schematic sectional drawing for demonstrating one Embodiment in the manufacturing method of the wiring board of this invention. (L)-(p) is a schematic sectional drawing for demonstrating the example of one Embodiment in the manufacturing method of the wiring board of this invention. (F), (g) is a schematic sectional drawing for demonstrating an example of other embodiment in the manufacturing method of the wiring board of this invention. (H), (i) is a schematic sectional drawing for demonstrating an example of other embodiment in the manufacturing method of the wiring board of this invention. (J), (k) is a schematic sectional drawing for demonstrating an example of other embodiment in the manufacturing method of the wiring board of this invention. (A), (b) It is a schematic sectional drawing for demonstrating another example of the other embodiment in the manufacturing method of the wiring board of this invention. (A), (b) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. (C), (d) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. (E), (f) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. (G), (h) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. (I), (j) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. (K), (l) is a schematic sectional drawing for demonstrating another example of other embodiment in the manufacturing method of the wiring board of this invention. FIG. 19 is a schematic cross-sectional view showing a wiring board manufactured by a conventional manufacturing method. (A), (b) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (C), (d) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (E), (f) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (G), (h) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (I) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board. (J)-(n) is a schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board.

Hereinafter, a method of manufacturing a wiring board according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing an embodiment of a wiring board manufactured by a manufacturing method according to the present invention, in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip-chip connection. Show.

  As shown in FIG. 1, a wiring board 10 manufactured according to the present invention is formed on the inside and the surface of an insulating substrate 3 in which a plurality of buildup insulating layers 2 are laminated on the upper and lower surfaces of a core insulating plate 1. The core wiring conductor 4 and the build-up wiring conductor 5 are deposited, and the solder resist layer 6 is deposited on the outermost surface thereof. In addition, a semiconductor element mounting portion 3A on which the semiconductor integrated circuit element E is mounted is provided at the center of the upper surface of the insulating base 3.

  The core insulating plate 1 has a thickness of about 50 to 800 μm, and is made of, for example, an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. Become. The insulating plate 1 functions as a core member of the insulating base 3.

  A plurality of through holes 7 having a diameter of 50 to 300 μm are formed from the upper surface to the lower surface of the core insulating plate 1, and the core wiring conductor 4 is attached to the inner surface of the through hole 7. Furthermore, the inside of the through hole 7 is filled with a hole filling resin 8, and the core wiring conductor 4 is also attached to the upper and lower surfaces of the insulating plate 1 including the hole filling resin 8. A part of the core wiring conductor 4 forms a land pattern 4 </ b> A for covering the through hole 7 and connecting to the build-up wiring conductor 5. The diameter of the land pattern 4A is about 70 to 150 μm larger than the diameter of the through hole 7. Further, a part of the wiring conductor 4 on the upper and lower surfaces of the insulating plate 1 has a fine pattern with a width or interval of 30 μm or less.

  In addition, the build-up insulating layer 2 has a thickness of about 20 to 50 μm, and a plurality of via holes 9 each having a diameter of about 35 to 100 μm are formed on the surface of each insulating layer 2 and the inner surface of the via hole 9. A wiring conductor 5 for build-up is formed on the substrate. The build-up wiring conductor 5 is connected to the land pattern 4 </ b> A in the core wiring conductor 4 through a part of the via hole 9. Further, a part of the build-up wiring conductor 5 deposited on the outermost insulating layer 2 on the upper surface side of the wiring substrate 10 is an electrode terminal of the semiconductor integrated circuit element E in the semiconductor element mounting portion 3A. Circular semiconductor element connection pads 5A that are electrically connected to T by flip-chip connection via conductive bumps B1 are formed, and a plurality of these semiconductor element connection pads 5A are formed in a lattice pattern. . These semiconductor element connection pads 5A are covered with the solder resist layer 6 at the outer periphery thereof, and the central part of the upper surface is exposed from the solder resist layer 6, and the semiconductor integrated pad 5A is integrated with the exposed portion of the semiconductor element connection pad 5A. The electrode terminal T of the circuit element E is electrically connected through a conductive bump B1 made of solder, gold or the like.

  On the other hand, a part deposited on the outermost insulating layer 2 on the lower surface side of the wiring board 10 is a circular external connection pad 5B electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 5B are formed in a grid. The external connection pad 5B has an outer peripheral portion covered with a solder resist layer 6 and a lower surface center portion exposed from the solder resist layer 6. An external electric circuit (not shown) is exposed on the exposed portion of the external connection pad 5B. The wiring conductor of the board is electrically connected via the solder ball B2. The solder resist layer 6 protects the outermost wiring conductor 5 and defines exposed portions of the semiconductor element connection pads 5A and the external connection pads 5B.

  A method for manufacturing the wiring board 10 according to the present invention will be described with reference to FIGS. First, as shown in FIG. 2A, a double-sided copper-clad plate 12 in which copper foils 11 are laminated on the upper and lower surfaces of an insulating plate 1 made of an electrically insulating material such as glass-epoxy resin or glass-bismaleimide triazine resin. Prepare. The thickness of the insulating plate 1 is, for example, about 50 to 800 μm, and the thickness of the copper foil 11 is, for example, about 2 to 18 μm. The surface of the copper foil 11 that is in close contact with the insulating plate 1 is a rough surface having a ten-point average height Rz of 0.10 to 7.0 μm. As such a double-sided copper-clad board 12, what is generally sold for printed wiring board applications may be used. In addition, when the copper foil 11 is thicker than 5 μm, it is preferable to reduce the thickness to 5 μm or less by polishing or etching. Thus, by setting the thickness of the upper and lower copper foils 11 in the double-sided copper-clad plate 12 to 5 μm or less, the formation of the through-hole 7 is facilitated in the step of forming the through-hole 7 described later.

  Next, as shown in FIG. 2B, through holes 7 are formed from the upper surface to the lower surface of the double-sided copper-clad plate 12 by drilling or laser processing. The diameter of the through hole 7 is about 50 to 300 μm. After forming the through hole 7, it is preferable to desmear the inner wall of the through hole 7 with an aqueous solution containing potassium permanganate, sodium permanganate or the like.

  Next, as shown in FIG. 3C, the first electroless copper plating layer 13a and the first electrolytic copper plating layer 13b are sequentially deposited over the entire inner wall of the through hole 7 and the entire surface of the copper foil 11. The first conductor layer 13 is formed. The thickness of the 1st electroless copper plating layer 13a is about 0.1-1.0 micrometer, and the thickness of the 1st electrolytic copper plating layer 13b is about 15-30 micrometers. A known plating solution may be used as a plating solution for performing these platings.

  Next, as shown in FIG. 3D, the hole filling resin 8 is filled into the through hole 7 to which the first conductor layer 13 is deposited. The hole-filling resin 8 is made of a resin-based insulating material in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin, and an inorganic insulating filler such as silica is added to a thermosetting resin composition such as an epoxy resin. It is formed by injecting a dispersed resin paste into the through hole 7 and thermosetting it. The resin paste may be injected using a known screen printing method.

  Next, as shown in FIG. 4E, the upper and lower ends of the hole filling resin 8 and the surfaces of the first conductor layer 13 and the copper foil 11 remain, and the copper foil 11 layer remains on the upper and lower surfaces of the insulating plate 1. So that it is polished and flattened. For polishing, a roll polishing device or a belt polishing device is preferably used. At this time, the thickness of the layer of the copper foil 11 remaining on the insulating plate 1 is about 2 to 5 μm. When polishing, the exposed surface of the first conductor layer 13 or the surface of the copper foil 11 is etched so that the end of the hole-filling resin 8 is removed from the first conductor layer 13 or the copper foil 11 layer. It is preferable that the method of polishing and then polishing the protruding hole filling resin 8 be repeated a plurality of times. By adopting such a method, the upper and lower ends of the hole filling resin 8 and the surfaces of the first conductor layer 13 and the copper foil 11 can be efficiently polished.

  Next, as shown in FIG. 4F, the upper and lower surfaces of the insulating plate 1 are exposed by removing the remaining layer of the copper foil 11 by etching. An etching solution containing cupric chloride, ferric chloride or the like may be used for etching the copper foil 11. At this time, the surface of the insulating plate 1 remains uneven with a ten-point average height Rz corresponding to the rough surface of the copper foil 11 of 0.10 to 7.0 μm. This unevenness functions as an anchor that strengthens the adhesion between the insulating plate 1 and the second conductor layer 14 when the second conductor layer 14 described later is formed.

  Next, as shown in FIG. 5G, the second electroless copper plating layer 14a is deposited over the entire upper and lower surfaces of the insulating plate 1, the end surface of the first conductor layer 13, and the entire surface of the hole filling resin 8. Let The second electroless copper plating layer 14a has a thickness of about 0.1 to 1.0 μm and is deposited by using a known electroless plating solution.

  Next, as shown in FIG. 5 (h), a predetermined pattern including an opening pattern for forming a land pattern 4A that exposes a region corresponding to and around the through hole 7 in the second electroless copper plating layer 14a. A plating resist layer 15 is deposited on the surface of the second electroless copper plating layer 14a. The plating resist layer 15 is formed by adhering a dry film resist made of a photosensitive resin onto the second electroless copper plating layer 14a and exposing and developing the predetermined pattern.

  Next, as shown in FIG. 6 (i), the second electrolytic copper plating layer 14 b is deposited on the second electroless copper plating layer 14 a exposed from the plating resist layer 15. The second electrolytic copper plating layer 14b has a thickness of about 15 to 30 μm and is deposited by using a known electrolytic plating solution.

  Next, as shown in FIG. 6 (j), the plating resist layer 15 is peeled off from the second electroless copper plating layer 14a. An alkaline stripping solution may be used for stripping the plating resist layer 15.

  Next, as shown in FIG. 7 (k), the second electroless copper plating layer 14a exposed on the insulating plate 1 is removed by etching, and the remaining second electroless copper plating layer 14a and second electrolysis are removed. A core wiring conductor 4 having a land pattern 4A connected to the first conductor layer 13 in the through hole 7 is formed by covering the periphery of the through hole 7 and its periphery with the second conductor layer 14 made of the copper plating layer 14b. To do. Such a method of forming the wiring conductor 4 using the second conductor layer 14 on the upper and lower surfaces of the insulating plate 1 is a so-called semi-additive method, and the first method is used in the etching for forming the wiring conductor 4. The second electrolytic copper plating layer 14b is not greatly etched in the lateral direction because it is only necessary to etch the thickness of the second electroless copper plating layer 14a. Accordingly, the second conductor layer 14 composed of the second electroless copper plating layer 14a remaining on the core insulating plate 1 and the second electrolytic copper plating layer 14b thereon is provided on the core insulating plate 1. Fine core wiring conductors 4 can be formed on the lower surface at high density. As a result, a land pattern 4A for connection to the build-up wiring conductor 5 is formed on the through-hole 7, so that the wiring conductor 4 in the through-hole 7 and the build-up wiring conductor 5 connected thereto are provided. Can be connected through the land pattern 4A in the shortest distance, and the wiring board 10 having high-density fine wiring in which the width and interval of the wiring in the core wiring conductor 4 are 30 μm or less can be provided. When the thickness of the electroless copper plating layer 14a is less than 0.1 μm, it is difficult to satisfactorily deposit the second electrolytic copper plating layer 14b on the surface of the electroless copper plating layer 14a. When the thickness exceeds 0 μm, the amount of the second electrolytic copper plating layer 14b etched in the lateral direction when the exposed portion of the second electroless copper plating layer 14a is removed by etching increases. In particular, the width and interval are 20 μm or less. There is a tendency that it is difficult to form fine wirings in a good manner. Therefore, the thickness of the second electroless copper plating layer 14a is preferably 0.1 to 1.0 μm. Note that a known etching solution containing hydrogen peroxide, sodium persulfate, or the like may be used for etching.

  Next, as shown in FIG. 8L, build-up insulating layers 2 are laminated on the upper and lower surfaces of the core insulating plate 1 on which the wiring conductors 4 are formed. The insulating layer 2 is a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 20 to 50 μm. Such an insulating layer 2 is made of, for example, an uncured resin sheet containing a thermosetting resin composition such as an epoxy resin and an inorganic insulating filler such as silica, as a core insulating plate 1 on which a wiring conductor 4 is formed. It is formed by sticking to the upper and lower surfaces and thermosetting. The insulating layer 2 may contain glass cloth.

  Next, as shown in FIG. 8 (m), the via hole 9 having the core wiring conductor 4 as the bottom surface is formed by laser processing the build-up insulating layer 2. The diameter of the via hole 9 is about 35 to 100 μm. Some of the via holes 9 have the center portion of the land pattern 4A on the through hole 7 as a bottom surface.

  Next, as shown in FIG. 8 (n), the build-up wiring conductor 5 composed of the third conductor layer 16 connected to the land pattern 4A is formed in the via hole 9 and on the surface of the insulating layer 2. The wiring conductor 5 composed of the third conductor layer 16 is formed by sequentially depositing an electroless copper plating layer having a thickness of about 0.1 to 1.0 μm and an electrolytic copper plating layer having a thickness of about 10 to 20 μm. The semi-additive method may be used.

  Next, as shown in FIG. 8 (o), a predetermined number of insulating layers 2 and wiring conductors 5 are formed as necessary. Finally, as shown in FIG. A solder resist layer 6 is deposited on the layer 2 and the wiring conductor 5 to complete the wiring substrate 10 according to the present invention. The solder resist layer 6 is a resin-based electrical insulating material containing a photosensitive thermosetting resin such as an acrylic-modified epoxy resin and an inorganic insulating filler such as silica, and has a thickness of about 10 to 25 μm. . Such a solder resist layer 6 is composed of, for example, an uncured photosensitive resin sheet or resin paste containing a thermosetting resin composition such as an acrylic-modified epoxy resin and an inorganic insulating filler such as silica, and the outermost insulating layer 2. In addition, it is formed by depositing on the wiring conductor 5 and exposing and developing to a predetermined pattern, followed by thermosetting.

  Thus, according to the method for manufacturing a wiring board of the present invention, it is possible to provide the wiring board 10 having high-density fine wiring in which the width and interval of the wiring in the core wiring conductor 4 are 20 μm or less. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the insulating plate 1 The upper and lower ends of the hole filling resin 8 and the surface of the first conductor layer 13 are polished and planarized so that the copper foil 11 layer remains on the upper and lower surfaces, and then the copper foil 11 remaining on the upper and lower surfaces of the insulating plate 1. Then, the upper and lower surfaces of the insulating plate 1 are exposed, and then a second electroless copper plating layer 14a is deposited on the entire surface of the insulating plate 1 and a second pattern of the second electrolytic copper plating is formed thereon. The layer 14b is deposited, and finally the second electroless copper plating layer 14a exposed on the insulating plate 1 is removed by etching, whereby the core wiring conductor 4 is formed on the insulating plate 1 and the hole-filling resin 8. As shown in FIG. 2 (a) in the above embodiment example. The upper and lower ends of the hole-filling resin 8 and the surface of the first conductor layer 13 are polished so that the copper foil 11 layer remains on the upper and lower surfaces of the insulating plate 1 through the steps described with reference to FIG. 9F, the copper foil 11 layer remaining on the upper and lower surfaces of the insulating plate 1 remains in a thickness of 1.0 to 2.0 μm without being completely removed by etching. The thickness is reduced by such etching, and then, as shown in FIG. 9 (g), the second electroless process is performed over the entire surface of the copper foil 11, the end surface of the first conductor layer 13, and the surface of the hole filling resin 8. A copper plating layer 14a is deposited to a thickness of 0.1 to 1.0 μm, and then, as shown in FIG. 10 (h), a plating resist layer 15 having a predetermined pattern is formed on the surface of the second electroless copper plating layer 14a. And plating resist layer 15 as shown in FIG. 10 (i). Then, a second electrolytic copper plating layer 14b is deposited on the second electroless copper plating layer 14a exposed from the second electroless copper plating layer 14a. Then, as shown in FIG. After the plating resist layer 15 is peeled and removed, as shown in FIG. 11 (k), the second electroless copper plating layer 14a exposed on the insulating plate 1 and the underlying copper foil 11 are removed by etching. The wiring conductor 4 for the core may be formed by

  In this case, the second electrolytic copper plating layer 14b is greatly etched in the lateral direction because it is only necessary to etch the thickness of the reduced thickness of the copper foil 11 and the second electroless copper plating layer 14a. There is no. Therefore, the second conductor layer 14 composed of the thin copper foil 11 layer remaining on the core insulating plate 1, the second electroless copper plating layer 14a, and the second electrolytic copper plating layer 14b thereon. Thus, fine core wiring conductors 4 can be formed on the surface of the core insulating plate 1 and the through holes 7 at a high density. As a result, a via hole 9 for buildup can be formed immediately above the through hole 7 formed in the insulating plate 1 for the core, and the wiring conductor 4 for the core also has a high density of 30 μm or less. A method of manufacturing a wiring board including fine wiring can be provided. In addition, when the total thickness of the copper foil 11 layer and the electroless copper plating layer 14a having a reduced thickness is less than 1 μm, the adhesion strength between the resin of the insulating substrate 1 and the copper foil 11 layer is reduced. When the thickness exceeds 2 μm, the second electrolytic copper plating layer 14b is etched in the lateral direction when the copper foil 11 having a reduced thickness and the exposed portion of the second electroless copper plating layer 14a are removed by etching. Therefore, it tends to be difficult to satisfactorily form fine wiring having a width and interval of 30 μm or less. Therefore, the total thickness of the copper foil 11 having a reduced thickness and the second electroless copper plating layer 14a is preferably 1 to 2 μm. In this case, the surface of the copper foil 11 in contact with the insulating plate 1 preferably has a ten-point average roughness Rz in the range of 0.02 to 3.0 μm.

  Furthermore, in the above-described embodiment, the double-sided copper-clad plate 12 having the copper foil 11 deposited on the upper and lower surfaces of the insulating plate 1 is used as a core substrate. FIG. 12A shows a schematic cross-sectional view. In this way, an inner layer conductor 21 made of copper foil is laminated between the insulating plates 1 in a laminated plate in which a plurality of core insulating plates 1 are laminated, and a copper foil 11 is laminated on the upper and lower surfaces thereof. Using the board 22 as a core substrate, the wiring substrate 30 having the core inner conductor 21 as shown in FIG. 12B may be formed using the same manufacturing method as in the above-described embodiment. .

  Furthermore, in the above-described embodiment, both surfaces in which copper foils 11 are directly attached to the upper and lower surfaces of the insulating plate 1 made of an electrically insulating material such as glass-epoxy resin or glass-bismaleimide triazine resin as a core substrate. Although the copper-clad plate 12 is used, as shown in FIG. 13A, the surface can be roughened on the upper and lower surfaces of the insulating plate 1 made of an electric insulating material such as glass-epoxy resin or glass-bismaleimide triazine resin. A double-sided copper-clad plate 32 with a primer resin layer to which the copper foil 11 is attached via the primer resin layer P may be used as a starting material for the core. The primer resin layer P contains a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and the arithmetic average roughness of the surface with a roughening solution such as an aqueous solution containing potassium permanganate or sodium permanganate. A resin that can be roughened with Ra to 100 to 600 nm is used. For such resins, a fine filler that forms a roughened surface on the surface of the primer resin layer P by protruding or dropping from the surface of the resin during the treatment with the roughening liquid, or a roughening liquid is preferred. A fine resin phase that forms a roughened surface on the surface of the primer resin layer P is dispersed by being dissolved in the primer resin layer P. Moreover, as the copper foil 11, the surface roughness of the surface in contact with the primer resin layer P is 500 nm or less, particularly 300 nm or less in terms of arithmetic average roughness Ra. In this case, when the surface roughness of the surface of the copper foil 11 in contact with the primer resin layer P exceeds 500 nm, the primer resin layer P after the copper foil 11 is removed from the surface of the primer resin layer P by etching as described later. Since the risk that the arithmetic average roughness Ra of the surface becomes a rough surface exceeding 600 nm increases, it tends to be difficult to form the fine wiring conductor 4 on the surface of the primer resin layer P.

  When a wiring board is manufactured using such a double-sided copper-clad plate 32 with a primer resin layer, first, as shown in FIG. 13B, the through-hole 7 is formed from the upper surface to the lower surface of the double-sided copper-clad plate 32 as described above. It is formed in the same manner as the embodiment.

  Next, as shown in FIG. 14 (c), the first electroless copper plating layer 13 a and the first electrolytic copper plating layer 13 b are sequentially applied over the entire inner wall of the through hole 7 and the entire surface of the copper foil 11. The first conductor layer 13 thus formed is formed in the same manner as in the above embodiment.

  Next, as shown in FIG. 14D, the filling resin 8 is filled in the through hole 7 to which the first conductor layer 13 is deposited in the same manner as in the above-described embodiment.

  Next, as shown in FIG. 15 (e), the upper and lower ends of the hole-filling resin 8 and the surfaces of the first conductor layer 13 and the copper foil 11 are left so that the layer of the copper foil 11 remains on the primer resin layer P. Then, the surface is polished and flattened in the same manner as in the above embodiment.

  Next, as shown in FIG. 15 (f), the remaining copper foil 11 layer is removed by etching in the same manner as in the above-described embodiment to expose the surface of the primer resin layer P. At this time, the surface of the primer resin layer P is a smooth surface having an arithmetic average roughness Ra corresponding to the surface of the copper foil 11 of 500 nm or less.

  Next, as shown in FIG. 16G, the exposed surface of the primer resin layer P is roughened so that the arithmetic average roughness Ra has minute irregularities of 100 to 600 nm. For the roughening, a roughening solution such as an aqueous solution containing potassium permanganate or sodium permanganate may be used. This minute unevenness functions as an anchor that strengthens the adhesion between the primer resin layer P and the second conductor layer 14 when the second conductor layer 14 described later is formed. Further, it is possible to satisfactorily form fine wiring conductors 4 on the primer resin layer P by roughening the surface of the primer resin layer P so that the arithmetic average roughness Ra has minute irregularities of 100 to 600 nm. It becomes. In addition, when the surface roughness after roughening in the primer resin layer P is less than 100 nm in terms of arithmetic average roughness Ra, it tends to be difficult to firmly adhere the primer resin layer P and the second conductor layer 14. If it exceeds 600 nm, it tends to be difficult to satisfactorily form the fine wiring conductor 4 on the primer resin layer P. Therefore, the surface roughness after roughening in the primer resin layer P is preferably in the range of 100 to 600 nm in terms of arithmetic average roughness Ra.

  Next, as shown in FIG. 16 (h), the second electroless copper plating layer 14 a is formed on the surface of the primer resin layer P, the end surface of the first conductor layer 13, and the entire surface of the hole-filling resin 8. It is applied in the same manner as in the embodiment. The second electroless copper plating layer 14a has a thickness of about 0.1 to 1.0 μm. At this time, since the arithmetic average roughness Ra of the surface of the primer resin layer P to which the second electroless copper plating layer 14a is applied is 100 to 600 nm, it is a roughened surface having fine irregularities. The electroless copper plating layer 14a and the primer resin layer P are firmly adhered with the fine irregularities as anchors, and the surface of the second electroless copper plating layer 14a has an arithmetic average roughness Ra of 100 to 100. The surface has fine irregularities of 600 nm.

  Next, as shown in FIG. 17 (i), a predetermined pattern including an opening pattern for forming a land pattern 4A that exposes a region corresponding to and around the through hole 7 in the second electroless copper plating layer 14a. The plating resist layer 15 is deposited on the surface of the second electroless copper plating layer 14a in the same manner as in the above embodiment. At this time, the surface of the second electroless copper plating layer 14a is a surface having a fine asperity with an arithmetic average roughness Ra of 100 to 600 nm as described above. The electrolytic copper plating layer 14a can be in good contact with no gap.

  Next, as shown in FIG. 17 (j), the second electrolytic copper plating layer 14b is coated on the second electroless copper plating layer 14a exposed from the plating resist layer 15 in the same manner as the above-described embodiment. Put on. At this time, as described above, since the plating resist layer 15 and the electroless copper plating layer 14a are in good contact with each other without any gap, the electrolytic copper plating layer 14b does not sink under the plating resist layer 15, and thus the plating resist A precise pattern corresponding to the opening pattern of layer 15 is applied.

  Next, as shown in FIG. 18 (k), after removing the plating resist layer 15 from the second electroless copper plating layer 14a in the same manner as in the above-described embodiment, it is shown in FIG. 18 (l). As described above, the second electroless copper plating layer 14a exposed on the primer resin layer P is removed by etching in the same manner as in the above-described embodiment, and the remaining second electroless copper plating layer 14a and the second electrolysis copper are removed. A core wiring conductor 4 having a land pattern 4A connected to the first conductor layer 13 in the through hole 7 is formed by covering the periphery of the through hole 7 and its periphery with the second conductor layer 14 made of the copper plating layer 14b. To do. As a result, a via hole 9 for buildup can be formed immediately above the through hole 7 formed in the insulating plate 1 for the core, and the wiring conductor 4 for the core also has a high density of 30 μm or less. A method of manufacturing a wiring board including fine wiring can be provided. At this time, the electrolytic copper plating layer 14 b is not exposed under the plating resist layer 15, but is exposed on the primer resin layer P because it is deposited in an accurate pattern corresponding to the opening pattern of the plating resist layer 15. A wiring board having high-density fine wiring in which the width and interval of the wiring in the core wiring conductor 4 is 30 μm or less (particularly 20 μm or less) is further removed by etching away the second electroless copper plating layer 14a. It can be reliably provided. Moreover, you may use such a primer resin layer P between the copper foil 11 and the insulating board 1 in the multilayer board 22 shown to Fig.12 (a). The surface of the core wiring conductor 4 that is in contact with the build-up insulating layer is preferably subjected to a chemical roughening treatment in order to strengthen the adhesion with the build-up insulating layer.

1: Insulating plate for core 2: Insulating layer for buildup 4: Wiring conductor for core 4A: Land pattern 5: Wiring conductor for buildup 7: Through hole 8: Filling resin 9: Via hole 11: Copper foil 12: Double-sided copper-clad board 13: First conductor layer 13a: First electroless plating layer 13b: First electroplating layer 14: Second conductor layer 14a: Second electroless plating layer 14b: Second Electrolytic plating layer 15: Plating resist layer 16: Third conductor layer 21: Inner layer conductor 22: Multilayer board 32: Double-sided copper-clad board with primer resin layer P: Primer resin layer

Claims (1)

Inner layer conductors made of copper foil are arranged between the two-sided copper-clad plates in which copper foils are laminated on the upper and lower surfaces of the core insulating plate or the laminated plates in which a plurality of core insulating plates are laminated. A step of preparing a multilayer board in which copper foil is laminated on the upper and lower surfaces, and
Forming a plurality of through holes from the upper surface to the lower surface of the double-sided copper-clad plate or multilayer plate;
Forming a first conductor layer formed by sequentially depositing a first electroless plating layer and a first electrolytic plating layer over the entire inner surface of the through-hole and the upper and lower copper foil surfaces;
Filling the through hole with the first conductor layer deposited thereon with a filling resin;
Polishing and flattening the upper and lower ends of the hole-filling resin and the surface of the first conductor layer so that the copper foil layer remains on the upper and lower surfaces;
Etching the copper foil layer remaining on the upper and lower surfaces to reduce the thickness of the copper foil layer;
Depositing a second electroless plating layer over the surface of the copper foil layer with reduced thickness, the end surface of the first conductor layer, and the entire surface of the hole filling resin;
A plating resist layer having a predetermined pattern including an opening pattern for land formation that exposes a region corresponding to the through hole and the periphery thereof in the second electroless plating layer is formed on the second electroless plating layer. Process,
Depositing a second electrolytic plating layer on the second electroless plating layer exposed from the plating resist layer;
After the plating resist layer was peeled and removed from the second electroless plating layer, the second electroless plating layer exposed on the upper and lower surfaces and the copper foil layer thereunder were removed by etching. The first conductor in the through hole covers the periphery of the through hole and the periphery thereof by the second conductor layer comprising the copper foil layer, the second electroless plating layer, and the second electrolytic plating layer. Forming a core wiring conductor having a land pattern connected to the layer;
Forming a build-up insulating layer over the entire surface of the second conductor layer and the exposed upper and lower surfaces, and forming a via hole in the insulating layer with the center of the land pattern as a bottom surface;
And a step of forming a build-up wiring conductor comprising a third conductor layer of a predetermined pattern connected to the land pattern in the via hole and on the surface of the insulating layer. Method.

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