JP5573786B2 - Noise tolerance evaluation method and noise tolerance evaluation apparatus for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a noise tolerance evaluation method for a semiconductor integrated circuit and a noise tolerance evaluation apparatus for implementing the same.

  For example, Japanese Patent Laid-Open No. 2002-270695 (Patent Document 1) and Japanese Patent Laid-Open No. 2007-73838 (Patent Document 2) disclose methods for evaluating noise resistance of a semiconductor integrated circuit.

  FIG. 29 is a flowchart showing an outline of a conventional noise tolerance evaluation method 90.

  In the noise immunity evaluation method 90 shown in FIG. 29, a circuit netlist describing connection information of each element constituting the semiconductor integrated circuit is created in step S11 from the circuit diagram of the semiconductor integrated circuit designed in step S1. To do. Next, based on the circuit net list created in step S11, in step S2, a circuit simulation for noise tolerance by a circuit simulator (SPICE) is performed. Next, in step S3, the noise tolerance of the semiconductor integrated circuit designed in step S1 is determined from the circuit simulation result obtained in step S2. If the noise tolerance is insufficient (NO), the process returns to step S1, corrects the circuit diagram, and repeats steps S11, S2, and S3. Then, the process proceeds to step S4 for the first time when the noise resistance becomes sufficient in step S3 (YES), and the noise resistance evaluation of the semiconductor integrated circuit is completed.

  FIG. 30 is a flowchart showing the outline of the conventional noise tolerance evaluation method 91, which is a more precise version of the noise tolerance evaluation method 90 of FIG. In the flowchart of the noise tolerance evaluation method 91 shown in FIG. 30, the same steps as those in the flowchart of the noise tolerance evaluation method 90 shown in FIG.

  A noise tolerance evaluation method 91 in FIG. 30 is a more accurate noise tolerance evaluation method for a semiconductor integrated circuit by incorporating layout information of each element constituting the semiconductor integrated circuit into the noise tolerance evaluation method 90 in FIG. . That is, in the noise immunity evaluation method 91 of FIG. 30, the step of creating the layout diagram of each element constituting the semiconductor integrated circuit shown in step S1a and extracting the parasitic element in the flowchart of FIG. It is added after. Therefore, the circuit netlist created in step S11 of the flowchart of FIG. 30 not only contains connection information for each element constituting the semiconductor integrated circuit, but also occurs due to the layout of each element. The connection information of each parasitic element is also described. Next, based on the circuit net list created in step S11, a circuit simulation for noise resistance is performed by the circuit simulator (SPICE) in step S2. In the noise tolerance determination in step S3 of FIG. 30, if the noise tolerance is insufficient (NO), the layout diagram is corrected by returning to step S1a, or the circuit diagram and the layout diagram are corrected after returning to step S1, Steps S11, S2, and S3 are repeated. Then, the process proceeds to step S4 for the first time when the noise resistance becomes sufficient in step S3 (YES), and the more accurate noise resistance evaluation of the semiconductor integrated circuit incorporating the layout information is completed.

JP 2002-270695 A JP 2007-73838 A

  In order to evaluate the tolerance to external noise (possibility of malfunction) for the designed semiconductor integrated circuit, conventionally, as shown in steps S2 and S3 of FIGS. 29 and 30, noise generated by a circuit simulator (SPICE) is used. Circuit simulation for tolerance has been performed.

  However, as the semiconductor integrated circuit becomes a large-scale LSI, a large number of circuit blocks are formed on one chip, and the number of elements mounted on the chip is remarkably increased. For this reason, the circuit net list in step S11 of FIG. 29 includes a large amount of element models such as transistors, resistors, and capacitors, and becomes a large-scale net list. In addition, in the circuit netlist in step S11 of FIG. 30, parasitic elements such as parasitic resistance, parasitic capacitance, and parasitic inductance, which become propagation paths of the high-frequency signal extracted from the layout information, are added, and the scale is further increased. Netlist information. In addition, in the circuit simulation for noise immunity in step S2 shown in FIGS. 29 and 30, a signal in a wide frequency range of several kHz to several GHz corresponding to external noise is input separately from the input signal for functional operation. It is necessary to let For example, in recent cases, circuit malfunctions in the order of several tens of MHz to GHz have been reported. To evaluate the noise immunity of each circuit block, it is necessary to analyze the period of the external noise and the time constant of the responsiveness of each circuit block for a sufficiently long time, and the circuit simulation per unit time as the external noise becomes high frequency As the number of analysis points increases, a long analysis time is required. Further, as parameters of the external noise used in the circuit simulation in step S2, it is necessary to consider not only the frequency but also the noise amplitude, the noise input node (terminal), and the like.

  From the above situation, the noise tolerance evaluation methods 90 and 91 by the conventional circuit simulator (SPICE) shown in steps S2 and S3 of FIGS. 29 and 30 are applied to the analysis of noise tolerance of a large-scale semiconductor integrated circuit. In many cases, however, it does not converge, and even if it converges, the analysis time becomes enormous and it becomes unrealistic.

  The present invention has been made in view of the above circumstances, and is a novel noise tolerance evaluation method that replaces the conventional circuit simulation and a noise tolerance evaluation apparatus that implements the same, and even if it is a large-scale semiconductor integrated circuit, It is an object of the present invention to provide a noise resistance evaluation method and a noise resistance evaluation apparatus for a semiconductor integrated circuit capable of performing a general noise resistance evaluation in a short time.

The invention according to claim 1 is a noise tolerance evaluation method for a semiconductor integrated circuit for evaluating the tolerance of the semiconductor integrated circuit against noise , implemented in a noise tolerance evaluation apparatus ,
A circuit net list creation unit creating a circuit net list from a circuit diagram of the semiconductor integrated circuit;
A second step in which a replacement circuit netlist creation unit creates a replacement circuit netlist by replacing active elements in the circuit netlist with high-frequency equivalent passive element circuits;
A third step in which a control node extraction unit extracts a control node corresponding to a control terminal of the transistor before replacement from the replacement circuit netlist;
A fourth step in which a noise injection node setting unit selects a predetermined node from the replacement circuit netlist and sets a noise injection node;
A fifth step in which a noise frequency setting unit sets noise of a predetermined frequency, and a path impedance calculation unit calculates a path impedance between the control node and the noise injection node different from each other in the replacement circuit netlist; ,
An impedance list creation unit creating a list of the impedance in each combination of the control node, the noise injection node, and the path;
The noise tolerance determination unit includes a seventh step of determining noise tolerance of the semiconductor integrated circuit from the minimum value of the impedance in the list.

  The noise immunity evaluation method for a semiconductor integrated circuit is a novel noise immunity evaluation method that replaces the conventional circuit simulation. In the noise immunity evaluation method, by analyzing the noise propagation path and the impedance of the path, a malfunction due to noise of each transistor constituting the semiconductor integrated circuit is generated without basically using a circuit simulator (SPICE). This possibility can be easily evaluated in a short time. In the noise tolerance evaluation method, each process performed in the first step to the seventh step will be described in detail below.

  The first step in the noise tolerance evaluation method is a step of creating a circuit netlist from the circuit diagram of the semiconductor integrated circuit. The circuit netlist describes circuit topology information of a semiconductor integrated circuit to be evaluated, that is, connection information between devices constituting the semiconductor integrated circuit. The creation of the circuit netlist in the first step is a basic step in the case of performing a simulation, and is the first step performed in a noise tolerance evaluation method using a conventional circuit simulator (SPICE), for example.

  Next, in the second step of the noise tolerance evaluation method, the replacement element net list is created by replacing the active element in the circuit net list created in the first step with a passive element circuit equivalent in terms of high frequency. Therefore, in the replacement circuit netlist, the semiconductor integrated circuit to be evaluated is described as a passive element integrated circuit composed of all passive elements, and connection information of all the passive elements is described.

  Next, in the third step of the noise tolerance evaluation method, a control node corresponding to the control terminal of the transistor before replacement is extracted from the replacement circuit netlist created in the second step. The control terminal of the transistor is a base terminal if it is a bipolar transistor, and a gate terminal if it is a MOS transistor. The control node extraction in the third step may be performed by extracting all control nodes in the replacement circuit netlist or, for example, a malfunction that handles a high amplification factor, a minute current, and a minute voltage is likely to occur. Some control nodes may be extracted.

  In the fourth step of the noise tolerance evaluation method, a predetermined node is selected from the replacement circuit net list created in the second step, and a noise injection node is set. In the fourth step, for example, if a noise injection node is set only for a node corresponding to an external terminal, the noise resistance of the semiconductor integrated circuit against external noise is evaluated. On the other hand, if noise injection nodes are set only for some of the nodes corresponding to the transistors before replacement, which are likely to generate noise, such as oscillation circuits and clock generation circuits, the noise resistance of the semiconductor integrated circuit against internal noise Will be evaluated. Needless to say, noise injection nodes may be set for all nodes in the replacement circuit netlist.

  Next, in the fifth step of the noise tolerance evaluation method, noise of a predetermined frequency is set, and in the replacement circuit netlist created in the second step, the path between the control node and the noise injection node different from each other is set. Calculate the impedance. In a sixth step, the impedance calculation results for each combination of control node, noise injection node, and path are integrated to create an impedance list.

  The impedance calculation in the fifth step may be performed for each control line and noise injection node that are different from each other, as described later, and may be calculated as a combined impedance of the net path. It may be.

  Finally, in the seventh step of the noise tolerance evaluation method, the noise tolerance of the semiconductor integrated circuit is determined from the minimum impedance value in the list. That is, when the minimum impedance value in the list is smaller than a predetermined reference value, it is determined that there is no noise tolerance, the process returns to the first step, and the circuit diagram of the semiconductor integrated circuit is corrected. Then, the first to seventh steps described above are repeated for the corrected circuit diagram, and the noise resistance evaluation is continued. Finally, when the minimum impedance value in the list created in the sixth step becomes larger than a predetermined reference value in the seventh step, it is determined that there is noise tolerance, and the noise of the semiconductor integrated circuit is determined. End resistance evaluation.

  As described above, the noise immunity evaluation method for a semiconductor integrated circuit described above evaluates the noise immunity of a semiconductor integrated circuit by analyzing the noise propagation path and the impedance of the path. Thus, the circuit simulation by the circuit simulator (SPICE) is not performed. For this reason, it is not necessary to perform a large-scale analysis unlike the noise tolerance evaluation method based on the conventional circuit simulation, and it is possible to efficiently evaluate the noise tolerance within a limited design period.

  As described above, the noise immunity evaluation method for the semiconductor integrated circuit is a novel noise immunity evaluation method that replaces the conventional circuit simulation, and a substantial noise immunity evaluation can be performed even for a large-scale semiconductor integrated circuit. It can be a method for evaluating noise resistance of a semiconductor integrated circuit that can be performed in a short time.

Since the noise tolerance evaluation method of the semiconductor integrated circuit can evaluate the noise tolerance in a short time, the parasitic element extraction unit is obtained from the layout diagram of the semiconductor integrated circuit as described in claim 2. An eighth step of extracting parasitic elements based on the layout information to be generated , and in the first step, the circuit net list creation unit creates a circuit net list including the parasitic elements. Is preferred.

  As a result, the noise tolerance evaluation is performed on the propagation path of the high-frequency signal (noise) including the parasitic element, and the noise tolerance of the semiconductor integrated circuit can be more accurately evaluated.

In the noise immunity evaluation method for the semiconductor integrated circuit, as described in claim 3, for example, in the third step, the control node extraction unit extracts all control nodes from the replacement circuit netlist. Thus, it is possible to evaluate the noise resistance of all the transistors present in the semiconductor integrated circuit.

According to a fourth aspect of the present invention, in the third step, the control node extraction unit may select and extract a predetermined control node from the replacement circuit netlist . For example, among the transistors that are present in the semiconductor integrated circuit, malfunction amplification factor is higher may be evaluated noise immunity by selecting the transistor that would likely occur.

In the noise immunity evaluation method of the semiconductor integrated circuit, as described in claim 5, in the fourth step, the noise injection node setting unit selects all nodes from the replacement circuit netlist, A noise injection node can be set. According to this, it is possible to evaluate noise resistance for both external noise propagating from an external terminal of the semiconductor integrated circuit and internal noise generated by a specific transistor in the semiconductor integrated circuit.

In addition, when it is considered that there is no possibility of malfunction due to internal noise, in the fourth step, the noise injection node setting unit is externally connected to the external circuit from the replacement circuit netlist. A noise injection node may be set by selecting a terminal node. According to this, it is possible to evaluate the noise resistance of only the external noise propagating from the external terminal of the semiconductor integrated circuit.

In the noise immunity evaluation method of the semiconductor integrated circuit, as described in claim 7, in the fifth step, the path impedance calculation unit calculates a combined impedance of a net path between the control node and a noise injection node. Preferably, in the sixth step, the impedance list creation unit creates the list of the combined impedances in each combination of the control node and the noise injection node.

  According to this, in comparison with the method of calculating the impedance of the line path between the control node and the noise injection node according to claim 10 described later, each line path is actually in the net path between the control node and the noise injection node. Reflects the noise that propagates in a more faithful manner. For this reason, more accurate noise tolerance evaluation is possible.

In this case, as described in claim 8, the path impedance calculation unit includes a circuit simulator, and the circuit simulator gives a predetermined AC potential difference or an AC current to the control node and the noise injection node, and the control is performed. The combined impedance may be calculated from the total current flowing between the node and the noise injection node or the potential difference between the nodes . This makes it easy to create a list of the combined impedances.

The path impedance calculation unit may provide a predetermined AC potential difference or an AC current to the control node and the noise injection node by using a hardware description language, and the control node and the noise injection. It is also possible to calculate the combined impedance from the total current flowing between the nodes or the potential difference between the nodes.

  In the method using the circuit simulator according to the eighth aspect, it is impossible to identify and handle the noise propagation direction for one noise propagation path. For this reason, in the method using the circuit simulator, for example, when the diode is replaced with a passive element in the second step, it is necessary to select and replace either forward noise propagation or backward noise propagation. On the other hand, in the method using the hardware description language according to the ninth aspect, it is possible to identify and handle the noise propagation direction for one noise propagation path. Therefore, the method using the hardware description language according to claim 9 can perform more accurate noise tolerance evaluation than the method using the circuit simulator according to claim 8.

On the other hand, in the net path between the control node and the noise injection node, when it is possible to specify to some extent a line path where noise easily propagates or a line path where noise hardly propagates, the fifth path as described in claim 10 In the step, the path impedance calculation unit calculates an impedance of a line path between the control node and the noise injection node. In the sixth step, the impedance list creation unit includes the control node, the noise injection node, and the noise injection node. A list of the impedances in each combination of the line paths may be created.

Further, in the noise immunity evaluation method for the semiconductor integrated circuit, as described in claim 11, the replacement circuit netlist creation unit sets a ground (GND) node and a power supply node of the replacement circuit netlist in an alternating manner. The AC ground node may be set to 0 potential.

The above-described GND node and power supply node are, for example, a GND terminal or a power supply terminal of an IC terminal, and when these IC terminals have a low impedance outside the IC, an AC ground node that can be set to 0 potential in an alternating manner. It can be. The AC ground node is not limited to the GND node and the power supply node, but may be the following node. For example, this is a case where a GND terminal and a power supply terminal in each circuit block in the IC are directly connected to the outside of the IC via the IC terminal, and these IC terminals have a low impedance outside the IC. In addition, other IC terminals to which a large-capacitance capacitor (several μF or more) is added externally, terminals of each circuit block, or Si substrate node when the silicon (Si) substrate is securely grounded (GND) May be an AC ground node. Note that each of the nodes described above can be individually an AC ground node, or all nodes can be AC ground nodes.

  Since the number of noise propagation paths to be evaluated can be reduced by setting the AC ground node as described above, the impedance calculation in the fifth step is facilitated.

  Moreover, in the noise tolerance evaluation method for the semiconductor integrated circuit, as described in claim 12, the semiconductor integrated circuit may be an entire circuit formed in one semiconductor chip. As described above, the semiconductor integrated circuit may be a circuit block that is a component of an entire circuit formed in one semiconductor chip.

In the noise immunity evaluation method of the semiconductor integrated circuit, as described in claim 14, in the fifth step, the noise frequency setting unit sets the frequency of the noise to be set in order to evaluate the frequency dependence of impedance. is varied in a predetermined frequency range, the route impedance calculation unit preferably calculates the impedance of the path between the control node and the noise injection node.

  According to this, compared with the case where noise tolerance is evaluated only with one noise frequency, more reliable noise tolerance can be evaluated.

  Further, by evaluating the frequency dependence of each impedance between the control node and the noise injection node as described above, it is determined whether each noise propagation path is capacitive, resistive, or inductive. be able to. That is, if the propagation path impedance is inversely proportional to the noise frequency, it is capacitive, if the propagation path impedance does not depend on the noise frequency, it is resistive, and if the propagation path impedance is proportional to the noise frequency, it is inductive. It is. By determining whether the noise propagation path is capacitive, resistive, or inductive, it is possible to implement appropriate and reliable noise countermeasures that match the following propagation path characteristics.

For example, in the noise immunity evaluation method for the semiconductor integrated circuit, as described in claim 15, a noise countermeasure is provided for a combination of the control node and the noise injection node determined as having no noise immunity in the seventh step. The circuit creation unit may insert a noise countermeasure element having a predetermined impedance between the control node and an AC ground node that is set to 0 potential in an alternating manner.

In this case, as described in claim 16, for the combination of the control node and the noise injection node determined to have no noise tolerance in the seventh step, the impedance of the path is capacitive in inverse proportion to the frequency. In this case, the noise countermeasure circuit creation unit calculates a ground impedance between the control node and the AC ground node for the transistor before replacement , and the impedance as the noise countermeasure element is smaller than a minimum value of the ground impedance. Is preferably inserted between the control node and the AC ground node.

  The control node is the base of the bipolar transistor or the gate of the MOS transistor as described above, and the above-mentioned ground impedance generally has a large value. Accordingly, when the noise propagation path is capacitive, a capacitance having an impedance smaller than the ground impedance of the transistor is inserted between the control node and the AC ground node. As a result, a new path for escaping noise reaching the control node to the AC ground node is arranged, and malfunction of the transistor due to noise can be suppressed. When the impedance of the capacitor inserted between the control node and the AC ground node is sufficiently small, the control node is in a state of being pseudo-AC grounded against noise.

  When implementing noise countermeasures, unlike the above, it is possible to add a noise countermeasure capacitor to the noise injection node and connect it to the AC ground node to allow the noise injected into the noise injection node to escape to the AC ground node as soon as possible. However, the method of adding the noise countermeasure capacitance to the noise injection node requires a large capacitance because the noise injected into the noise injection node is not attenuated. On the other hand, the method of adding a noise countermeasure capacitor to the control node of a transistor that is easily affected by the noise determined to have no noise tolerance described above attenuates the noise by the impedance of the propagation path from the noise injection node to the control node. Therefore, the capacity may be a smaller value.

  The ground impedance calculated for the transistor before replacement can be calculated using, for example, a circuit simulator (SPICE). Further, for example, as described in claim 17, it may be a combined impedance of a net path between the control node and the AC ground node after the replacement.

In addition, as described in claim 18, with respect to a combination of the control node and the noise injection node determined to have no noise tolerance in the seventh step, a resistance whose frequency impedance does not depend on a frequency, or a frequency When the inductivity increases in proportion to the noise suppression circuit , the noise suppression circuit creation unit inserts at least one of a resistor and an inductance in series in front of the control node as the noise suppression element, and the capacitance is It is preferable to insert a low-pass filter between the control node and the AC ground node, and at least one of the resistor and the inductance and the capacitor.

  When the noise propagation path is resistive or inductive as described above, at least one of the resistance and the inductance is inserted in series before the control node so that the path impedance to the control node becomes sufficiently high. To increase the attenuation of noise. A low-pass filter is formed by at least one of the resistor and the inductance and a capacitor inserted between the control node and the AC ground node. According to this, by appropriately setting at least one of the resistance and the inductance and the value of the capacitance, it is possible to cut off a problematic high frequency noise component and suppress the transmission of the noise component to the transistor. . If the noise propagation path is resistive, the resistance inserted between the control node and the AC ground node and the impedance of the resistive path is not inserted in series in front of the control node. It is also possible to configure a low-pass filter.

  The invention described in claims 19 to 21 relates to a noise tolerance evaluation apparatus for a semiconductor integrated circuit, which implements the noise tolerance evaluation method described above.

Noise immunity evaluation apparatus according to claim 19, a noise immunity evaluation apparatus of semi-conductor integrated circuit,
Based on the circuit information obtained from the circuit diagram of the semiconductor integrated circuit, a circuit netlist creation unit that creates a circuitry netlist,
Based on replacement information to the passive element circuit from the active element, the circuit active elements in the net list replacing the high-frequency equivalent passive element circuit, replacing circuit creating a location circuit netlist netlist generation unit When,
From the substitution circuit netlist, a control node extracting unit that extracts a control node corresponding to a control terminal of the replacement before the transistor,
And selecting a predetermined node from the substitution circuit netlist, and the noise injection node setting unit for setting a noise injection node,
And the noise frequency setting unit which sets the noise of Jo Tokoro frequency,
In said replacement circuit netlist, and route the impedance calculation unit for calculating the impedance of the route between different said control node and said noise injection node,
An impedance list creation unit for creating a list of the impedances in each combination of the control node, the noise injection node, and the path;
And a noise tolerance determination unit that determines noise tolerance of the semiconductor integrated circuit from the minimum value of the impedance in the list.

  Thus, the noise resistance evaluation method for a semiconductor integrated circuit according to claim 1 can be carried out.

  The noise tolerance evaluation apparatus according to claim 20, further comprising a parasitic element extraction unit that extracts a parasitic element from the layout information based on layout information obtained from a layout diagram of the semiconductor integrated circuit, The circuit net list creation unit creates the circuit net list including the parasitic elements.

  Thus, the noise resistance evaluation method for a semiconductor integrated circuit according to claim 2 can be carried out.

Moreover, noise immunity evaluation apparatus according to claim 21, for the combination of the previous SL noise immunity determination unit without noise immunity been judged with the control node the noise injection node, based on the noise countermeasure circuit constraint information, A noise countermeasure circuit creating unit is provided that inserts a noise countermeasure element having a predetermined impedance between the control node and an AC ground node that is set to 0 potential in an alternating manner.

  Thus, the noise tolerance evaluation method for a semiconductor integrated circuit according to claim 15 can be carried out.

  The effects obtained by the noise immunity evaluation method for a semiconductor integrated circuit implemented using the noise immunity evaluation apparatus according to claims 19 to 21 are as described above, and a description thereof is omitted.

1 is a flowchart showing a basic configuration of a noise immunity evaluation method for a semiconductor integrated circuit according to the present invention and an outline of a noise immunity evaluation method 100. FIG. It is an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation method 100 of the semiconductor integrated circuit shown in FIG. In the example of the circuit diagram, the circuit diagram of the comparator circuit 10 of a simple analog circuit is illustrated. It is the figure which illustrated a part of circuit net list. FIG. 5 is a diagram illustrating connection information of each device, taking as an example a portion surrounded by a one-dot chain line in FIG. 4. It is the figure which showed an example of replacement | exchange to the passive element circuit equivalent to a high frequency from an active element, (a) is a passive element of resistance, impedance, and capacity | capacitance, and is not replaced. (B) to (c) are active element diodes, MOS transistors, and bipolar transistors, respectively. FIG. 7 is a diagram specifically explaining replacement of a MOS transistor with a passive element in consideration of device characteristics, where (a) is a diagram showing a relationship between a gate voltage Vg and a drain current Id of the MOS transistor, and (b) is a diagram. FIG. 5 is a diagram showing the relationship between the drain potential Vd of the MOS transistor and the drain current Id. FIG. 13B is a replacement circuit diagram 13a in which the active element of the comparator circuit 10 shown in FIG. 3 is replaced with a passive element circuit equivalent in terms of high frequency based on the replacement example of the active element shown in FIG. It is the detailed flow 20 which showed the process performed in 3rd step S13-6th step S16 shown in FIG. 1 in detail about the case where impedance is calculated for every line path | route. FIG. 13B is a diagram illustrating two line paths L1 and L2 indicated by broken lines with respect to the control node T7 and the noise injection node P1 in the replacement circuit diagram 13a of FIG. In the case of calculating the combined impedance of the net path, it is a detailed flow 30 showing in more detail the processing performed in the third step S13 to the sixth step S16 shown in FIG. It is a figure explaining the mode of propagation of noise by a net route. It is a figure explaining the mode of calculation of the synthetic impedance by a circuit simulator or a hardware description language. It is a figure explaining the case where 0 electric potential is set to a power supply node and a ground (GND) node. FIG. 9 is a flowchart showing an outline of a noise tolerance evaluation method 101 as a modification of the noise tolerance evaluation method 100 shown in FIG. 1. FIG. 16 shows an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation method 101 for the semiconductor integrated circuit shown in FIG. In the example of the layout diagram, a simple layout diagram of the CMOS circuit 40 is illustrated for easy understanding. FIG. 2 is a schematic cross-sectional view of a semiconductor integrated circuit 50, illustrating various parasitic elements and noise propagation paths resulting from the layout and structure of each element constituting the semiconductor integrated circuit 50. 3 is a circuit diagram illustrating a part of a logic circuit 60. FIG. FIG. 9 is a flowchart showing an outline of a noise tolerance evaluation method 102 as a modification of the noise tolerance evaluation method 100 shown in FIG. 1. It is the figure which showed collectively whether the frequency dependence of the impedance of a noise propagation path | route and whether this noise propagation path | route is capacitive, resistive, or inductive. FIG. 21 is a flowchart showing an outline of a noise tolerance evaluation method 102a as a modification of the noise tolerance evaluation method 102 shown in FIG. 20. FIG. 21 is a flowchart showing an outline of a noise tolerance evaluation method 102b as a modification of the noise tolerance evaluation method 102 shown in FIG. 20. 24 is a diagram showing a configuration of a noise tolerance evaluation apparatus 202 as an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation methods 102a and 102b of the semiconductor integrated circuit shown in FIGS. 22 and 23. FIG. It is a figure which shows the outline of the noise countermeasure with respect to the control node determined with noise tolerance evaluation method 100-102,102a, 102b without noise tolerance, (a) is a structure before noise countermeasure, (b) is after noise countermeasure. It is the composition. It is a figure which shows the example of the more detailed noise countermeasure which considered the characteristic of the noise propagation path, (a) is a structure about the case of a capacitive propagation path, (b) is the structure of a resistive or inductive propagation path. It is the structure about the case. (A) is the figure which showed the case where there exists injection | pouring of the external noise via the circuit structure of a band gap low voltage circuit (BG circuit) and parasitic capacitance Ca, (b) is control node Ta and AC ground node It is the figure which showed the circuit structure at the time of inserting noise countermeasure capacity | capacitance C3 between Ga. FIG. 4 is a circuit diagram of a comparator circuit 10a in which a circuit similar to the comparator circuit 10 shown in FIG. 3 is composed of bipolar transistors. It is the flowchart which showed the outline of the conventional noise tolerance evaluation method 90. FIG. FIG. 30 is a flowchart showing an outline of a conventional noise tolerance evaluation method 91, which is a more precise noise tolerance evaluation method 90 of FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a basic configuration of a noise tolerance evaluation method for a semiconductor integrated circuit according to the present invention, and is a flowchart showing an outline of a noise tolerance evaluation method 100. In addition, in each processing step in the noise immunity evaluation method 100 of FIG. 1, the same reference numerals are given to those performing the same processing as the processing steps in the conventional noise immunity evaluation method 90 shown in FIG.

  FIG. 2 is an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation method 100 of the semiconductor integrated circuit shown in FIG.

  The noise immunity evaluation method 100 for a semiconductor integrated circuit shown in FIG. 1 includes a first step S11 for creating a circuit netlist from the circuit diagram of the semiconductor integrated circuit designed in step S1, and active elements in the circuit netlist. A second step S12 for generating a replacement circuit netlist by replacing with a passive element circuit equivalent to a high frequency, and a control node corresponding to the control terminal of the transistor before replacement is extracted from the replacement circuit netlist. Step S13 in Step 3 and a fourth step S14 in which a predetermined node is selected from the replacement circuit net list and a noise injection node is set, and noise of a predetermined frequency is set and is different from each other in the replacement circuit net list. A fifth step for calculating the impedance of the path between the control node and the noise injection node. S15, sixth step S16 for creating a list of the impedances in each combination of the control node, the noise injection node, and the path, and the noise tolerance of the semiconductor integrated circuit from the minimum value of the impedances in the list. And a seventh step S17 for determination.

  If it is determined in the seventh step S17 that there is no noise tolerance, the process returns to step S1, the circuit diagram is corrected, and each process after the first step S11 is repeated. If it is determined in the seventh step S17 that there is noise tolerance, the process proceeds to step S4, and the noise tolerance evaluation of the semiconductor integrated circuit is completed.

  2 is a noise tolerance evaluation apparatus for a semiconductor integrated circuit that implements the noise tolerance evaluation method 100 shown in FIG. 1, and is obtained from the circuit diagram of the semiconductor integrated circuit. The circuit netlist creation unit M11 that creates the circuit netlist on the basis of the circuit information M1 and the replacement information M2 from the active element to the passive element circuit, the active element in the circuit netlist is changed to a high frequency. A replacement circuit netlist creation unit M12 that creates the replacement circuit netlist by replacing the passive node circuit with a substantially equivalent passive element circuit, and the control node corresponding to the control terminal of the transistor before replacement from the replacement circuit netlist. A control node extracting unit M13 for extracting and a predetermined node from the replacement circuit net list are selected, and the noise injection node is selected. In the noise injection node setting unit M14 for setting the noise, the noise frequency setting unit M15a for setting the noise of the predetermined frequency, and the impedance of the path between the control node and the noise injection node which are different from each other in the replacement circuit netlist A path impedance calculation unit M15b that calculates the impedance, an impedance list creation unit M16 that creates a list of the impedances in each combination of the control node, the noise injection node, and the path, and a minimum value of the impedance in the list, And a noise tolerance determination unit M17 for determining the noise tolerance of the semiconductor integrated circuit.

  Thereby, the noise tolerance evaluation method 100 of the semiconductor integrated circuit shown in FIG. 1 can be implemented.

  A noise tolerance evaluation method 100 for a semiconductor integrated circuit shown in FIG. 1 is a novel noise tolerance evaluation method that replaces the conventional noise tolerance evaluation method 90 shown in FIG. In the noise tolerance evaluation method 100 of FIG. 1, by analyzing the noise propagation path and the impedance of the path, the noise of each transistor constituting the semiconductor integrated circuit is basically used without using a circuit simulator (SPICE). It is possible to easily evaluate the possibility of malfunctions due to. The purpose of the noise tolerance evaluation method 100 shown in FIG. 1 is to analyze the impedance of a noise propagation path and extract a control node through which noise easily propagates. The control node is, for example, a base or a gate in the case of a device of a bipolar transistor or a MOS transistor, and an input terminal having a high sensitivity in a circuit block level of an amplifier or a comparator. In the semiconductor integrated circuit noise resistance evaluation method 100 shown in FIG. 1, the plurality of control nodes are picked up and the ease of noise propagation is ranked for the plurality of picked-up control nodes.

  Next, in the noise tolerance evaluation method 100 of FIG. 1, each process performed in the first step S11 to the seventh step S17 will be described in detail with reference to a specific example.

  The first step S11 in the noise tolerance evaluation method 100 of FIG. 1 is a step of creating a circuit netlist from the circuit diagram of the semiconductor integrated circuit.

  FIG. 3 is an example of a circuit diagram, and illustrates a circuit diagram of a simple analog circuit comparator circuit 10 for easy understanding of the following description. As illustrated in FIG. 3, in the “circuit diagram”, connection of a device such as a transistor as an active element and a resistor or a capacitor as a passive element is shown. 1 is applicable not only to analog circuits but also to digital circuits such as logic circuits. In addition, the semiconductor integrated circuit actually evaluated by the noise tolerance evaluation method 100 of FIG. 1 is a large-scale LSI. Therefore, the circuit diagram handled by the noise tolerance evaluation method 100 in FIG. 1 is not a simple circuit diagram as in FIG. 3, but a large-scale circuit diagram in which analog circuits and digital circuits are combined.

  FIG. 4 is a diagram illustrating a part of the circuit netlist. FIG. 5 is a diagram for explaining the connection information of each device, taking as an example the part surrounded by the one-dot chain line in FIG.

  The circuit netlist created in the first step S11 of FIG. 1 is text data generated from a circuit diagram (hereinafter also referred to as “circuit diagram data”), which is circuit topology information of a semiconductor integrated circuit to be evaluated, that is, The connection information of each device constituting the semiconductor integrated circuit is described. The creation of a circuit netlist in the first step S11 of FIG. 1 is a basic step in the case of performing a simulation. For example, a circuit simulator (SPICE) like the conventional noise tolerance evaluation method 90 shown in FIG. This is also the first step in the noise tolerance evaluation method using.

  Next, in the second step S12 in the noise tolerance evaluation method 100 of FIG. 1, the active element in the circuit net list created in the first step S11 is replaced with a passive element circuit equivalent in terms of high frequency, so that a replacement circuit net is obtained. Create a list.

  FIG. 6 is a diagram showing an example of replacement of the active element with a high-frequency equivalent passive element circuit.

  FIG. 6A shows passive elements of resistance, inductance, and capacitance, and the above replacement is not performed. The impedance of the resistor does not depend on the frequency ω of the high frequency (noise), but the impedance of the inductance and the capacitance depends on the frequency ω as shown in parentheses of the symbol. It should be noted that the impedance of the capacitor used to replace the diode, MOS transistor, and bipolar transistor shown in FIGS. 6B to 6D shown below also depends on the frequency ω of the high frequency (noise). In the circuit net list (replacement circuit net list), after the frequency region is defined by | Z | = | R + jωL + 1 / (jωC) |, the resistor is designated as through and the + R value is added. Inductance is designated as through and the + L value is added. The capacity is specified as “through”, and the + C value is added.

  FIG. 6B shows a diode as an active element. The diode is replaced in different ways depending on the direction of noise propagation. The forward direction is replaced with zero resistance and the reverse direction is replaced with a capacitor. The replacement from a diode to a passive element circuit equivalent to a high frequency is illustrated by a symbol surrounded by a square and an arrow indicating a propagation direction, as indicated by a white arrow on the right side of the table. In the replacement circuit netlist, for example, the forward direction of the diode is designated as through and no value is added. The reverse direction of the diode is designated as through, and the capacitance (+ Cj) value is added. In general, since the value of the capacitance (+ Cj) is small, the reverse direction may be specified without propagating.

  FIG. 6C shows an active element MOS transistor. In the MOS transistor, the source-drain is replaced with a resistor, and the gate-drain and the gate-source are replaced with a capacitor. In the MOS transistor, there is no dependency on the noise propagation direction. In the replacement circuit netlist, for example, between the drain (D) and the source (S) of the MOS transistor is designated as through, and an on-resistance (+ R_ON) value is added. The gate (G) -drain (D) and the gate (G) -source (S) of the MOS transistor are designated as through, and the capacitance (+ Cgd) value and the capacitance (+ Cgs) value are added. Further, not limited to the replacement of FIG. 6C, for example, the D → S direction is designated as through and the value is not added, and the S → D direction is designated as through and the on-resistance (+ R_ON) value is added. , G → D and G → S may be specified without propagation.

  FIG. 6D shows a bipolar transistor as an active element. In bipolar, the emitter-collector is replaced with a resistor, and the base-collector is replaced with a capacitor. The method of replacement between the base and the emitter of the bipolar transistor is different depending on the direction of noise propagation. The base to emitter direction is replaced with zero resistance, and the emitter to base direction is replaced with capacitance. In the replacement circuit netlist, for example, the base (B) → emitter (E) direction of the bipolar transistor is designated as through and no value is added. The reverse emitter (E) → base (B) direction is designated as through, and the capacitance (+ Cbe) value is added. Between the collector (C) and the emitter (E) of the bipolar transistor is designated as through, and an on-resistance (+ R_ON) value is added. Between the base (B) and the collector (C) is designated as through, and the capacitance (+ Cbc) value is added. In addition, not limited to the replacement in FIG. 6D, for example, the B → E direction is designated as through and no value is added, and between E and C, through is designated as on resistance (+ R_ON) value. In addition, the B → C direction may be designated as not propagating, and the C → B direction may be designated as through and the on-resistance (+ R_ON) value may be added.

  In a MOS transistor or a bipolar transistor, the difference between the on state and the off state, the on resistance, the junction capacitance, and the like differ depending on the operating point. Therefore, the MOS transistor and the bipolar transistor are appropriately selected and replaced with the passive element circuit. Note that the rules for replacing active elements with passive elements are not limited to those described above. For example, a SPICE simulation is performed in advance in a normal state without noise to monitor the operating point of each node, and information on the monitored operating point is prepared in advance, describing the relationship between operating point-resistance and operating point-capacitance. The resistance value and the capacitance value corresponding to each operating point may be uniquely selected by a method of checking against the table.

  FIG. 7 is a diagram specifically explaining replacement of a MOS transistor with a passive element in consideration of device characteristics. FIG. 7A is a diagram showing the relationship between the gate voltage Vg of the MOS transistor and the drain current Id using the substrate potential Vb as a parameter. FIG. 7B is a diagram showing the relationship between the gate voltage Vg and the MOS transistor. It is the figure which showed the relationship between the drain electric potential Vd and the drain current Id.

  For example, in the MOS transistor at the operating point M shown in FIG. 7B, the ON resistance Rds = 3.5 [V] /6.3 [A] = 0.56 between the drain (D) and the source (S). Replace with [Ω].

  In the case of a MOS transistor, it is possible to more accurately replace the current value with the impedance from each operating point of the source (S), drain (D), and gate (G) using circuit simulation. If circuit simulation is performed using the circuit diagram netlist described above, the operating points of each node at the stable point can be listed as “operating point data”. By inputting this operating point data, it is possible to define the impedance corresponding to each operating point read from the device characteristic data. In addition, the parasitic capacitance between the gate (G) and the drain (D) and between the gate (G) and the source (S) is given by the transistor parameter of the circuit simulation, and this can also be replaced with the impedance.

  "Circuit diagram data (circuit netlist)", "Operating point data (regulation of bias points of each node and each transistor at a certain time)", "Device characteristic data (operating point obtained by setting the noise frequency) By combining “impedance values of transistors corresponding to data)”, an “impedance check” to be described later can be performed in an equivalent circuit including only passive elements not including active elements.

  8 is a replacement circuit diagram 13a in which the active elements of the comparator circuit 10 shown in FIG. 3 are replaced with high-frequency equivalent passive element circuits based on the active element replacement example shown in FIG. .

  Therefore, the replacement circuit net list created in the second step S12 in the noise tolerance evaluation method 100 of FIG. 1 will be described with reference to the example of the comparator circuit 10 of FIG. It is a list. Specifically, for the circuit netlist of the comparator circuit 10 shown in FIG. 3 as shown in FIG. 4, the active elements in the circuit netlist are replaced with the active element replacement table shown in FIG. Then, a “replacement circuit netlist” is created in which the passive element circuit is replaced with a high frequency equivalent. Therefore, in the replacement circuit netlist, the semiconductor integrated circuit to be evaluated is described as a passive element integrated circuit composed of all passive elements, and connection information of all the passive elements is described.

  Next, in the third step S13 in the noise tolerance evaluation method 100 of FIG. 1, a control node corresponding to the control terminal of the transistor before replacement is extracted from the replacement circuit netlist created in the second step S12. The control node may be extracted in advance at the stage of the circuit diagram of the semiconductor integrated circuit in step S1 of FIG. 1 or at the stage of creating the circuit netlist in the first step S11. The control terminal of the transistor described above is a base terminal if it is a bipolar transistor, and a gate terminal if it is a MOS transistor. In the example of the comparator circuit 10 in FIG. 3 and the replacement circuit diagram 13a in FIG. 8, control nodes T1 to T8 are shown. The extraction of the control nodes in the third step S13 may extract all the control nodes in the replacement circuit netlist. For example, a malfunction that handles a high amplification factor, a minute current, and a minute voltage is likely to occur. Some control nodes that are considered to be extracted may be extracted.

  In the fourth step S14 in the noise tolerance evaluation method 100 of FIG. 1, a predetermined node is selected from the replacement circuit net list created in the second step, and a noise injection node is set. The noise injection node may be set in advance at the stage of the circuit diagram of the semiconductor integrated circuit in step S1 in FIG. 1 or at the stage of creating the circuit netlist in the first step S11. In the example of the comparator circuit 10 in FIG. 3 and the replacement circuit diagram 13a in FIG. 8, noise injection nodes P1 to P4 are shown. In the fourth step S14, for example, if the noise injection node is set only for the node corresponding to the external terminal, the noise resistance of the semiconductor integrated circuit against the external noise is evaluated. On the other hand, if noise injection nodes are set only for some of the nodes corresponding to the transistors before replacement, which are likely to generate noise, such as oscillation circuits and clock generation circuits, the noise resistance of the semiconductor integrated circuit against internal noise Will be evaluated. Needless to say, noise injection nodes may be set for all nodes in the replacement circuit netlist.

  Next, in a fifth step S15 in the noise tolerance evaluation method 100 of FIG. 1, noise having a predetermined frequency is set, and in the replacement circuit netlist created in the second step S12, the control node and the noise injection different from each other are set. Calculate the impedance of the path between nodes. The noise frequency may be set at any step as long as it is a stage prior to the fifth step S15 in FIG.

  In the next sixth step S16, the impedance calculation results for each combination of the control node, the noise injection node, and the path are integrated to create an impedance list.

  Finally, in the seventh step S17 in the noise tolerance evaluation method 100 of FIG. 1, the noise tolerance of the semiconductor integrated circuit is determined from the minimum impedance value in the list. That is, if the minimum impedance value in the list is smaller than a predetermined reference value, it is determined that there is no noise tolerance, and the process returns to step S1 to correct the circuit diagram of the semiconductor integrated circuit. Then, the first step S11 to the seventh step S17 described above are repeated for the corrected circuit diagram, and the noise resistance evaluation is continued. Finally, when the minimum impedance value in the list created in the sixth step S16 becomes larger than the predetermined reference value in the seventh step S17, it is determined that there is noise tolerance, and the process proceeds to step S4. Then, the noise tolerance evaluation of the semiconductor integrated circuit is completed.

  As described above, the noise tolerance evaluation method 100 of the semiconductor integrated circuit shown in FIG. 1 evaluates the noise tolerance of the semiconductor integrated circuit by analyzing the noise propagation path and the impedance of the path. Unlike the conventional noise tolerance evaluation method 90 shown, circuit simulation using a circuit simulator (SPICE) is not performed. For this reason, it is not necessary to perform a large-scale analysis unlike the noise tolerance evaluation method based on the conventional circuit simulation, and it is possible to efficiently evaluate the noise tolerance within a limited design period.

  Next, the impedance calculation in the fifth step S15 in the noise tolerance evaluation method 100 described above will be described in more detail.

  The calculation of the impedance in the fifth step S15 may calculate the impedance for each line path, as shown below, for the control node and the noise injection node which are different from each other, or as the combined impedance of the net path. You may make it do.

  FIG. 9 is a detailed flow 20 showing in more detail the processing performed in the third step S13 to the sixth step S16 shown in FIG. 1 when the impedance is calculated for each line path.

In the detailed flow 20 shown in FIG. 9, A control nodes (T _a ) are extracted in step S13a corresponding to the third step S13 in FIG. Next, in step S14a corresponding to the fourth step S14 in FIG. 1, B noise injection nodes (P _b ) are set. Next, in step S15a, C line paths (L _c ) are extracted for the specific control node (T _a ) and the noise injection node (P _b ).

When extracting the line path (L _c ), the noise propagation path should not be looped. In addition, a condition that the same node or the same element does not pass twice or more may be given.

  FIG. 10 is a diagram illustrating two line paths L1 and L2 indicated by broken lines with respect to the control node T7 and the noise injection node P1 in the replacement circuit diagram 13a of FIG.

In step S15b in the detailed flow 20 of FIG. 9, the noise (high frequency) of the frequency (ω) is set, and the impedance of the line path (L _c ) is calculated. In FIG. 10, impedances Z1 and Z2 of the line paths L1 and L2 are illustrated as Z1 = (R11) + 1 / jω (C11) and Z2 = (R21) + (R22) + (R23), respectively. The impedance of elements connected in parallel may be degenerated.

When the impedance calculation in step S15b is completed for one line path, the process proceeds to steps S15c and S15d, and the impedance calculation in step S15b is repeated while changing the line path, and a specific control node (T _a ) and noise injection node ( Impedance values of all (C lines) of the extracted line paths for P _b ) are calculated.

When a series of processing from step S15a to step S15d is completed for the specific control node (T _a ) and noise injection node (P _b ), the process proceeds to steps S15e and S15f, and the noise injection node (P _b ) is changed. However, the series of processing from step S15a to step S15d is repeated. Then, the impedance values of the extracted line paths are calculated for all (B) noise injection nodes (P _b ) set as the specific control node (T _a ).

Similarly, when a series of processing from step S14a to step S15f is completed for a specific control node (T _a ), the process proceeds to steps S15g and S15h, and the control node (T _a ) is changed, and steps S14a to S15 are performed. The series of processes in S15f is repeated. Then, the impedance values of the extracted line paths are calculated for all (A) extracted control nodes (T _a ) and all (B) set noise injection nodes (P _b ).

  When the above series of processing ends, the process proceeds to step S16a, and a list of impedance values for all the calculated line paths is created.

  As described above, in the detailed flow 20 shown in FIG. 9, the impedance of the line path between the control node and the noise injection node is calculated in the fifth step S15 in the noise tolerance evaluation method 100 of FIG. In step S16, a list of impedances in each combination of the control node, the noise injection node, and the line path is created.

When calculating impedance for each line path as in the detailed flow 20 shown in FIG. 9, even if a list of impedance values for all line paths existing in the replacement circuit netlist (semiconductor integrated circuit) is created. Good. However, the method for calculating the impedance for each line path described above is performed when the line path where noise easily propagates between the specific control node and the noise injection node or the line path where noise hardly propagates can be specified to some extent. Since the line path (L _c ) extracted in S15a can be narrowed down, it is particularly suitable.

  Next, the case where the impedance calculation in the fifth step S15 in the noise tolerance evaluation method 100 of FIG. 1 is calculated as the combined impedance of the net path for different control nodes and noise injection nodes will be described.

  FIG. 11 is a detailed flow 30 showing in more detail the processing performed in the third step S13 to the sixth step S16 shown in FIG. 1 when calculating the combined impedance of the net path. In addition, in the detailed flow 30 shown in FIG. 11, the same code | symbol was attached | subjected about the process step similar to the detailed flow 20 shown in FIG.

In the detailed flow 30 shown in FIG. 11, A control nodes (T _a ) are extracted in step S13a corresponding to the third step S13 in FIG. Next, in step S14a corresponding to the fourth step S14 in FIG. 1, B noise injection nodes (P _b ) are set.

  Steps S13a and S14a are the same as those in the detailed flow 20 shown in FIG.

On the other hand, in the detailed flow 20 shown in FIG. 9, C line paths (L _c ) are extracted from the specific control node (T _a ) and the noise injection node (P _b ) in step S15a, and in step S15b. The impedance of each line path (L _c ) was calculated. On the other hand, in the detailed flow 30 shown in FIG. 11, in step S15i, noise (high frequency) of frequency (ω) is set, and a specific control node (T _a ) and noise injection node (P _b ) are set. Calculate the net path combined impedance. That is, in the detailed flow 30 shown in FIG. 11, the individual line paths (L _c ) of the specific control node (T _a ) and the noise injection node (P _b ) as in the detailed flow 20 shown in FIG. Rather than calculating the impedance, the entire propagation path of noise is regarded as a net path connecting from the control node (T _a ) to the noise injection node (P _b ), and the combined impedance is calculated.

  FIG. 12 is a diagram for explaining how noise propagates through the net path.

  FIG. 12 shows how the noise injected into the noise injection node P1 in the replacement circuit diagram 13a of FIG. 8 flows out in each direction of the net path as indicated by the broken arrow and reaches the control node T7 from each direction. This is shown schematically.

The processing steps after step S15e in the detailed flow 30 of FIG. 11 are the same as those of the detailed flow 20 of FIG. That is, in the detailed flow 30 of FIG. 11, when the process of step S15i for the specific control node (T _a ) and the noise injection node (P _b ) is completed, the process proceeds to steps S15e and S15f, and the noise injection node ( The process of step S15i is repeated while changing P _b ). Then, a combined impedance value is calculated for all (B) noise injection nodes (P _b ) set as the specific control node (T _a ).

Similarly, in the detailed flow 30 of FIG. 11, when _a series of processes in steps S14a to S15f for _a specific control node (T _a ) is completed, the process proceeds to steps S15g and S15h, and the control node (T _a ) A series of processes in step S14a to step S15f are repeated while changing. Then, the combined impedance value of each net path is calculated for all (A) extracted control nodes (T _a ) and all (B) set noise injection nodes (P _b ).

  When the above series of processing ends, the process proceeds to step S16b, and a list of combined impedance values for all calculated net paths is created.

  As described above, in the detailed flow 30 shown in FIG. 11, the combined impedance of the net path between the control node and the noise injection node is calculated in the fifth step S15 in the noise tolerance evaluation method 100 of FIG. In step S16, a list of combined impedances in each combination of the control node and the noise injection node is created.

  According to the method of calculating the net impedance of the net path between the control node and the noise injection node as in the detailed flow 30 shown in FIG. 11, the control node and the noise injection node are as shown in the detailed flow 20 of FIG. Compared with the method of calculating the impedance of the line path, the noise that is distributed and propagated to each line path in the net path between the control node and the noise injection node is actually reflected more faithfully. For this reason, more accurate noise tolerance evaluation is possible.

  The combined impedance in step S15i of the detailed flow 30 in FIG. 11 can be directly calculated by synthesizing the impedance of each passive element in the net path from the replacement circuit netlist created in the second step S12 in FIG. it can. On the other hand, using a hardware description language such as a circuit simulator, Verilog-AMS (Analog & Mixed Signal), or VHDL-AMS, a predetermined AC potential difference or AC current is given to the control node and the noise injection node, and the control node and noise It is possible to easily calculate from the total current flowing between the injection nodes or the potential difference between the nodes, which makes it easier to create a list of combined impedances.

  FIG. 13 is a diagram for explaining how the synthetic impedance is calculated by the circuit simulator and the hardware description language.

  FIG. 13 is a circuit diagram of the replacement circuit 13a of FIG. 8. The potentials Vp and Vt are respectively applied to the noise injection node P1 and the control node T7. The total current I is indicated by a solid line. By calculating the total current I using a circuit simulator (SPICE) or a hardware description language, the combined impedance Z (= R) between the noise injection node P1 and the control node T7 can be calculated as R = (Vp−Vt) / I can be obtained easily from I. FIG. 13 shows a method in which a predetermined AC potential difference is given to the control node and the noise injection node, and the combined impedance is calculated from the total current flowing between the control node and the noise injection node. However, the present invention is not limited to this, and a predetermined alternating current may be given to the control node and the noise injection node, and the combined impedance may be calculated from the potential difference between the nodes.

  There is the following difference between the method using the circuit simulator and the method using a hardware description language. In the method using the circuit simulator, it is impossible to identify and handle the noise propagation direction for one noise propagation path. Therefore, in the method using the circuit simulator, when the diode is replaced with, for example, a passive element in the second step S12 of FIG. 1, either the forward noise propagation or the reverse noise propagation shown in FIG. It is necessary to select and replace. Similarly, the replacement between the base and emitter of the bipolar transistor shown in FIG. On the other hand, in a method using a hardware description language such as Verilog-AMS, it is possible to identify and handle the noise propagation direction for one noise propagation path. For this reason, the method using the hardware description language can perform more accurate noise tolerance evaluation than the method using the circuit simulator.

  As described above, the impedance calculation of the line path shown in FIG. 9 or the net path shown in FIG. 11 is performed in the fifth step S15 in the noise tolerance evaluation method 100 of FIG. 1, and the sixth step S16 of FIG. If the impedance list of the line path or the combined impedance list of the net path is created, the noise tolerance can be determined in the next seventh step S17.

  As described above, in the noise immunity evaluation method 100 for a semiconductor integrated circuit shown in FIG. 1, in the third step S13, all control nodes are extracted from the replacement circuit netlist created in the second step S12. Thus, it is possible to evaluate the noise resistance of all the transistors present in the semiconductor integrated circuit. Further, in the third step S13, a predetermined control node is selected and extracted from the replacement circuit net list created in the second step S12. For example, the amplification factor among the transistors existing in the semiconductor integrated circuit is A transistor that is considered to be high and likely to cause malfunction may be selected to evaluate noise resistance.

  In the noise immunity evaluation method 100 for a semiconductor integrated circuit shown in FIG. 1, in a fourth step S14, all nodes are selected from the replacement circuit netlist created in the second step S12, and a noise injection node is set. can do. According to this, it is possible to evaluate noise resistance for both external noise propagating from an external terminal of the semiconductor integrated circuit and internal noise generated by a specific transistor in the semiconductor integrated circuit. If there is no possibility of malfunction due to internal noise, in the fourth step S14, the node of the external terminal is selected from the replacement circuit net list created in the second step S12, and noise injection is performed. A node may be set. According to this, it is possible to evaluate the noise resistance of only the external noise propagating from the external terminal of the semiconductor integrated circuit.

  Also, in the semiconductor integrated circuit noise tolerance evaluation method 100 shown in FIG. 1, the ground (GND) node and the power supply node of the replacement circuit netlist created in the second step S12 are set to 0 potential in an alternating manner. Alternatively, an AC ground node may be used.

  The above-described GND node and power supply node are, for example, a GND terminal or a power supply terminal of an IC terminal, and when these IC terminals have a low impedance outside the IC, an AC ground node that can be set to 0 potential in an alternating manner. It can be. The AC ground node is not limited to the GND node and the power supply node, but may be the following node. For example, this is a case where a GND terminal and a power supply terminal in each circuit block in the IC are directly connected to the outside of the IC via the IC terminal, and these IC terminals have a low impedance outside the IC. In addition, other IC terminals to which a large-capacitance capacitor (several μF or more) is added externally, terminals of each circuit block, or Si substrate node when the silicon (Si) substrate is securely grounded (GND) May be an AC ground node. Note that each of the nodes described above can be individually an AC ground node, or all nodes can be AC ground nodes.

  As described above, the fifth step S15 is performed after applying a 0V potential to a node having low circuit impedance such as a GND node or a power supply node to form an AC ground node.

  FIG. 14 is a diagram illustrating a case where 0 potential is set to the power supply node and the GND node. FIG. 14 shows that the power supply line and the ground (GND) line are AC-grounded in the replacement circuit diagram 13a of FIG. 8 so that both the power supply node and the GND node become AC ground nodes set to zero potential.

  According to this, the noise propagation path evaluated in the fifth step S15 in the noise tolerance evaluation method 100 of FIG. 1, that is, steps S15a to S15d in the detailed flow 20 of FIG. 9 or step S15i in the detailed flow 30 of FIG. Since the number can be reduced, the impedance can be easily calculated in the fifth step S15 of FIG.

  FIG. 15 is a flowchart showing an outline of the noise tolerance evaluation method 101 as a modification of the noise tolerance evaluation method 100 shown in FIG. In addition, in each processing step in the noise tolerance evaluation method 101 of FIG. 15, the same reference numerals are given to those performing the same processing as the processing steps in the noise tolerance evaluation method 100 shown in FIG.

  FIG. 16 is an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation method 101 of the semiconductor integrated circuit shown in FIG. 15, and is a diagram showing the configuration of the noise tolerance evaluation apparatus 201. In addition, in the noise tolerance evaluation apparatus 201 shown in FIG. 16, the same code | symbol was attached | subjected about the part similar to the noise tolerance evaluation apparatus 200 shown in FIG.

  The noise immunity evaluation method 101 of the semiconductor integrated circuit shown in FIG. 15 is different from the noise immunity evaluation method 100 shown in FIG. 1 in that the layout diagram shown in step S1a and the parasitic element extraction process are the same as those in step S1. It has been added later. That is, the noise tolerance evaluation method 101 shown in FIG. 15 incorporates layout information of each element constituting the semiconductor integrated circuit with respect to the noise tolerance evaluation method 100 shown in FIG. This is a noise tolerance evaluation method. Accordingly, the circuit netlist created in the first step S11 of FIG. 15 not only describes connection information of each element constituting the semiconductor integrated circuit, but also occurs due to the layout of each element. The connection information of each parasitic element is also described.

  As described above, the noise immunity evaluation method 100 for a semiconductor integrated circuit shown in FIG. 1 can evaluate noise immunity in a short time. From this, as in the noise immunity evaluation method 101 of the semiconductor integrated circuit shown in FIG. 15, a layout diagram of the semiconductor integrated circuit is created in step S1a, and parasitic elements are extracted from the layout diagram, and the first step S11. Preferably, a circuit netlist including the parasitic elements is created. As a result, the noise tolerance evaluation is performed on the propagation path of the high-frequency signal (noise) including the parasitic element, and the noise tolerance of the semiconductor integrated circuit can be more accurately evaluated.

  A noise tolerance evaluation apparatus 201 for a semiconductor integrated circuit shown in FIG. 16 is a noise tolerance evaluation apparatus for a semiconductor integrated circuit that implements the noise tolerance evaluation method 101 shown in FIG. 15, and the noise tolerance evaluation apparatus 200 shown in FIG. In addition to the above configuration, a parasitic element extraction unit M1ab for extracting a parasitic element from the layout information M1aa based on the layout information M1aa obtained from the layout diagram of the semiconductor integrated circuit is provided, and a circuit netlist is created. In the part M11, the circuit netlist including the parasitic elements is created.

  Thereby, the noise tolerance evaluation method 101 of the semiconductor integrated circuit shown in FIG. 15 can be implemented.

  FIG. 17 is an example of a layout diagram and illustrates a simple layout diagram of the CMOS circuit 40 for easy understanding. FIG. 18 is a schematic cross-sectional view of the semiconductor integrated circuit 50, illustrating various parasitic elements and noise propagation paths resulting from the layout and structure of each element constituting the semiconductor integrated circuit 50. is there.

  In the layout diagram of the CMOS circuit 40 shown in FIG. 17, the coating pattern is applied to the P substrate 41, the N well 42, the P + region 43, the N + region 44, the polysilicon layer 45, the first aluminum layer 46, and the second aluminum layer 47, respectively. They are shown in a superimposed manner. In addition, the crosses enclosed by double squares indicate the positions of the contacts to the diffusion regions and the via holes connecting the layers.

  Even in the small CMOS circuit 40 shown in FIG. 17, there are a large number of parasitic elements, which serve as propagation paths for high-frequency signals (noise). For example, a parasitic capacitance between wiring and wiring, a parasitic capacitance between wiring and a silicon substrate, a parasitic resistance of wiring, a parasitic capacitance and a parasitic resistance between devices in a silicon substrate. When an SOI structure substrate having a buried oxide film is used, the capacitance of the buried oxide film, the trench capacity in the trench isolation structure, and the like are also parasitic elements.

  For example, in the semiconductor integrated circuit 50 shown in FIG. 18, a substrate having an SOI structure including a support substrate 51, a buried oxide film 52, and an SOI layer 53 is used. Each element of the power transistor Tr 1, the CMOS transistor Tr 2, and the bipolar transistor Tr 3 is surrounded by the insulating isolation trench 54 and formed in the SOI layer 53 by trench isolation (TD) technology. On the SOI layer 53, a thin film resistor Rf capable of on-chip adjustment for increasing the accuracy of the analog circuit is formed via an interlayer insulating film 56. The structure of the semiconductor integrated circuit 50 in which various elements shown in FIG. 18 are integrated is suitable as a structure of an automotive IC that requires compatibility with multiple power supplies, stable operation at high temperatures, and compatibility between high breakdown voltage and high integration. It is also strong against negative input surges specific to automobiles, and it is possible to realize latch-up free.

  On the other hand, in the structure of the semiconductor integrated circuit 50 in which various elements shown in FIG. 18 are integrated, many parasitic elements are generated. Therefore, it is necessary to evaluate the influence of these parasitic elements. In FIG. 18, as the parasitic capacitance, an oxide film capacitance of the buried oxide film 52, a trench capacitance of the insulating isolation trench 54, a wiring capacitance between the wirings 55, and the like are illustrated. Examples of the parasitic resistance include the substrate resistance of the support substrate 51 and the SOI layer 53 made of silicon (Si), and the wiring resistance of the wiring 55 made of aluminum (Al) or the like. Further, as the parasitic inductance, the wiring inductance of the wiring 55 is illustrated.

  In addition, as a noise propagation path, FIG. 18 illustrates an external noise N1 injected through the IC lead and the wiring 55 and an internal noise N2 generated by the power transistor Tr1.

  In the noise tolerance evaluation method 101 shown in FIG. 15, the semiconductor integrated circuit that is actually evaluated is a large-scale LSI. For this reason, the layout diagram of the semiconductor integrated circuit is actually a large-scale layout diagram in which a number of layout diagrams as shown in FIG. 17 are arranged. Therefore, in step S1a of the noise tolerance evaluation method 101 shown in FIG. 15, a layout diagram of a semiconductor integrated circuit is created, and parasitic elements having large capacitance values and resistance values are appropriately selected and extracted from the layout diagram. Incorporated into the circuit net list created in the first step S11. Therefore, the circuit netlist created in the first step S11 of FIG. 15 combines the text data (circuit diagram data) generated from the circuit diagram with the text data (layout data) of the parasitic elements generated from the layout diagram. The circuit topology information including the parasitic element of the semiconductor integrated circuit to be evaluated, that is, the connection information between each device constituting the semiconductor integrated circuit and the parasitic element is described. In the circuit netlist created in the first step S11 of FIG. 15, the LVS verification is performed on the circuit element data obtained from the circuit diagram and the circuit element and parasitic element data obtained from the layout diagram. , Make sure that a match is made. As a result, the node of the circuit element can be connected to the node of the extracted parasitic element, and the parasitic element can be added to the circuit netlist. The circuit net list created in the first step S11 of FIG. 15 is equivalent in data format to the circuit net list created in the first step S11 of FIG. 1, and takes the description format illustrated in FIG. .

  In the noise immunity evaluation method 101 of FIG. 15, when it is determined that there is no noise immunity in the seventh step S17, the process returns to step S1a instead of step S1 to correct only the circuit element layout. Good. In particular, this method is effective when the noise tolerance evaluation method 100 shown in FIG. 1 is performed and the noise tolerance of the semiconductor integrated circuit is confirmed.

  In the semiconductor integrated circuit noise tolerance evaluation methods 100 and 101 shown in FIGS. 1 and 15, the semiconductor integrated circuit may be an entire circuit formed on one semiconductor chip, or one semiconductor chip. It may be a circuit block, which is a component of the entire circuit formed in the above.

  FIG. 19 is a circuit diagram illustrating a part of the logic circuit 60.

  A logic circuit 60 shown in FIG. 19 includes circuit blocks CB1 to CB6 surrounded by a one-dot chain line. Each circuit block CB1 to CB6 has been evaluated for noise resistance by the noise resistance evaluation methods 100 and 101 described above. For this reason, in each of the circuit blocks CB1 to CB6 surrounded by the alternate long and short dash line, which terminal (node) is the most sensitive to noise among the input / output terminals (nodes) enclosed by the alternate long and short dash line, and has the tolerance It is known how much. Accordingly, in the noise tolerance evaluation of the logic circuit 60 shown in FIG. 19, the node most sensitive to noise in each of the circuit blocks CB1 to CB6 is the transistor control node in the noise tolerance evaluation methods 100 and 101 described above. The inside of each of the circuit blocks CB1 to CB6 surrounded by the alternate long and short dash line can be handled as a black box.

  As described above, the noise immunity evaluation method for the semiconductor integrated circuit described above is a novel noise immunity evaluation method that replaces the conventional circuit simulation, and is a substantial noise immunity evaluation even for a large-scale semiconductor integrated circuit. This can be a method for evaluating noise resistance of a semiconductor integrated circuit that can be performed in a short time.

  In the noise tolerance evaluation method described above, noise propagation paths and transistors that are likely to malfunction are narrowed down, and circuit simulation using a conventional circuit simulator (SPICE) is performed on the narrowed propagation paths and transistors. Also good.

  FIG. 20 is a flowchart showing an outline of the noise tolerance evaluation method 102 as a modification of the noise tolerance evaluation method 100 shown in FIG. In addition, in each processing step in the noise tolerance evaluation method 102 in FIG. 20, the same reference numerals are given to those performing the same processing as the processing steps in the noise tolerance evaluation method 100 shown in FIG.

In the noise immunity evaluation method 102 for the semiconductor integrated circuit shown in FIG. 20, the fourth step S14 for setting the noise injection node and the fifth for calculating the impedance of the path are compared with the noise immunity evaluation method 100 shown in FIG. During the step S15, the frequency range of the noise to be evaluated (ω _a <ω _i <ω _b )
Step S18 for setting is added. In the noise tolerance evaluation method 102 in FIG. 20, the noise frequency (ω _i ) set in the fifth step S15 is set to the predetermined frequency range (ω _a <ω _i <ω _b ) shown in step S18.
In the fifth step S15 and the sixth step S16, the impedance of the path between the control node and the noise injection node at each frequency (ω _i ) is calculated, and the frequency dependence of the impedance is evaluated. ing.

  According to this, as compared with the case where the noise tolerance is evaluated only with one noise frequency as in the noise tolerance evaluation method 100 shown in FIG. 1, the noise tolerance can be evaluated more reliably.

  Further, by evaluating the frequency dependence of each impedance between the control node and the noise injection node as described above, it is determined whether each noise propagation path is capacitive, resistive, or inductive. be able to.

  FIG. 21 is a diagram collectively showing the frequency dependence of the impedance of the noise propagation path and whether the noise propagation path is capacitive, resistive, or inductive.

  As shown in FIG. 21, when the impedance of the propagation path is inversely proportional to the noise frequency, it is capacitive, and when the impedance of the propagation path does not depend on the noise frequency, it is resistive, and the impedance of the propagation path is proportional to the noise frequency. If you are inductive. By determining whether the noise propagation path is capacitive, resistive, or inductive, it is possible to implement appropriate and reliable noise countermeasures that match the following propagation path characteristics.

  Next, a noise countermeasure method for the control node determined to have no noise tolerance in the seventh step S17 of the noise tolerance evaluation methods 100 to 102 shown in FIGS. 1, 15, and 20 will be described.

  FIG. 22 and FIG. 23 are flowcharts showing the outline of the noise tolerance evaluation methods 102a and 102b, respectively, as modifications of the noise tolerance evaluation method 102 shown in FIG.

  In the noise immunity evaluation methods 102a and 102b of the semiconductor integrated circuit shown in FIGS. 22 and 23, the control node determined as having no noise immunity in the seventh step S17 as compared with the noise immunity evaluation method 102 shown in FIG. On the other hand, step S19 for setting a noise countermeasure circuit to be described later is added. In the noise immunity evaluation method 102a in FIG. 22, after setting the noise countermeasure circuit in step S19 for the control node determined to have no noise immunity in the seventh step S17, the process returns to step S1 again. The configuration is such that the steps after step S11 of 1 are repeated to confirm again that the noise tolerance has been secured. On the other hand, the noise tolerance evaluation method 102b in FIG. 23 performs the noise countermeasure circuit setting in step S19 for the control node determined to have no noise tolerance in the seventh step S17, and then proceeds to step S4. Then, the noise tolerance evaluation by the impedance check is finished as it is. The noise tolerance evaluation method 102b in FIG. 23 can be employed when the influence and effect on the entire circuit due to the setting of the noise countermeasure circuit in step S19 are known in advance.

  FIG. 24 is an example of a noise tolerance evaluation apparatus for implementing the noise tolerance evaluation methods 102a and 102b of the semiconductor integrated circuit shown in FIGS. 22 and 23, and is a diagram showing the configuration of the noise tolerance evaluation apparatus 202. In addition, in the noise tolerance evaluation apparatus 202 shown in FIG. 24, the same code | symbol was attached | subjected about the part similar to the noise tolerance evaluation apparatus 201 shown in FIG.

  The noise immunity evaluation device 202 of the semiconductor integrated circuit shown in FIG. 24 is added to the configuration of the noise immunity evaluation device 201 shown in FIG. 16, and the control node determined as having no noise immunity by the noise immunity determination unit M17 and the control node Regarding the combination of noise injection nodes, based on the noise countermeasure circuit constraint information M19a, noise that inserts a noise countermeasure element having a predetermined impedance, which will be described later, between the control node and an AC ground node that is set to 0 potential in an alternating manner. A countermeasure circuit creation unit M19b is included.

  Thereby, the noise tolerance evaluation methods 102a and 102b of the semiconductor integrated circuit shown in FIGS. 22 and 23 can be implemented.

  FIG. 25 is a diagram showing an outline of noise countermeasures for a control node determined to have no noise tolerance by the noise tolerance evaluation methods 100 to 102, 102a, and 102b described above, and FIG. 25 (a) is a configuration before noise countermeasures. FIG. 25B shows a configuration after noise countermeasures. FIG. 26 is a diagram showing an example of more detailed noise countermeasures in consideration of the characteristics of the noise propagation path. FIG. 26A shows a configuration for a capacitive propagation path, and FIG. Is a configuration for resistive or inductive propagation paths.

  In FIG. 25A, the noise injection node Pa, the control node Ta, and the impedance Z1 of the noise propagation path are determined as having no noise tolerance in the seventh step S17 in the noise tolerance evaluation methods 100 to 102, 102a, and 102b described above. Combination. The impedance Z2 between the control node Ta and the AC ground node Ga is a ground impedance with respect to the AC ground node Ga of the transistor or circuit block to which the control node Ta belongs.

  As a noise countermeasure for the control node Ta determined to have no noise tolerance, basically, as shown in FIG. 25 (b), a noise countermeasure element having an impedance Z3 smaller than the ground impedance Z2 of the control node Ta is connected to the control node Ta and the AC. The noise component is inserted between the ground nodes Ga to facilitate escape to the AC ground node Ga.

  More specifically, in the noise tolerance evaluation method 102, 102a, 102b of the semiconductor integrated circuit shown in FIGS. 20, 22 and 23, the control node and the noise injection node determined as having no noise tolerance in the seventh step S17. When the impedance of the path is capacitive that is inversely proportional to the frequency, the ground impedance between the control node and the AC ground node set to 0 potential in an alternating manner is calculated for the transistor before replacement, and the ground impedance It is preferable to insert a capacitor having an impedance smaller than the minimum value between the control node and the AC ground node.

  That is, when the impedance Z1 of the noise propagation path between the noise injection node Pa and the control node Ta shown in FIG. 25A is capacitive (C) inversely proportional to the frequency as shown in FIG. For the transistor before replacement, the ground impedance Z2 between the control node Ta and the AC ground node Ga which is set to 0 potential in an alternating manner is calculated, and the impedance [(1 / jωC3) <Z2 smaller than the minimum value of the ground impedance Z2 is calculated. ] Is inserted between the control node Ta and the AC ground node Ga.

  The control node Ta shown in FIG. 26A is the base of the bipolar transistor or the gate of the MOS transistor as described above, and the above-mentioned ground impedance Z2 generally has a large value. Therefore, when the noise propagation path is capacitive (C), the capacitance C3 having an impedance [(1 / jωC3) <Z2] smaller than the ground impedance Z2 of the transistor is set between the control node Ta and the AC ground node Ga. Insert into. As a result, a new path for escaping the noise reaching the control node Ta to the AC ground node Ga is arranged, and malfunction of the transistor due to noise can be suppressed. When the impedance of the capacitor C3 inserted between the control node Ta and the AC ground node Ga is sufficiently small, the control node Ta is in a state of being pseudo-AC grounded against noise.

  When noise countermeasures are implemented, unlike the above, a noise countermeasure capacitor is added to the noise injection node Pa shown in FIG. 26A and connected to the AC ground node, and the noise injected into the noise injection node Pa is AC as soon as possible. A method of escaping to the ground node is also conceivable. However, the method of adding the noise countermeasure capacity to the noise injection node Pa requires a large capacity because the noise injected to the noise injection node Pa is not attenuated. On the other hand, the method of adding the noise countermeasure capacitor C3 to the control node Ta of the transistor that is easily affected by the noise determined to have no noise tolerance is the impedance of the propagation path from the noise injection node Pa to the control node Ta. Since the noise is attenuated, the capacity may be smaller.

  Note that the ground impedance Z2 of FIG. 26A calculated for the transistor before replacement can be calculated using, for example, a circuit simulator (SPICE). Further, for example, the combined impedance of the net path between the control node Ta and the AC ground node Ga after replacement with the above-described passive element circuit may be used.

  In the noise immunity evaluation methods 102, 102a, and 102b of the semiconductor integrated circuit shown in FIGS. 20, 22 and 23, the path for the combination of the control node and the noise injection node determined as having no noise immunity in the seventh step S17. Is impedance independent of frequency or inductivity that increases in proportion to frequency, at least one of a resistance and an inductance is inserted in series before the control node, and a capacitor is connected to the control node. Preferably, it is inserted between AC ground nodes set to zero potential, and at least one of the resistance and inductance and the capacitor constitute a low-pass filter.

  That is, the impedance Z1 of the noise propagation path between the noise injection node Pa and the control node Ta shown in FIG. 25A is a frequency independent resistance (R) or frequency as shown in FIG. In the case of inductivity (L) that increases in proportion to the resistance R4, the resistor R4 is inserted in series before the control node Ta, and the capacitor C4 is inserted between the control node Ta and the AC ground node Ga. C4 constitutes a low-pass filter. Although not shown, instead of the resistor R4, the inductance L4 may be inserted in series before the control node Ta, or both the resistor R4 and the inductance L4 are inserted in series before the control node Ta. Also good.

  When the noise propagation path is resistive (R) or inductive (L), for example, as shown in FIG. 26B, a resistor R4 is inserted in series before the control node Ta, and the control node The attenuation of noise is increased by making the path impedance (R + R4, jωL + R4) to Ta sufficiently high. The resistor R4, the control node Ta, and the capacitor C4 inserted between the AC ground node Ga constitute a low-pass filter having a high cutoff frequency ωh = 1 / C4 · (R + R4, R4). According to this, by appropriately setting the values of the resistor R4 and the capacitor C4, it is possible to cut a high-frequency noise component that is a problem and suppress the transmission of the noise component to the transistor. When the noise propagation path is resistive (R), the resistance R4 is inserted in series between the control node Ta and the AC ground node Ga without connecting the resistor R4 in series before the control node Ta. It is also possible to configure a low-pass filter with the impedance of the path (R).

  In the noise immunity evaluation methods 100 to 102 shown in FIGS. 1, 15 and 20, as in the noise immunity evaluation method 102a shown in FIG. 22, the control determined as having no noise immunity in the seventh step S17. The node is configured to return to step S1 and implement the above-described noise countermeasures, and repeat the steps after the first step S11 to confirm again that noise tolerance has been ensured. However, if the effects and effects of noise countermeasures on impedance are known in advance, such as noise countermeasures inserting noise countermeasure capacitors C3 and C4 and resistor R4 illustrated in FIG. 26, the noise illustrated in FIG. Similar to the tolerance evaluation method 102b, the noise countermeasure may be taken, and the process may proceed to step S4 to end the noise tolerance evaluation as it is.

  On the other hand, when noise countermeasures such as the noise countermeasure capacitors C3 and C4 and the resistor R4 shown in FIG. 26 are implemented, the influence on the circuit operation of the transistor and circuit block to which the control node Ta belongs is applied to the circuit simulation. Need to confirm. The insertion of the capacitors C3 and C4 has the merit that the operating point of the circuit operation is hardly changed, but the delay time is affected. Further, the insertion of the resistor R43 affects the current capability of circuit operation, IR drop (voltage drop), and delay time.

  Next, the above-described noise countermeasure will be described using a specific circuit as an example.

  FIG. 27A is a diagram showing a circuit configuration of a bandgap low voltage circuit (BG circuit) and a case where external noise is injected through the parasitic capacitance Ca, and FIG. 27B is a diagram illustrating a control node Ta. 2 is a diagram showing a circuit configuration when a noise countermeasure capacitor C3 is inserted between the AC ground node Ga and the AC ground node Ga.

  As shown in FIG. 27A, a case where noise propagates from a noise injection node Pa such as an external wiring to the base (control node Ta) of the bipolar transistor Tra via a parasitic capacitance Ca (several tens of fF) is taken as an example. To do. In this case, a malfunction occurs as follows. When noise (AC component voltage) is applied to the PN junction (between the base and emitter of the bipolar transistor Tra), the operating current tends to increase due to the nonlinearity of the PN junction. However, since the operating current of the bipolar transistor Tra is supplied at a constant current, the current to be increased is not supplied, and the operating point is lowered accordingly, and the base-emitter voltage VBE (the + input of the amplifier) ) Decreases. For this reason, the output voltage VBG of the BG circuit decreases and the BG circuit malfunctions.

  As shown in FIG. 27A, a capacitance C3 of 10 pF that is sufficiently larger than the base-emitter capacitance of the bipolar transistor Tra and the parasitic capacitance Ca serving as a noise path is inserted between the control node Ta and the AC ground node Ga. By doing so, noise injected with low impedance can be released to GND.

  According to the BG circuit malfunction analysis (5V output transient analysis) simulation result shown in FIG. 27, for example, when a voltage amplitude equivalent to noise is injected into the noise injection node Pa for a BG circuit whose design output voltage VBG is 1.19V. In the case of FIG. 27A in which the noise countermeasure capacitor C3 is not inserted, the output voltage VBG decreases to 0.68 V (a decrease of about 43%). On the other hand, in the case of FIG. 27B in which the noise countermeasure capacitor C3 is inserted, the output voltage VBG can be 1.13V (a decrease of about 5%) even if noise is injected.

  FIG. 28 is a circuit diagram of a comparator circuit 10a in which a circuit similar to the comparator circuit 10 shown in FIG.

  Similarly to the BG circuit shown in FIG. 27, the comparator circuit 10a shown in FIG. 28 is assumed to have noise injection (noise injection node Pa) through a parasitic capacitance Ca such as an external wiring. The noise countermeasure capacitor C3 is inserted between the control node Ta determined to have no noise tolerance in the seventh step S17 in the noise tolerance evaluation method 102 and the AC ground node Ga. The value of the noise countermeasure capacitor C3 is calculated by calculating the combined impedance of the net path between the control node Ta and the AC ground node Ga before the noise countermeasure capacitor C3 is inserted as the ground impedance Z2 shown in FIG. Set it to a smaller value.

  As described above, the above-described noise tolerance evaluation method for a semiconductor integrated circuit and the noise tolerance evaluation apparatus for implementing the same are both a novel noise tolerance evaluation method and a noise tolerance evaluation apparatus that replace the conventional circuit simulation. Thus, even in a large-scale semiconductor integrated circuit, a noise resistance evaluation method and a noise resistance evaluation apparatus for a semiconductor integrated circuit capable of performing substantial noise resistance evaluation in a short time.

90, 91, 100-102, 102a, 102b Noise tolerance evaluation method 20, 30 Detailed flow T1-T8, Ta control node P1-P4, Pa Noise injection node Ga AC ground node 200-202 Noise tolerance evaluation apparatus

Claims (21)

A noise tolerance evaluation method for a semiconductor integrated circuit for evaluating a noise tolerance of a semiconductor integrated circuit, which is performed in a noise tolerance evaluation apparatus ,
A circuit net list creation unit creating a circuit net list from a circuit diagram of the semiconductor integrated circuit;
A second step in which a replacement circuit netlist creation unit creates a replacement circuit netlist by replacing active elements in the circuit netlist with high-frequency equivalent passive element circuits;
A third step in which a control node extraction unit extracts a control node corresponding to a control terminal of the transistor before replacement from the replacement circuit netlist;
A fourth step in which a noise injection node setting unit selects a predetermined node from the replacement circuit netlist and sets a noise injection node;
A fifth step in which a noise frequency setting unit sets noise of a predetermined frequency, and a path impedance calculation unit calculates a path impedance between the control node and the noise injection node different from each other in the replacement circuit netlist; ,
An impedance list creation unit creating a list of the impedance in each combination of the control node, the noise injection node, and the path;
Noise resistance determining unit, from the minimum value of the impedance in said list, noise immunity evaluation method of a semiconductor integrated circuit characterized by comprising and a seventh step of determining the noise immunity of the semiconductor integrated circuit. The parasitic element extraction unit further includes an eighth step of extracting a parasitic element based on layout information obtained from the layout diagram of the semiconductor integrated circuit ;
2. The method for evaluating a noise resistance of a semiconductor integrated circuit according to claim 1, wherein, in the first step, the circuit net list creation unit creates a circuit net list including the parasitic elements. 3. The method of evaluating noise immunity of a semiconductor integrated circuit according to claim 1, wherein , in the third step, the control node extraction unit extracts all control nodes from the replacement circuit netlist. 3. The noise resistance of the semiconductor integrated circuit according to claim 1, wherein , in the third step, the control node extraction unit selects and extracts a predetermined control node from the replacement circuit netlist. Evaluation method. 5. The noise injection node setting unit according to claim 1, wherein in the fourth step, the noise injection node setting unit selects all nodes from the replacement circuit netlist and sets noise injection nodes. 2. A method for evaluating noise resistance of a semiconductor integrated circuit according to 1. 5. The noise injection node setting unit according to claim 1, wherein the noise injection node setting unit sets a noise injection node by selecting a node of an external terminal from the replacement circuit netlist. The method for evaluating noise resistance of a semiconductor integrated circuit according to the item. In the fifth step, the path impedance calculation unit calculates a combined impedance of a net path between the control node and a noise injection node,
The said 6th step WHEREIN: The said impedance list preparation part produces the list | wrist of the said synthetic | combination impedance in each combination of the said control node and the said noise injection node, It is any one of Claim 1 thru | or 6 characterized by the above-mentioned. The noise tolerance evaluation method of the semiconductor integrated circuit as described. The path impedance calculator has a circuit simulator,
The circuit simulator applies a predetermined AC potential difference or AC current to the control node and the noise injection node, and calculates the combined impedance from the total current flowing between the control node and the noise injection node or the potential difference between the nodes. The method for evaluating noise resistance of a semiconductor integrated circuit according to claim 7, wherein: The path impedance calculation unit uses a hardware description language to give a predetermined AC potential difference or AC current to the control node and the noise injection node, and a total current flowing between the control node and the noise injection node or between the nodes. The method for evaluating noise resistance of a semiconductor integrated circuit according to claim 7, wherein the combined impedance is calculated from a potential difference. In the fifth step, the path impedance calculation unit calculates an impedance of a line path between the control node and a noise injection node,
The impedance list creation unit creates the impedance list in each combination of the control node, the noise injection node, and the line path in the sixth step . The method for evaluating noise resistance of a semiconductor integrated circuit according to one item. 11. The replacement circuit netlist creation unit sets the ground (GND) node and the power supply node of the replacement circuit netlist as AC ground nodes set to zero potential in an alternating manner. The method for evaluating noise resistance of a semiconductor integrated circuit according to any one of the preceding claims.   12. The method for evaluating noise resistance of a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an entire circuit formed on one semiconductor chip.   The noise of the semiconductor integrated circuit according to any one of claims 1 to 11, wherein the semiconductor integrated circuit is a circuit block which is a component of an entire circuit formed in one semiconductor chip. Resistance evaluation method. In order to evaluate the frequency dependence of impedance, in the fifth step, the noise frequency setting unit changes the frequency of noise to be set within a predetermined frequency range, and the path impedance calculation unit is configured to connect the control node and the noise. noise immunity evaluation method of a semiconductor integrated circuit according to any one of claims 1 to 13, characterized in that to calculate the impedance of the path between the injection node. About the combination of the control node and the noise injection node determined to have no noise tolerance in the seventh step,
15. The semiconductor integrated circuit according to claim 14 , wherein the noise countermeasure circuit creation unit inserts a noise countermeasure element having a predetermined impedance between the control node and an AC ground node that is set to zero potential in an alternating manner. Noise tolerance evaluation method. For the combination of the control node and the noise injection node determined to have no noise tolerance in the seventh step, when the impedance of the path is capacitive that is inversely proportional to the frequency,
The noise countermeasure circuit creation unit calculates a ground impedance between the control node and the AC ground node for the transistor before replacement,
16. The noise resistance evaluation of a semiconductor integrated circuit according to claim 15, wherein a capacitor having an impedance smaller than the minimum value of the ground impedance is inserted between the control node and the AC ground node as the noise countermeasure element. Method.   17. The noise tolerance evaluation of a semiconductor integrated circuit according to claim 16, wherein the ground impedance calculated for the transistor before replacement is a combined impedance of a net path between the control node and the AC ground node after the replacement. Method. When the combination of the control node and the noise injection node determined to have no noise tolerance in the seventh step is a frequency-independent resistance or an inductivity that increases in proportion to the frequency ,
The noise countermeasure circuit creation unit inserts at least one of a resistor and an inductance in series before the control node as the noise countermeasure element, and inserts a capacitor between the control node and the AC ground node, 16. The method for evaluating noise resistance of a semiconductor integrated circuit according to claim 15, wherein at least one of the inductance and the capacitance constitute a low-pass filter. A noise immunity evaluation apparatus of semi-conductor integrated circuit,
Based on the circuit information obtained from the circuit diagram of the semiconductor integrated circuit, a circuit netlist creation unit that creates a circuitry netlist,
Based on replacement information to the passive element circuit from the active element, the circuit active elements in the net list replacing the high-frequency equivalent passive element circuit, replacing circuit creating a location circuit netlist netlist generation unit When,
From the substitution circuit netlist, a control node extracting unit that extracts a control node corresponding to a control terminal of the replacement before the transistor,
And selecting a predetermined node from the substitution circuit netlist, and the noise injection node setting unit for setting a noise injection node,
And the noise frequency setting unit which sets the noise of Jo Tokoro frequency,
In said replacement circuit netlist, and route the impedance calculation unit for calculating the impedance of the route between different said control node and said noise injection node,
An impedance list creation unit for creating a list of the impedances in each combination of the control node, the noise injection node, and the path;
A noise tolerance evaluation apparatus for a semiconductor integrated circuit, comprising: a noise tolerance determination unit that determines noise tolerance of the semiconductor integrated circuit from the minimum value of the impedance in the list. Based on layout information obtained from the layout diagram of the semiconductor integrated circuit, a parasitic element extraction unit that extracts a parasitic element from the layout information,
20. The noise immunity evaluation apparatus for a semiconductor integrated circuit according to claim 19, wherein the circuit net list creation unit creates the circuit net list including the parasitic elements. About the combination of the control node and the noise injection node determined to have no noise tolerance in the noise tolerance determination unit,
A noise countermeasure circuit creation unit for inserting a noise countermeasure element having a predetermined impedance between the control node and an AC ground node that is set to 0 potential in an alternating manner based on the noise countermeasure circuit constraint information. 21. The apparatus for evaluating noise tolerance of a semiconductor integrated circuit according to claim 19 or 20.

Images