JP5569910B2 - 薄箔を基礎とした半導体パッケージの製造方法 - Google Patents
薄箔を基礎とした半導体パッケージの製造方法 Download PDFInfo
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- JP5569910B2 JP5569910B2 JP2011512502A JP2011512502A JP5569910B2 JP 5569910 B2 JP5569910 B2 JP 5569910B2 JP 2011512502 A JP2011512502 A JP 2011512502A JP 2011512502 A JP2011512502 A JP 2011512502A JP 5569910 B2 JP5569910 B2 JP 5569910B2
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- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12431—Foil or filament smaller than 6 mils
- Y10T428/12438—Composite
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims (11)
- 金属担体を提供するステップと、
金属箔を提供するステップと、
前記金属箔の一部を前記金属担体に超音波接合するステップであって、接合部分が集積回路のパッケージングにおける箔担体パネルとして使用される前記金属箔内の複数のパネルを規定し、前記接合部分が長方形状を形成する線になって配置され、各長方形状が前記複数のパネルの1つを規定し、前記複数のパネルが複数の行と複数の列に配置されてパネルのアレイを形成する、前記ステップと、
各パネルが他から分離されて前記超音波接合動作により形成される長方形状の少なくとも1つを含むように、前記金属箔を十字に交差する複数のソーストリートに沿って前記金属箔を切断するステップと、
を含む、方法。 - 請求項1に記載の方法であって、
前記金属箔の表面を銀または銀合金でスポット鍍金して各パネル内に複数のデバイスエリアを形成するステップを更に含み、各デバイスエリアが集積回路ダイのワイヤボンディングに用いられ、前記金属箔が前記スポット鍍金動作の間に連続した金属のシートのままであり、前記スポット鍍金動作が前記金属箔の切断の前に行われる、方法。 - 請求項1又は2に記載の方法であって、
前記金属箔が、前記金属箔の上部表面及び底部表面上に形成されたニッケル層及びパラジウム層を有する銅箔である、方法。 - 請求項1乃至3のいずれか1項に記載の方法であって、
前記金属箔の厚さが0.5と2ミル(12.70と50.80μm)の間であり、前記担体の厚さが5と10ミル(127.00と254.00μm)の間である、方法。 - 請求項1乃至4のいずれか1項に記載の方法であって、
前記超音波接合部分が、複数の閉じた長方形状を規定する連続した線の形状に形成され、各閉じた長方形状が前記複数のパネルの各々の周りに連続的な周辺部を形成する、方法。 - 請求項1乃至5のいずれか1項に記載の方法であって、
接合された金属箔と金属担体を切断することが複数の分離されたパネルを形成する、方法。 - 金属担体を提供するステップと、
金属箔を提供するステップと、
前記金属箔の部分を前記金属担体に超音波接合して箔担体構成体を形成するステップであって、前記接合部分が長方形状パネルを形成する線になって配置される、前記ステップと、
複数のダイを前記金属箔に取り付けるステップと、
モールド箔担体構成体を形成するために前記複数のダイと前記金属箔の少なくとも一部をモールディング物質で封止するステップと、
モールド箔構成体を形成するために前記モールド箔担体構成体から前記担体を取り除くステップと、
前記金属箔内に複数のデバイスエリアを規定するために前記担体を取り除いた後に前記金属箔をエッチングするステップであって、各デバイスエリアが前記複数のダイの内の少なくとも1個を支持し且つ複数の電気的接続部を有し、前記エッチングが前記モールディング物質の一部を露出させる、前記ステップと、
前記エッチングステップの後に、複数のパッケージ化された集積回路装置を提供するために前記モールド箔構成体を単体化するステップと、
を含む、方法。 - 請求項7に記載の方法であって、
前記封止ステップが、前記金属箔上に単一の連続したモールドされたストリップを形成する態様で、前記モールディング物質を前記複数のダイと前記金属箔の前記一部とに適用することを含む、方法。 - 請求項7に記載の方法であって、
前記金属箔が、銅層と、銀又は銀合金から形成された第2層とを含み、
前記モールディング物質が前記銀層と接触し、
前記エッチングステップが、各デバイスエリア上にコンタクトパッドを形成するために前記銅層と前記第2層の両方をエッチングすることを含み、前記モールディング物質がコンタクトパッド間に露出され、
前記第2層が各コンタクトパッド上にワイヤボンディングサイトを提供する、
方法。 - 請求項7に記載の方法であって、
前記金属箔をエッチングプロセスのために露出させる形態とされる再使用可能なエッチング担体のキャビティ内に前記モールド箔構成体を設置するステップを更に含む、方法。 - 請求項7に記載の方法であって、
前記金属箔がニッケルとパラジウムで被覆された複数の表面を有する金属層を含む、方法。
Applications Claiming Priority (3)
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US12/133,335 | 2008-06-04 | ||
US12/133,335 US8375577B2 (en) | 2008-06-04 | 2008-06-04 | Method of making foil based semiconductor package |
PCT/US2009/043503 WO2009148768A2 (en) | 2008-06-04 | 2009-05-11 | Foil based semiconductor package |
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JP2011523213A JP2011523213A (ja) | 2011-08-04 |
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US (1) | US8375577B2 (ja) |
EP (1) | EP2286451A4 (ja) |
JP (1) | JP5569910B2 (ja) |
KR (1) | KR101612976B1 (ja) |
CN (1) | CN102057485A (ja) |
MY (1) | MY152738A (ja) |
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-
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- 2008-06-04 US US12/133,335 patent/US8375577B2/en active Active
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- 2009-05-11 WO PCT/US2009/043503 patent/WO2009148768A2/en active Application Filing
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CN102057485A (zh) | 2011-05-11 |
KR20110015047A (ko) | 2011-02-14 |
US8375577B2 (en) | 2013-02-19 |
KR101612976B1 (ko) | 2016-04-15 |
JP2011523213A (ja) | 2011-08-04 |
WO2009148768A3 (en) | 2010-03-04 |
US20090305076A1 (en) | 2009-12-10 |
WO2009148768A2 (en) | 2009-12-10 |
MY152738A (en) | 2014-11-28 |
TWI484611B (zh) | 2015-05-11 |
EP2286451A2 (en) | 2011-02-23 |
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