JP5569840B2 - Wiring board forming method and wiring board - Google Patents

Description

  The present invention relates to a wiring board forming method for forming a wiring pattern on the surface of a conductive substrate, and more particularly to a wiring board forming method for simultaneously forming a decoupling capacitor when forming a wiring pattern.

  In order to eliminate a malfunction of a circuit caused by fluctuations in power supply voltage, a technique for suppressing noise by connecting a decoupling capacitor near the substrate is generally known. The decoupling capacitor needs to be arranged close to the substrate, and it is necessary to secure a region for the arrangement, which has been a factor that hinders downsizing of the semiconductor.

  In connection with the above factors, a wiring board incorporating a decoupling capacitor is disclosed (for example, see Patent Documents 1 and 2). In the technique shown in Patent Document 1, a decoupling capacitor is formed between an input-side electrode layer and an output-side electrode layer via an interlayer insulating layer, and this decoupling capacitor is connected between a ground layer and a power supply layer. A plurality of power supply terminals used to supply power to the semiconductor element are formed by patterning the output-side electrode layer, and these power supply terminals are connected to the power supply layer by capacitor vias. Is.

  The technique shown in Patent Document 2 is formed between a plurality of through vias such as power supply vias, ground vias, signal vias and the like formed between the front and back surfaces and the pitch of the through vias. It is an interposer made of ceramic having a dielectric constant material, a power electrode surface and a ground electrode surface extending in a direction substantially orthogonal to the surface.

JP 2005-310814 A JP 2001-326298 A

However, since the technique shown in each of the above patent documents incorporates a decoupling capacitor, the manufacturing process becomes complicated, and there is a problem that labor and cost increase.
Therefore, the present invention provides a wiring board forming method and a wiring board that can greatly reduce the labor and cost of manufacturing a wiring board by simultaneously forming a decoupling capacitor when forming a wiring pattern. .

(1) The wiring board forming method disclosed in the present application is a wiring board forming method for forming a wiring board on which a circuit element is placed on at least one side surface of a conductive substrate. A cylindrical first via insulating portion for insulatingly covering the entire surface from one side surface to the other side surface of the substrate, and a conductive material having conductivity in the first via insulating portion are sealed inside the via. A via forming step for forming a first via conductive portion; and at least a peripheral region of the first via conductive portion on the other side surface of the substrate; and a cylindrical end portion of the first via insulating portion. A dielectric part forming step of forming a dielectric part by extending an insulating material to be connected over the entire circumference, and a first wiring layered on the surface of the dielectric part and connected to the first via conductive part Wiring forming step of forming a portion, and the first wiring There is connected to the power supply, the substrate is connected to the ground, is characterized in that the capacitor sandwiching the dielectric portion is formed by the substrate and the first wiring portion.

  As described above, in the wiring substrate forming method disclosed in the present application, the first wiring portion is connected between the substrate connected to the ground and the first wiring portion connected to the first via conductive portion and connected to the power source. Since a capacitor is formed with a dielectric portion formed by extending an insulating material connected over the entire circumference of the cylindrical end portion of the via insulating portion, a decoupling capacitor is formed at the same time as the wiring portion is formed Thus, there is no need for a special process for forming the decoupling capacitor, and it is possible to significantly reduce manufacturing labor and cost.

  (2) In the wiring board forming method disclosed in the present application, in the via forming step, the entire surface from the one side surface to the other side surface of the substrate is insulated and coated inside the second via formed in the substrate. A second via-conductive portion having a shape and a second via-conductive portion in which a conductive material having conductivity is enclosed in the second via-insulating portion. An insulating part forming step of forming an insulating part by extending an insulating material so as not to be in contact with at least a part of the cylindrical end part of the second via insulating part, which is laminated in a peripheral region of the via conductive part; The wiring forming step forms a second wiring portion formed on the surface of the insulating portion and connected to the second via conductive portion and the substrate, and the second wiring portion is grounded. And the dielectric portion is connected to the first wiring portion and the substrate. It is characterized in that the capacitor sandwiching is formed.

  As described above, in the wiring board forming method disclosed in the present application, the second via insulating portion and the second via conductive portion are formed, and at least a part of the second via insulating portion is in contact with the cylindrical end portion. Forming an insulating portion by extending an insulating material so as not to be laminated, forming a second wiring portion formed on the surface of the insulating portion and connected to the second via conductive portion and the substrate; 2 is connected to the ground, and a capacitor sandwiching the dielectric portion between the first wiring portion and the substrate is formed. Therefore, at the same time as forming the wiring portion, the first wiring portion serving as a power supply electrode and the ground A decoupling capacitor can be formed by using the second wiring portion serving as an electrode, and a special process for forming the decoupling capacitor is not required, thereby greatly reducing manufacturing labor and cost. Has the effect of being able to

  (3) In the wiring substrate forming method disclosed in the present application, the dielectric portion forming step and the insulating portion forming step form a groove having a cross-sectional shape by discharging droplets of the insulating material by an ink jet method. Including a catalyst forming step of discharging droplets serving as a catalyst for electroless plating into the groove having a cross-sectional groove shape of the material by the inkjet method, wherein the wiring forming step is performed by electroless plating on the surface of the catalyst. The first wiring portion and the second wiring portion are formed.

  As described above, in the method for forming a wiring board disclosed in the present application, a droplet of an insulating material for forming a dielectric portion and an insulating portion is ejected by an ink jet method to form a concave groove shape, and there is no recess in the groove. Since the droplets that serve as the catalyst for electroplating are discharged, the electroless plating catalyst is reliably discharged without protruding from the insulating material, and the decoupling capacitor is formed at the same time as the wiring part is formed within the range of the groove in the cross section Can be formed easily, and the work can be saved. Further, the decoupling capacitor can be formed not on the inside of the substrate but on the surface by the ink jet method, and the manufacturing labor and cost can be greatly reduced.

  (4) In the wiring board forming method disclosed in the present application, the droplet of the insulating material is a droplet that becomes liquid repellent with the first conductive portion and the second conductive portion formed in the via. It is characterized by this.

  As described above, in the wiring substrate forming method disclosed in the present application, the droplets of the insulating material are droplets that become liquid repellent with the first conductive portion and the second conductive portion formed in the via. Therefore, the insulating material remains on the surfaces of the first conductive portion and the second conductive portion, so that the conductivity is not deteriorated, and the conductivity can be ensured.

  (5) In the wiring board forming method disclosed in the present application, the insulating material applied to the surfaces of the first conductive portion and the second conductive portion after the dielectric portion forming step and the insulating portion forming step. And a cleaning process for cleaning the droplets.

  As described above, in the wiring board forming method disclosed in the present application, after forming the dielectric portion and the insulating portion, the droplets of the insulating material applied to the surfaces of the first conductive portion and the second conductive portion are washed. Therefore, it is possible to prevent the insulating material from remaining on the surfaces of the first conductive portion and the second conductive portion, thereby ensuring the conductivity.

  (6) In the wiring board forming method disclosed in the present application, the insulating droplets discharged in the dielectric portion forming step are dielectrics, and the insulating droplets discharged in the insulating portion forming step are insulators. The dielectric and the insulator are discharged from different discharge ports in a single step.

  As described above, in the wiring board forming method disclosed in the present application, the insulating droplets ejected in the dielectric portion forming step and the insulating droplets ejected in the insulating portion forming step are different droplets. However, since the discharge is performed in one process from different discharge ports, the manufacturing process can be simplified and the working efficiency can be improved without performing each process in a separate process.

  (7) A wiring board disclosed in the present application is a wiring board in which a circuit element is placed on at least one side surface of the board, and at least the surface on the other side surface of the board has conductivity. A first via insulating portion formed in a cylindrical shape by insulatively covering the entire surface from one side surface to the other side surface of the substrate inside the formed first via, and in the first via insulating portion A first via conductive portion formed by encapsulating a conductive material having conductivity, and laminated on at least a peripheral region of the first via conductive portion on the other side surface of the substrate; A dielectric portion formed by extending an insulating material to be connected over the entire circumference of the cylindrical end portion of the portion, and formed by being laminated on the surface of the dielectric portion and connected to the first via conductive portion. A first wiring portion, wherein the substrate is connected to the ground, Serial and is characterized in that the capacitor sandwiching the dielectric portion is formed and the substrate first wiring portion.

  (8) The wiring board disclosed in the present application is a cylindrical second via insulating portion that covers and covers the entire surface from one side surface to the other side surface of the substrate inside the second via formed in the substrate. And a second via conductive portion encapsulating a conductive material in the second via insulating portion, and laminated on at least the peripheral region of the second via conductive portion on the other side of the substrate, An insulating portion formed by extending an insulating material so that at least a portion thereof does not contact the cylindrical end portion of the second via insulating portion; and the second via that is laminated on a surface of the insulating portion. A conductive part and a second wiring part formed to be connected to the substrate, wherein the second via conductive part is connected to the ground, and the dielectric part is sandwiched between the first wiring part and the substrate. A capacitor is formed.

It is sectional drawing and the equivalent circuit schematic of the wiring board which concerns on embodiment of this invention. It is a functional block diagram of the apparatus used for the wiring board formation method which concerns on embodiment of this invention. It is a figure which shows the process of the inkjet method used for the wiring board formation method which concerns on embodiment of this invention. It is a flowchart which shows the wiring board formation method which concerns on embodiment of this invention. It is a figure which shows each process of the wiring board formation method which concerns on embodiment of this invention.

  Embodiments of the present invention will be described below. The present invention can be implemented in many different forms. Also, the same reference numerals are given to the same elements throughout the present embodiment.

(Embodiment of the present invention)
A wiring board and a wiring board forming method according to this embodiment will be described with reference to FIGS. 1 is a cross-sectional view and an equivalent circuit diagram of a wiring board according to the present embodiment, FIG. 2 is a functional block diagram of an apparatus used for the wiring board forming method according to the present embodiment, and FIG. 3 is a wiring according to the present embodiment. FIG. 4 is a flowchart showing a wiring board forming method according to this embodiment, and FIG. 5 is a drawing showing each process of the wiring board forming method according to this embodiment. is there.

  In FIG. 1A, a wiring substrate 1 includes a silicon substrate 2 having conductivity, vias 7a and 7b formed in the silicon substrate 2, and other sides from the one side of the silicon substrate 2 inside the vias 7a and 7b. Cylindrical via insulating portions 3a and 3b that insulate and coat the entire side surface, via conductive portions 4a and 4b enclosing conductive materials in the via insulating portions 3a and 3b, and the lower surface side of the silicon substrate 2 The dielectric portion 5a is formed by extending an insulating material that is stacked at least in the peripheral region of the via conductive portion 4a and connected over the entire circumference of the cylindrical end portion of the via insulating portion 3a. On the lower surface side, an insulating portion 5b is formed that is laminated at least in the peripheral region of the via conductive portion 4b and is formed by extending an insulating material so that at least a part thereof does not contact the cylindrical end portion of the via insulating portion 3b; Part 5a or insulating part 5b Provided via conductor portion 4a while being laminated on the surface, the wiring portion 6a which is connected to 4b, and the 6b.

  The wiring portion 6a is connected to a power supply and functions as a power supply electrode, and the wiring portion 6b is connected to the ground (GND) and functions as a GND electrode. That is, since the wiring part 6b is in contact with the silicon substrate 2, the silicon substrate 2 becomes GND, and a decoupling capacitor is formed in which the dielectric part 5a is sandwiched between the wiring part 6a and the silicon substrate 2. FIG. 1B shows this configuration as an equivalent circuit, and a capacitor is configured between the power supply and GND.

  In FIG. 1, the insulating portion 5 b is formed by extending an insulating material so that at least part of the insulating portion 5 b does not contact the cylindrical end portion of the via insulating portion 3 b, thereby connecting the silicon substrate 2 to the GND. However, it is not always necessary to use such a configuration as long as the silicon substrate 2 is connected to GND as shown in FIG.

  In addition, since both the dielectric portion 5a and the insulating portion 5b need to have insulating properties, they may be formed of the same insulating material, but the performance of the decoupling capacitor is improved (decoupling capacitor performance). In order to increase the capacitance, it is desirable to form the dielectric portion 5a with a dielectric (eg, barium titanate).

  In the present embodiment, an inkjet method is used when forming the dielectric portion 5a, the insulating portion 5b, and the wiring portions 6a and 6b. The dielectric part 5a and the insulating part 5b are formed by discharging droplets by an ink jet method, and the wiring parts 6a and 6b are formed by electroless plating on the surfaces of the dielectric part 5a and the insulating part 5b by the ink jet method. After discharging droplets serving as a catalyst, the wiring portions 6a and 6b are formed by electroless plating.

Here, the ink jet method used in the present embodiment will be described in detail. FIG. 2 shows a configuration of an apparatus for realizing the ink jet method. The inkjet apparatus 100 controls the movement of the ejection port that ejects droplets based on the wiring pattern information stored in the drawing information 70, and draws the wiring pattern with the droplets ejected from the ejection port. A silicon substrate 2 that forms the conductive substrate, a plating unit 30 that forms the wiring substrate 1 on which conductive wiring is formed by performing electroless plating, a movement control unit 50 that controls the movement of the discharge port of the inkjet 10, And a drive unit 60 that moves the discharge port based on the control of the movement control unit 50.

  Further, the ink jet 10 discharges the insulator droplets in the cross-sectional groove shape to form the insulating portion 5b, and discharges the dielectric droplets in the cross-sectional groove shape to discharge the dielectric portion 5a. And forming a catalyst portion by discharging droplets serving as a catalyst for electroless plating into a groove having a cross-sectional groove shape formed by the insulator discharge portion 11 and the dielectric discharge portion 14. The catalyst discharge part 12 and the discharge control part 13 which controls the discharge operation of each discharge part are provided.

  As the ink jet ink (hereinafter referred to as ink) that provides droplets for forming the dielectric portion 5a and the insulating portion 5b having insulating properties, the ink jet ink (hereinafter referred to as the head) has an insulating property after drying the droplets. Therefore, it is necessary to form liquid droplets that can be ejected stably and continuously. About the structure of insulating ink, it can produce | generate by selecting a well-known material as a structural component and adjusting to the appropriate physical property mentioned later.

  In general, the physical properties of ink on which droplets are stably formed in a head of a piezoelectric element vary depending on the configuration of the head, but the viscosity is 3 mPa · sec to 150 mPa · sec, preferably 4 mPa · sec at the temperature inside the head. Or 30 mPa · sec. When the value is larger than this, it becomes impossible to eject the droplet, and when the value is smaller, the ejection amount of the droplet is not stable.

  The surface tension is 20 mN / m to 40 mN / m at the temperature inside the head. If the value is larger than this, the droplets cannot be ejected, and if the value is smaller, the droplet amount during continuous ejection is not stable.

  The temperature inside the head depends on the material stability, but is used at a room temperature of 20 ° C. to 45 ° C. In order to increase the solid content in the ink and improve the film thickness, a temperature of about 40 ° C. is sometimes used.

In order to draw the dielectric portion 5a and the insulating portion 5b by ink jet, it is necessary to land the droplets continuously, and the individual droplets after landing need to be combined. Therefore, the pitch p ₁ between droplet landings is set so that D> p ₁ with respect to the droplet spreading diameter D at the time of landing. The droplet spreading diameter D at the time of landing is always larger than the diameter d of the droplet flying from the head. Further, immediately after the landing, the kinetic energy is consumed and the contact substrate and the static stable state are reached. Therefore, since it is difficult to measure the spread diameter immediately after landing, D ₁ > p ₁ is set using the spread diameter D ₁ that is stably observed after one drop has landed on the substrate.

  On the other hand, the inventors have found that the static contact angle is important in order to obtain a good shape after the droplets coalesce. When the contact angle exceeds 30 °, if the line has fluidity, after forming the shape, a bulge is formed in part, and further, it breaks up into droplets, and a good shape cannot be maintained.

As a constituent component of the ink for having insulating properties after formation, a resin composition showing insulating properties is used to stabilize the shape in the application of the catalyst ink for forming the catalyst portion which is the subsequent treatment, as described above. It should be prepared so that it is soluble or nanodispersible in the solvent used for adjusting the viscosity and surface tension and does not exhibit fluidity after evaporation of the solvent.

  In particular, the ink composition that preferentially forms a cross-sectional groove shape is preferably prepared so as not to exhibit fluidity during solvent evaporation. Further, when the contact angle with the substrate is set to be less than 30 °, it is possible to form a concave groove shape preferentially in the solvent evaporation process.

  The physical property value of the catalyst ink containing a component that becomes a catalyst for electroless plating is also made equal to the physical property of the insulating ink in order to be stably ejected by inkjet. As the catalyst component, a palladium salt is generally used, and an aqueous solution containing a base necessary for stabilizing the complex is used. To this, an ethylene glycol solvent that does not impair stability in order to obtain a viscosity suitable for inkjet is added, and a nonionic surfactant is added to adjust the surface tension.

  In addition, the catalyst ink used for electroless plating is not limited to a uniform solution, and contains nano metal catalyst particles and catalyst metal colloids (for example, reference materials: Tadao Hayashi, Masao Matsuoka, Hidemi Rope Fune, “ Electroless Plating—Basics and Applications ”(described in the“ Electroplating Research Society ”, published by Nikkan Kogyo Shimbun), which has the ink physical properties, head ejection stability, head material corrosion, etc. It is applicable if it does not affect.

The droplet landing pitch p ₂ of the catalyst ink is set such that D ₂ > p ₂ with respect to the droplet spreading diameter D ₂ for the dielectric portion 5a and the insulating portion 5b. At this time, since the dielectric part 5a and the insulating part 5b have a groove shape in cross section, it is sufficient to fill the liquid so as not to overflow from the left and right banks.

  FIG. 3 shows the steps of the ink jet method. First, the surface treatment of the silicon substrate 2 is performed (FIG. 3A). In this surface treatment, the Deep-UV irradiation device 37 is used to irradiate the surface of the silicon substrate 2 with Deep-UV, thereby causing a photochemical reaction on the surface of the silicon substrate 2 to oxidize and remove organic substances. .

  When the surface of the silicon substrate 2 is cleaned, the insulating wiring 33 is formed (FIG. 3B). The insulating ink 33a is discharged from the head 32 with the physical property values of the insulating ink as described above. At this time, the insulating ink 33a is ejected in the same pattern as the wiring pattern information. After drawing the insulating wiring, the silicon substrate 2 is dried on a hot plate. By this step, the dielectric portion 5a and the insulating portion 5b shown in FIG. 1 are formed, and each insulating wiring has a concave groove shape in cross section.

  When the insulating wiring 33 is formed, a line of the catalyst portion (palladium salt) 34 is formed (FIG. 3C). The catalyst ink 34a is ejected from the head 32 into the concave groove of the insulating wiring 33 formed in the previous step with the physical property values of the catalyst ink as described above. After line drawing of the catalyst part 34, drying is performed at room temperature. The catalyst part 34 is formed in the concave groove in the insulating wiring 33, and the catalyst ink 34 does not protrude from the left and right banks.

  When the line of the catalyst part 34 is formed, the photocuring of the insulating resin is performed (FIG. 3D). Here, ultraviolet rays are irradiated by the ultraviolet exposure device 38, and air blow drying is performed after washing with pure water.

  When the photocuring of the insulating resin is performed, an alkali reduction treatment is performed (FIG. 3E). Here, it is immersed in a dimethylaminoborane DMAB aqueous solution, washed with water and air blow dried.

When the alkali reduction treatment is performed, an electroless plating treatment is performed (FIG. 3F). Here, it is immersed in a plating solution, subjected to electroless plating and washed with water. A plating layer 36 is formed in the concave groove in the insulating wiring 33.

  Here, the drawing of the insulating wiring and the drawing of the catalyst portion are performed separately, but the respective droplets are arranged on the heads arranged adjacent to each other or separated by a predetermined distance. The insulating ink that is filled and discharged in the process of forming the insulating wiring and the catalyst ink that is discharged in the process of forming the catalyst part are disposed adjacent to each other or separated by a predetermined distance. Insulating ink and catalyst ink may be sequentially discharged by one drawing process, preceded by a step of forming at least insulating wiring, which are discharged from different discharge ports. In this case, it is preferable to heat the substrate to about 30 ° C. to 100 ° C. in order to suppress the fluidity of the insulating droplets.

  In the present embodiment, the dielectric portion 5a and the insulating portion 5b are formed when the insulating wiring is drawn. Therefore, an insulating ink which is discharged in the process of forming the dielectric portion 5a by filling each of the droplets into two heads that are arranged adjacent to each other or separated by a predetermined distance, and the insulating portion Insulating ink ejected in the step of forming 5b is ejected from different ejection ports disposed adjacent to each other or separated by a predetermined distance, and the dielectric portion 5a, The insulating portion 5b may be drawn at the same time. In other words, a head for ejecting ink for forming the dielectric portion 5a, a head for ejecting ink for forming the insulating portion 5b, and a head for ejecting ink for forming the catalyst portion are individually prepared, and one drawing process is performed. Then, the insulating wiring and the catalyst portion may be drawn.

  Furthermore, in the wiring pattern forming method in the present embodiment, the insulating wiring is a curable resin composition, and after the catalyst forming step, the catalyst is fixed or plated at the time of reduction of the catalyst portion and / or electroless plating. For the purpose of stably forming the layer, it includes an immobilization step of curing the curable resin composition and immobilizing the catalyst portion by irradiating the insulating wiring with ultraviolet rays or performing heat treatment at 80 ° C. to 160 ° C. Therefore, even if the reducing solution or plating solution is alkaline, the catalyst will not be eluted, and a linear catalyst part is surely formed, and a highly accurate wiring pattern is formed by electroless plating. You may be able to.

  Furthermore, the catalyst used in electroless plating, its reduction method, plating bath, and plating method are not limited to those described above, and known methods can be used (see, for example, references).

  Furthermore, in this embodiment, the formation of the catalyst portion and the electroless plating are performed after forming the insulating wiring, but the formation of the insulating wiring without performing the formation of the catalyst portion and the electroless plating is performed. A conductive wiring pattern may be formed by applying a conductive paste on the insulating wiring.

  The above is the detailed description regarding the ink jet method used in the present embodiment. In the present embodiment, the dielectric part 5a, the insulating part 5b, and the catalyst part are drawn using the inkjet method to form the wiring parts 6a and 6b, and the decoupling capacitor is simultaneously formed.

  Next, processing steps of the wiring board forming method according to the present embodiment will be described with reference to FIGS. First, vias 7a and 7b are formed in the silicon substrate 2 (S21), and cylindrical via insulating portions 3a and 3b that insulate and cover the entire surface from one side to the other side of the silicon substrate 2 inside the vias 7a and 7b. (S22), via conductive portions 4a and 4b in which a conductive material having conductivity is enclosed are formed in the via insulating portions 3a and 3b (S23), and the back surface of the silicon substrate 2 is polished (S24). FIG. 5A shows the wiring board formed through the steps up to here.

The dielectric part 5a and the insulating part 5b are drawn on the back surface of the polished silicon substrate 2 (S25, S
26) The surfaces of the via conductive portions 4a and 4b are cleaned (S27). The drawing here uses the ink jet method described above. A wiring substrate formed through the steps up to here is illustrated in FIG. As shown in FIG. 5 (B), the dielectric portion 5a is stacked with a predetermined width d ₁ in the peripheral region of at least via conductor portion 4a, the entire circumference of the cylindrical end portion 3a of the via insulating portion 3a ' Formed by extending the insulating material to be connected, the insulating portion 5b is laminated at least in the peripheral region of the via conductive portion 4b, and at least partly does not contact the cylindrical end portion 3b ′ of the via insulating portion 3b. to secure the width d ₂ from the tubular end portion 3b 'is formed by extending the insulating material.

  By forming in this way, the wiring part 6a connected to the power source is completely insulated from the silicon substrate 2, and the electrode of the wiring part 6b connected to GND is connected to the silicon substrate 2, and as a result In addition, the silicon substrate 2 is connected to GND.

  In addition, the surface of the via conductive portions 4a and 4b can be simplified by preparing the droplets of the insulating material for drawing the dielectric portion 5a and the insulating portion 5b to be liquid repellent with the via conductive portions 4a and 4b. It is possible to ensure the conductivity. Further, when drawing the dielectric portion 5a and the insulating portion 5b, an insulating material and a liquid repellent material may be applied in advance to the surfaces of the via conductive portions 4a and 4b. The thickness of the dielectric part 5a is preferably 10 μm or less in consideration of the connection of the wiring part 6a.

  When the dielectric portion 5a and the insulating portion 5b are formed, a catalyst portion is formed by the ink jet method described above (S28). The wiring board formed in this step is shown in FIG. Since the dielectric part 5a and the insulating part 5b are formed in a concave groove shape by the above-described ink jet method, the catalyst part has a direction opposite to the direction of the via conductive parts 4a and 4b (the dielectric part 5a and the insulating part 5b). There is no overflow in the outer direction of the portion 5b. On the contrary, the direction of the via conductive parts 4a and 4b (the inner direction of the dielectric part 5a and the insulating part 5b) needs to be formed with the wiring parts 6a and 6b.

  When the catalyst portion is formed, the wiring portions 6a and 6b are formed by electroless plating (S29). A wiring board formed in this step is shown in FIG. Wiring portions 6a and 6b are formed by plating at the portion where the catalyst portion is formed, and at the same time, a decoupling capacitor is formed between the wiring portion 6a and the substrate 2.

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Silicon substrate 3a, 3b Via insulation part 4a, 4b Via conductive part 5a Dielectric part 5b Insulation part 6a, 6b Wiring part 7a, 7b Via 10 Inkjet 11 Insulator discharge part 12 Catalyst discharge part 13 Discharge control part 14 Dielectric Body discharging part 30 Plating part 32 Head 33 Insulating wiring 33a Insulating ink 34 Catalyst part 34a Catalyst ink 35 Catalyst part (Pd ⁰ )
36 Plating Layer 37 Deep-UV Device 38 Ultraviolet Exposure Device 50 Movement Control Unit 60 Drive Unit 70 Drawing Information 100 Inkjet Device

Claims (8)

In a wiring board forming method for forming a wiring board on which a circuit element is placed on at least one side surface of a conductive silicon substrate,
Inside the first via formed in the silicon substrate, a cylindrical first via insulating portion that covers and covers the entire surface from one side surface to the other side surface of the silicon substrate, and in the first via insulating portion Forming a first via conductive portion in which a conductive material having conductivity is enclosed;
On the other side surface of the silicon substrate, an insulating material that is stacked at least in the peripheral region of the first via conductive portion and is connected over the entire circumference of the cylindrical end portion of the first via insulating portion is extended. A dielectric portion forming step for forming the dielectric portion;
Forming a first wiring portion that is laminated on the surface of the dielectric portion and connected to the first via conductive portion; and
The wiring substrate, wherein the first wiring portion is connected to a power source, the silicon substrate is connected to a ground, and a capacitor sandwiching the dielectric portion between the first wiring portion and the silicon substrate is formed. Forming method.
In the wiring board formation method according to claim 1,
The via forming step, the inside of the second via formed in the silicon substrate, the second via insulating portion cylindrical to the other side surface of the side entire surface from one side to the insulating coating of the silicon substrate, and the Forming a second via conductive portion in which a conductive material having conductivity is enclosed in the second via insulating portion;
On the other side surface of the silicon substrate, the insulating material is extended so as to be stacked at least in a peripheral region of the second via conductive portion so that at least a part thereof does not contact the cylindrical end portion of the second via insulating portion Including an insulating part forming step of forming an insulating part,
The wiring forming step forms a second wiring part formed on the surface of the insulating part and connected to the second via conductive part and the silicon substrate,
The wiring substrate forming method, wherein the second wiring portion is connected to a ground, and a capacitor is formed that sandwiches the dielectric portion between the first wiring portion and the silicon substrate.
In the wiring board formation method according to claim 2,
In the dielectric part forming step and the insulating part forming step, a droplet of the insulating material is ejected by an inkjet method to form a cross-sectional groove shape,
Including a catalyst forming step of discharging droplets serving as a catalyst for electroless plating by the ink-jet method into the groove having a cross-sectional groove shape of the insulating material;
The wiring board forming method, wherein the wiring forming step forms the first wiring part and the second wiring part on the surface of the catalyst by electroless plating. In the wiring board formation method according to claim 3,
A method of forming a wiring board, wherein the droplets of the insulating material are droplets that become liquid repellent with the first conductive portion and the second conductive portion formed in the via. In the wiring board formation method of Claim 4,
After the dielectric portion forming step and the insulating portion forming step, a cleaning step of cleaning droplets of the insulating material applied to the surfaces of the first conductive portion and the second conductive portion is included. A wiring board forming method. In the wiring board formation method in any one of Claim 2 thru | or 5,
Insulating droplets discharged in the dielectric portion forming step are dielectrics, and insulating droplets discharged in the insulating portion forming step are insulators,
The wiring substrate forming method, wherein the dielectric and the insulator are discharged from different discharge ports in one step. In the wiring board on which the circuit element is placed on at least one side surface of the board,
The surface of at least the other side surface of the substrate has conductivity,
A first via insulating portion formed in a cylindrical shape by insulatively covering the entire surface from one side of the substrate to the other side from the inside of the first via formed in the substrate;
A first via conductive portion formed by encapsulating a conductive material having conductivity in the first via insulating portion;
On the other side surface of the substrate, an insulating material that is stacked at least in the peripheral region of the first via conductive portion and is connected over the entire circumference of the cylindrical end portion of the first via insulating portion is extended. A dielectric part to be formed;
A first wiring part formed on the surface of the dielectric part and connected to the first via conductive part;
The wiring board, wherein the substrate is connected to a ground, and a capacitor sandwiching the dielectric portion between the first wiring portion and the substrate is formed. The wiring board according to claim 7,
A cylindrical second via insulating part that covers and covers the entire surface from one side surface of the substrate to the other side surface inside the second via formed in the substrate;
A second via conductive portion in which a conductive material having conductivity is enclosed in the second via insulating portion;
On the other side surface of the substrate, an insulating material is extended so that at least a part is not in contact with the cylindrical end portion of the second via insulating portion, which is stacked at least around the second via conductive portion. An insulating part formed by
A second wiring portion formed on the surface of the insulating portion and connected to the second via conductive portion and the substrate;
The wiring board, wherein the second via conductive portion is connected to a ground, and a capacitor is formed that sandwiches the dielectric portion between the first wiring portion and the substrate.

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