JP5540723B2 - Thin film transistor manufacturing method - Google Patents

Description

The present invention relates to the production how a thin film transistor capacitor having a LDD (lightly-doped-drain) region formed respectively between the channel region and the source region and the drain region.

  Thin film transistors using semiconductor thin films are widely used in the fields of liquid crystal display devices and the like.

  Since the semiconductor thin film used for the active layer of this thin film transistor is formed by the CVD method, it mainly has an amorphous structure or a polycrystalline structure. Therefore, grain boundaries and local defects are formed in the active layer of the thin film transistor, which lowers the carrier mobility and restricts the on-current of the thin film transistor.

  In order to solve this problem, as a technique for improving mobility, defect passivation by hydrogen plasma treatment, crystallization by laser annealing or heat treatment, and the like have been proposed.

  However, when these semiconductor thin films are crystallized uniformly, the leakage current of the thin film transistor increases, deteriorating the product characteristics. The causes of the deterioration of the leakage characteristics are caused by the enhancement of the high electric field effect by improving the carrier mobility in the LDD region and the decrease in the defect level of the LDD region that functioned as the center of photogenerated carrier recombination. It is estimated that Here, the LDD region is a region in which the electric field concentration is reduced by reducing the impurity concentration in the vicinity of the position corresponding to the end surface on the gate electrode side of the active layer.

  In view of the above situation, Patent Document 1 proposes a method of separately forming silicon grain sizes in a peripheral circuit portion and a pixel portion in a method for forming a thin film transistor used in a liquid crystal display device.

WO03 / 105236 pamphlet

  The technique described in Patent Document 1 obtains a silicon particle size within an allowable range in a peripheral circuit portion that has a large influence on on-current and a pixel portion that has a large influence on leakage current. . However, this method cannot ensure a sufficient on-current of the pixel portion. Therefore, for example, it becomes difficult to cope with recent high-speed panel drive in a liquid crystal display device.

  Although it is conceivable to increase the silicon particle size in the pixel portion, if the particle size is increased to the LDD region at this time, the total leakage current including the light leakage is increased. Become.

Accordingly, the present invention for such problems, while maintaining the leakage characteristics, and an object thereof is to provide a manufacturing how a thin film transistor motor which can significantly improve the on-current.

  In order to achieve the above-mentioned object, the invention according to claim 1 is a method of manufacturing a thin film transistor, comprising: a step of forming a semiconductor thin film; and an inert property of the semiconductor thin film that does not affect electrical characteristics of the semiconductor thin film. A step of implanting ions, a step of forming a mask on the LDD formation region located between the channel formation region, the source formation region and the drain formation region, and a semiconductor thin film on which the mask is formed on the LDD formation region And the step of implanting inert ions that do not affect the electrical characteristics of the semiconductor thin film, and the step of crystallizing the semiconductor thin film by heat treatment.

  According to the present invention, the particle size can be independently controlled in the LDD region and the channel region. As a result, the leakage characteristics and on-current of the thin film transistor can be made independent and improved, and the trade-off between leakage and on is greatly improved. By improving the on-current, it becomes possible to drive a semiconductor product using such a thin film transistor at a high speed. That is, it is possible to cope with high-speed panel driving. In addition, by reducing the leakage current, it is possible to improve a leakage characteristic defect represented by, for example, flicker and crosstalk in a liquid crystal display device.

It is explanatory drawing which showed typically an example of the whole structure of the thin-film transistor which concerns on one embodiment of this invention. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows an example of the manufacturing process of the thin-film transistor shown in FIG. It is explanatory drawing which shows the band profile of the thin-film transistor shown in FIG. 2 is a graph showing static characteristics in a high electric field state in the thin film transistor shown in FIG. 1. 3 is a graph showing measurement results of surface flicker in the thin film transistor shown in FIG. 1.

  The thin film transistor according to this embodiment includes a semiconductor thin film having a channel region formed below a gate electrode, and an LDD (Lightly Doped Drain) region formed between the channel region and a source region and a drain region, respectively. I have. The LDD region is a region having a carrier concentration lower than that of the source region and the drain region, and the impurity concentration in the vicinity of the position corresponding to the end surface on the gate electrode side of the active layer is reduced to reduce the electric field concentration.

  The crystal grain size of the LDD region is made smaller than the average crystal grain size of the semiconductor thin film, and the crystal grain size of the channel region is made larger than the average crystal grain size of the semiconductor thin film. .

  By using the thin film transistor having such a structure, an on-current can be improved and a semiconductor device such as a liquid crystal display element can be driven at high speed. In addition, by reducing the leakage current, it is possible to improve a leaky characteristic defect typified by flicker and crosstalk in a liquid crystal display device using a liquid crystal display element.

A semiconductor device in which such a thin film transistor is formed can be realized by a manufacturing method having the following steps.
(1) A step of forming a semiconductor thin film.
(2) A step of implanting inactive ions that do not affect the electrical characteristics of the semiconductor thin film into the semiconductor thin film.
(3) A step of forming a mask on the LDD formation region located between the channel formation region and the source formation region and the drain formation region.
(4) Implanting inactive ions that do not affect the electrical characteristics of the semiconductor thin film onto the semiconductor thin film in which a mask is formed on the LDD formation region.
(5) A step of crystallizing the semiconductor thin film by heat treatment.

Hereinafter, a thin film transistor, a manufacturing method thereof, and a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. The description will be given in the following order. Although a thin film transistor formed in a liquid crystal display element which is one of semiconductor devices will be described as an example here, the present invention can naturally be applied to a solid-state imaging element and other semiconductor devices.
1. 1. Configuration of thin film transistor 2. Manufacturing method of thin film transistor Thin film transistor characteristics

[1. Configuration of Thin Film Transistor]
FIG. 1 is an explanatory view schematically showing an example of the configuration of a thin film transistor for pixels (hereinafter also referred to as “pixel TFT”) which is a thin film transistor according to an embodiment of the present invention. As shown in the figure, a pixel TFT has a gate insulating film mainly composed of a semiconductor thin film made of a patterned active layer 12 and a silicon oxide film on a substrate 11 on which an interlayer insulating film for suppressing impurity diffusion is formed. The film 13 and the gate electrode 14 are sequentially stacked. In the figure, reference numeral 15 denotes an interlayer insulating film, and reference numeral 16 denotes a source / drain electrode. For example, a transparent insulating substrate such as a quartz substrate is used as the substrate 11, but in the case of a semiconductor device such as a solid-state imaging device, for example, an interlayer insulating film that suppresses impurity diffusion is formed on the surface. A semiconductor substrate is used.

  Here, the active layer 12 is formed of polysilicon which is a semiconductor thin film, but other semiconductor thin films such as germanium may be used. The active layer 12 has a channel region 20 formed below the gate electrode 14, and a source region 21 and a drain region 22. In the active layer 12, LDD (Lightly Doped Drain) regions 23 are formed between the channel region 20 and the source region 21 and drain region 22, respectively. The LDD region 23 is a region where the carrier concentration is lower than the carrier concentration of the source region 21 and the drain region 22 and the electric field concentration is reduced.

  In the pixel TFT according to this embodiment, the crystal grain size of the channel region 20, the source region 21, and the drain region 22 is set to a large grain size region 40 that is larger than the average crystal grain size of the active layer 12. For example, the crystal grain size is about 800 nm. Furthermore, the crystal grain size of the LDD region 23 is set to a small grain size region 41 that is smaller than the average crystal grain size of the active layer 12. For example, the crystal grain size is 300 nm or less.

  Thus, by dividing the crystal grain size of the active layer 12 into the large grain size region 40 and the small grain size region 41, the leakage current is suppressed without significantly improving the carrier mobility of the LDD region 23. However, the on-current characteristics of the pixel TFT can be improved.

  In addition, taking advantage of such characteristics improvement, the liquid crystal display element including the pixel TFT according to the present embodiment can be driven at high speed, and the leakage current is reduced, which is typified by flicker and crosstalk. It is possible to improve the leaky characteristic defect.

[2. Manufacturing method of thin film transistor (TFT)]
The pixel TFT having the above-described configuration is obtained through the steps shown in FIGS. 2A to 2H. That is, first, a semiconductor thin film is formed. As shown in FIG. 2A, a polycrystalline silicon film (hereinafter referred to as “polysilicon film”) 12a is formed on a substrate 11 made of synthetic quartz or the like.

Next, in the step of implanting the same kind of inactive ions into the polysilicon film 12a, as shown in FIG. 2B, a suitable amount of inactive ions that do not affect the electrical characteristics as the active layer is added to the polysilicon. By ion implantation into the film 12a, the film is converted into a homogeneous amorphous silicon film 12b. Examples of the inert ions that do not affect the electrical characteristics include Si + ions, and are implanted by, for example, an ion implantation apparatus. In addition, SiF3 + ions can also be used. The injection amount at this time can be adjusted so that a desired crystal grain size can be obtained after solid phase growth. In the present embodiment, the ion implantation amount is 4 × 10 ¹⁴ atoms / cm ^{2 and} the average crystal grain size of the polycrystalline silicon film after the solid phase growth is adjusted to be about 100 nm. The acceleration energy of Si + ions is set to 30 keV to 50 keV.

  Next, a mask is formed on the LDD formation region 23a located between the channel formation region 20a, the source formation region 21a, and the drain formation region 22a. That is, as shown in FIG. 2C, a mask 31 is formed with a resist on the LDD formation region 23a of the amorphous silicon film 12b where the LDD region 23 is to be formed later.

The step of implanting the same kind of inactive ions from the amorphous silicon film 12b in which the mask 31 is formed on the LDD formation region 23a is the next step. In this step, as shown in FIG. 2D, an appropriate amount of inactive ions that do not affect the electrical characteristics of the active layer is ion-implanted through the mask 31 into the amorphous silicon film 12b. Examples of the inert ions that do not affect the electrical characteristics include Si + ions, and are implanted by, for example, an ion implantation apparatus. In addition, SiF3 + ions can also be used. At this time, the sum of the implantation amount in this step and the implantation amount in the previous step (see FIG. 2C) provides a desired crystal grain size in a region other than the LDD region 23 and a peripheral transistor (not shown) after solid phase growth. Adjust as follows. In the present embodiment, solid phase growth is performed so that the sum of the implantation amount in the previous step (see FIG. 2C) and the implantation amount in the present step (see FIG. 2D) is about 1.2 × 10 ¹⁵ atms / cm ^2. The average crystal grain size of the subsequent polycrystalline silicon film is set to about 800 nm. The acceleration energy of this step (see FIG. 2D) is set to 30 keV to 50 keV as in the previous step (see FIG. 2C).

  Next, as a step of recrystallizing the amorphous silicon film 12b by heat treatment, the mask 31 is removed and solid phase growth is performed on the amorphous silicon film 12b by annealing at about 600 ° C. to 650 ° C. As shown in 2E, an active layer 12 formed into polycrystalline silicon is obtained.

  At this time, as shown in the figure, the portion where the mask 31 is not formed and the ion implantation amount is large is made larger than the polysilicon film 12a shown in FIGS. Is formed. Reference numeral 41 indicates a small particle size region formed at a location where the ion implantation amount is small, and the particle size is smaller than that of the large particle size region 40. Note that the large grain size region 40 coincides with the channel formation region 20a, the source formation region 21a, and the drain formation region 22a, and becomes the channel region 20, the source region 21, and the drain region 22 in a later process. On the other hand, the small particle size region 41 coincides with the LDD formation region 23a and becomes the LDD region 23 in a later process.

After the active layer 12 is formed, as shown in FIG. 2F, a gate insulating film 13 mainly composed of a silicon oxide film is formed on the active layer 12, and a gate electrode 14 is formed. The gate electrode 14 can be formed by adding P (phosphorus) and using polysilicon having an N-type conductivity or a metal having a relatively high melting point such as Mo, Ta, or Cr. Then, using this gate electrode 14 as a mask, low concentration ion implantation is performed using an ion implantation apparatus. By this step, a low concentration N-type conductive region is formed. In this low-concentration ion implantation step, ion species such as P + and As having an impurity concentration per unit area of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² are implanted using an ion implantation apparatus. N-type conductive regions are formed.

Next, as shown in FIG. 2G, a photoresist 32 is formed, and using this photoresist 32 as a mask, high concentration ion implantation is performed using an ion implantation apparatus to form a high concentration N-type impurity region. As a result, a channel region 20, a source region 21, a drain region 22, and an LDD region 23 are formed. In this high-concentration ion implantation step, ion species such as P + and As + having an impurity concentration per unit area of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² are implanted using an ion implantation apparatus. N-type conductive regions are formed.

After removing the photoresist 32, as shown in FIG. 2H, an interlayer insulating film 15 mainly composed of the same silicon oxide film as that of the gate insulating film 13 is formed and heat-treated using an arc furnace or the like to be active layer 12 To diffuse impurities. In this embodiment, a Furnace type batch furnace is used for this heat treatment, and a process at about 1000 ° C. is performed for several minutes to several tens of minutes in an N ₂ atmosphere. In addition to the heat treatment of the Furnace type batch furnace, heat treatment by RTA (Rapid Thermal Anneal), heat treatment by ELA (Exima Laser Anneal), or a combination thereof may be performed.

  Thereafter, a metal as an electrode material is formed, and patterning is performed using a photolithography technique, whereby the source / drain electrodes 16 and 16 are formed, and the pixel TFT shown in FIG. 1 can be obtained. After this, although explanation is omitted, there are processes such as formation of an interlayer insulating film, hydrogenation, contact opening, formation of a common electrode, contact opening, and extraction of a pixel electrode.

  As described above, in the manufacturing method of the pixel TFT according to the present embodiment, inert ions that do not affect the electrical characteristics of the semiconductor thin film are implanted through the mask 31 before annealing. The channel region 20, the source region 21, and the drain region 22 are a large particle size region 40, and the LDD region 23 is a small particle size region 41. For example, when germanium is used as the active layer 12, germanium ions are used as inert ions that do not affect the electrical characteristics of the active layer.

[3. Characteristics of thin film transistor]
In general, when light enters the LDD region of a thin film transistor, electrons excited from the valence band to the conduction band tend to flow into the drain according to the potential gradient. Therefore, this process is avoided by the process of “electron capture → recombination” by the localized level to suppress light leakage. However, conventionally, since the localized levels exist uniformly over the channel region, the source region, the drain region, and the LDD region, the ON current has been greatly reduced.

  On the other hand, the pixel TFT according to the present embodiment, as can be seen from the band profile shown in FIG. Maintaining the "joining" process. In FIG. 3, Ev indicates the upper end of the valence band, and Ec indicates the lower end of the conduction band.

  In addition, since the channel region 20, the source region 21, and the drain region 22 are large particle size regions 40, the electron mobility is higher than that in the prior art, and a decrease in on-current can be suppressed.

  That is, as shown in FIG. 4, in the pixel TFT (TEST) according to this embodiment, the characteristics of the weak inversion region are dramatically improved by increasing the crystal grain size of the channel region 20. The on-current can be improved more than twice as compared with TFT (Ref.). In addition, it has been found that the rising characteristics are improved and the operation is performed with a low threshold voltage (Vth).

  As described above, the pixel TFT according to the present embodiment can improve the on-current while maintaining the leakage characteristics as compared with the conventional case. For this reason, in the pixel TFT according to the present embodiment, the writing capability of the pixel potential is greatly improved.

  Further, as shown in FIG. 5, the measurement result of the surface flicker of the pixel TFT (TEST) according to the present embodiment is the same as that of the conventional TFT (Ref.), And it is understood that the increase tendency of the light leak is not seen. It was.

  When the above-described pixel TFT is applied to a liquid crystal display element, a sufficient on-current of the pixel portion can be secured, so that it is possible to improve leakage characteristic defects such as flicker and crosstalk. Therefore, for example, it is possible to easily cope with recent panel high-speed driving in a liquid crystal display device.

  Although the present invention has been described through the above-described embodiments, the present invention can be implemented in other forms with various modifications and improvements based on the knowledge of those skilled in the art. For example, in the above-described embodiment, an N-channel thin film transistor has been described as an example, but a P-channel TFT may be used. Further, as described above, the above-described thin film transistor has been described by taking a pixel TFT used in a liquid crystal display element as an example, but the present invention is not limited to this, and can naturally be applied to a solid-state imaging element and other semiconductor devices. .

DESCRIPTION OF SYMBOLS 11 Substrate 12 Active layer 14 Gate electrode 16 Source / drain electrode 20 Channel region 20a Channel formation region 21 Source region 21a Source formation region 22 Drain region 22a Drain formation region 23 LDD region 23a LDD formation region 40 Large particle size region 41 Small particle size region

Claims (1)

Forming a semiconductor thin film;
Implanting inert ions that do not affect the electrical properties of the semiconductor thin film into the semiconductor thin film;
Forming a mask on the LDD formation region located between the channel formation region and the source formation region and the drain formation region;
Implanting inert ions that do not affect the electrical characteristics of the semiconductor thin film onto the semiconductor thin film having a mask formed on the LDD formation region;
And a step of crystallizing the semiconductor thin film by heat treatment .

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