JP5538828B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a split gate type memory cell and a technique effective when applied to the manufacturing thereof.

  As a semiconductor device, for example, a semiconductor device having a nonvolatile semiconductor memory element that can be electrically written and erased is known. Further, as a memory cell structure of a nonvolatile semiconductor memory element, for example, a split gate type memory cell in which a selection MIS (Metal Insulator Semiconductor) transistor and a memory MIS transistor are connected in series is known.

  Among the split gate type memory cells, in particular, the gate electrode of the memory MIS transistor (hereinafter referred to as the memory gate electrode) is applied to the side wall of the gate electrode (hereinafter referred to as the control gate electrode) of the selected MIS transistor using a self-alignment technique. The arranged memory cell structure can reduce the gate length of the memory gate electrode to less than the minimum resolution dimension of lithography, so that the selection gate and the memory gate are individually formed by etching using a photoresist film as a mask. It is known that a fine memory cell can be realized.

  Of the two types of MIS transistors constituting the split gate type memory cell, the memory MIS transistor stores information by holding charges in its gate insulating film. There are two types. One is a floating gate method using a conductive polycrystalline silicon film that is electrically isolated as a part of the gate insulating film, and the other is an insulating material having a property of accumulating electric charges like a silicon nitride film. This is a MONOS (Metal Oxide Nitride Oxide Semiconductor) system that stores charges in the film.

  In either of the two types of charge holding methods described above, a silicon oxide film having excellent insulating properties is inserted as a potential barrier film between the insulating film (silicon nitride film) for accumulating charges and the semiconductor substrate. For example, in the MONOS method, a three-layer stacked insulating film called an ONO film in which a charge holding film is sandwiched between two silicon oxide films is used. In the floating gate method, when a local leak path is generated in the potential barrier film, the charge in the charge holding film leaks to the substrate side through the leak path, so that the charge cannot be held. On the other hand, in the MONOS method, since charges are accumulated at discrete trap levels in the charge holding film and the charges are spatially discretized and held, only the charges around the leak path leak. Therefore, there is an advantage that there is no extreme decrease in the charge retention life.

  For example, Patent Documents 1 to 4 describe a semiconductor device having a split gate type memory cell.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2008-159650) discloses a memory cell in which the upper portions of a memory gate electrode and a control gate electrode are silicided, and the upper portion between the memory gate electrode and the ONO film is covered with an electrical insulating layer. The structure to be disclosed is disclosed. According to this structure, since the distance between the upper part of the memory gate electrode and the upper part of the control gate electrode is longer than the distance corresponding to the film thickness of the ONO film, the gate electrode is silicided even if the memory cell is miniaturized. Short-circuiting between the gate electrodes due to the residue of the metal layer used at the time hardly occurs.

  Patent Document 2 (Japanese Patent Laid-Open No. 2008-294088) discloses that an ONO film interposed between a memory gate electrode and a control gate electrode is replaced with a normal ONO film (two silicon oxide films and a silicon nitride film interposed therebetween). ), A structure constituted by a four-layer film in which an insulating film (for example, a silicon nitride film having a thickness of 5 to 20 nm) is stacked is disclosed. According to this structure, when the polycrystalline silicon film for the memory gate electrode is etched, the insulating film functions as an etching stopper layer, and the ONO film is prevented from being damaged. Therefore, deterioration of the charge retention characteristics of the memory cell can be avoided. Can do.

  In Patent Document 3 (Japanese Patent Laid-Open No. 2007-109800), when siliciding the upper portions of the memory gate electrode and the control gate electrode, the memory gate electrode is formed lower than the ONO film, and the ONO on the upper portion of the memory gate electrode is formed. A technique for preventing a short circuit between gate electrodes by forming a sidewall insulating film (sidewall spacer) on the side surface of the film is disclosed.

  In Patent Document 4 (Japanese Patent Laid-Open No. 2007-258497), a bird's beak-shaped insulating film is formed between the upper portion of the memory gate electrode and the upper portion of the control gate electrode, and the distance between the upper portion of the memory gate electrode and the control gate electrode. Discloses a technique for avoiding a short circuit between the gate electrodes by making the length longer than the distance between the control gate electrode and the semiconductor substrate.

JP 2008-159650 A JP 2008-294088 A JP 2007-109800 A JP 2007-258497 A

  The above-described split gate type memory cell has a structure in which a side wall-like memory gate electrode is disposed on one side wall of a control gate electrode via a stacked gate insulating film in which a charge holding film is sandwiched between two potential barrier films. Thus, miniaturization of the memory cell is realized. However, with the miniaturization, the distance between the control gate electrode and the memory gate electrode becomes closer. The control gate electrode and the memory gate electrode are formed of a polysilicon film, and both have a silicide layer formed on the surface of the control gate electrode and the surface of the memory gate electrode in order to reduce the resistance. . In this case, since the surface of the control gate electrode and the surface of the memory gate electrode are separated from each other only by the stacked gate insulating film, the silicide layer formed on the control gate electrode and the silicide layer formed on the memory gate electrode There is a possibility that the control gate electrode and the memory gate electrode are short-circuited due to contact.

  As a countermeasure, for example, in Patent Document 4, an effective distance between the upper portions of the two gate electrodes is increased by forming a bird's beak-shaped insulating film between the upper portion of the memory gate electrode and the upper portion of the control gate electrode. doing. However, in order to form a bird's beak-shaped insulating film between the upper portion of the memory gate electrode and the upper portion of the control gate electrode, a step of heat-treating the semiconductor substrate at a high temperature is required. Therefore, in this method, there is a problem that re-diffusion of impurities in the semiconductor substrate occurs during the heat treatment of the semiconductor substrate, and the operation characteristics are likely to vary particularly in a fine memory cell.

  Another problem is that the stacked gate insulating film formed between the upper part of the memory gate electrode and the upper part of the control gate electrode is damaged by ion implantation or the like when forming the source / drain regions. The insulation resistance between the gate electrode and the control gate electrode may be deteriorated.

  An object of this embodiment is to improve the reliability of a semiconductor device. The main ones of the objects described in this embodiment will be exemplified below.

  One of the main objects of the present embodiment is that in a semiconductor device having a split gate type memory cell, the silicide layer formed on the surface of the control gate electrode of the split gate type memory cell and the surface of the memory gate electrode An object of the present invention is to provide a technique for preventing a short-circuit failure caused by contact of a formed silicide layer.

  Another main object of the present embodiment is to provide a technique for maintaining insulation resistance between a memory gate electrode and a control gate electrode in a semiconductor device having a split gate type memory cell.

  The above and other objects and novel features of the present embodiment will become apparent from the description of the present specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A semiconductor device which is a preferable aspect of the present embodiment is a semiconductor device having a memory cell, and the memory cell includes a first gate insulating film formed on a semiconductor substrate, and the first gate. A control gate electrode formed on the semiconductor substrate via an insulating film, a first gate formed on one side wall of the control gate electrode and on the semiconductor substrate, and formed in order from the control gate electrode side A second gate insulating film having a stacked structure of a potential barrier film, a charge holding film, and a second potential barrier film; and a memory gate electrode insulated from the control gate electrode and the semiconductor substrate via the second gate insulating film A source region composed of a semiconductor region formed in the semiconductor substrate in the vicinity of the control gate electrode, and a semiconductor region formed in the semiconductor substrate in the vicinity of the memory gate electrode. And a drain region made of the upper part of the control gate electrode and the memory gate electrode is a silicide layer is formed. Further, a sidewall insulating film is formed between the second gate insulating film formed on one side wall of the control gate electrode and the memory gate electrode, and the sidewall insulating film and the control gate electrode The sum of the thickness of the second potential barrier film formed on the side wall is larger than the thickness of the second potential barrier film formed below the memory gate electrode.

(2) A method for manufacturing a semiconductor device, which is a preferred embodiment of the present embodiment, is a method for manufacturing a semiconductor device having the configuration of (1) above, and includes the following steps (a) to (k). It is a waste.
(A) forming a well in the semiconductor substrate;
(B) forming a first gate insulating film on the semiconductor substrate;
(C) forming a control gate electrode on the first gate insulating film;
(D) After the step (b), a first potential barrier film, a charge holding film, and a second potential barrier film are sequentially formed on the semiconductor substrate, and the first potential barrier film, the charge holding film, and Forming a second gate insulating film comprising a laminated film of the second potential barrier film;
(E) depositing a first insulating film on the second gate insulating film;
(F) forming a sidewall insulating film made of the first insulating film on both side walls of the control gate electrode by patterning the first insulating film;
(G) After the step (f), a step of depositing a first conductive film on the semiconductor substrate;
(H) forming a memory gate electrode made of the first conductive film on both side walls of the control gate electrode by patterning the first conductive film;
(I) patterning the memory gate electrode, the sidewall insulating film, and the second gate insulating film to leave the memory gate electrode and the sidewall insulating film only on one sidewall of the control gate electrode; Leaving two gate insulating films on one side wall of the control gate electrode and below the memory gate electrode;
(J) After the step (i), by introducing impurities into the semiconductor substrate, a source region is formed in the semiconductor substrate in the vicinity of the control gate electrode, and in the semiconductor substrate in the vicinity of the memory gate electrode Forming a drain region;
(K) forming a silicide layer on the control gate electrode and the memory gate electrode;
Including
The sum of the film thicknesses of the sidewall insulating film and the second potential barrier film formed on the sidewall of the control gate electrode is larger than the film thickness of the second potential barrier film formed below the memory gate electrode. It is characterized by being thick.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  According to this embodiment, the reliability of the semiconductor device can be improved.

1 is a plan view of a principal part showing a memory array of a semiconductor device according to a first embodiment of the present invention; It is a principal part expanded sectional view along the AA line of FIG. FIG. 3 is an enlarged cross-sectional view showing a main part of the memory cell of FIG. 2. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 8; FIG. 9 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a method for manufacturing the semiconductor device following FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 10; FIG. 11 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a method for manufacturing the semiconductor device following FIG. 10; It is a principal part expanded sectional view of the semiconductor substrate which shows another example of the manufacturing method of a semiconductor device. It is a principal part expanded sectional view of the semiconductor substrate which shows another example of the manufacturing method of a semiconductor device. FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 12; FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 18; FIG. 19 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a method for manufacturing the semiconductor device following FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 19; FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 21; FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 22; FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 23; FIG. 24 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 23; FIG. 25 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 24; FIG. 25 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a method for manufacturing the semiconductor device following FIG. 24; FIG. 27 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 26; FIG. 27 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a method for manufacturing the semiconductor device following FIG. 26; FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 28; FIG. 29 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 28; FIG. 31 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 30; FIG. 31 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 30; FIG. 33 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 32; FIG. 33 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a method for manufacturing the semiconductor device following FIG. 32; It is a principal part expanded sectional view of the semiconductor substrate which shows another example of the manufacturing method of a semiconductor device. It is a principal part expanded sectional view which shows the memory cell of the semiconductor device which is Embodiment 2 of this invention. FIG. 38 is a cross-sectional view showing the memory cell of FIG. 37 in a further enlarged manner. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 40 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 39; FIG. 41 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 40; FIG. 42 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 41; FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 42; FIG. 44 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 43; FIG. 44 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a method for manufacturing the semiconductor device following FIG. 43; FIG. 45 is a main part cross-sectional view of the semiconductor substrate, showing the method for manufacturing the semiconductor device following FIG. 44; FIG. 45 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a method for manufacturing the semiconductor device following FIG. 44; FIG. 47 is a main-portion cross-sectional view of the semiconductor substrate, illustrating the manufacturing method of the semiconductor device following FIG. 46; FIG. 49 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 48; FIG. 50 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method of the semiconductor device following FIG. 49; FIG. 52 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 50; FIG. 52 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 51; FIG. 53 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 52; FIG. 54 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 53; FIG. 55 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 54; FIG. 56 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor device following FIG. 55; It is a principal part expanded sectional view of the semiconductor substrate which shows another example of the manufacturing method of a semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. Further, in the drawings for explaining the following embodiments, hatching may be given even in a plan view for easy understanding of the configuration.

(Embodiment 1)
1 is a plan view of a principal part showing a memory array of a semiconductor device according to the present embodiment, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 shows a memory cell in FIG. It is a principal part expanded sectional view.

The semiconductor device of this embodiment has a split gate type memory cell as a memory cell. FIG. 2 shows an extension of a bit line (BL) among a plurality of memory cells formed in a memory array on a silicon substrate. Two memory cells (MC ₁ , MC ₂ ) adjacent in the current direction are shown.

Each of the memory cells (MC ₁ , MC ₂ ) includes, for example, one selection MIS transistor and one memory MIS formed in a p-type well 4 of a p-type single crystal silicon substrate 1 (hereinafter simply referred to as a substrate). It consists of a transistor.

  The selection MIS transistor includes a gate insulating film (first gate insulating film) 7 formed on the surface of the p-type well 4 and a control gate electrode 8 formed on the gate insulating film 7. The gate insulating film 7 of the selection MIS transistor is made of, for example, a silicon oxide film, and the control gate electrode 8 is made of an n-type polycrystalline silicon film doped with phosphorus (P).

  The memory MIS transistor has an L-shaped laminated gate insulating film 9 partly formed on one side wall of the control gate electrode 8 and the other part formed on the surface of the p-type well 4, and the control gate electrode 8. And a memory gate electrode 10 that is electrically separated from the control gate electrode 8 and the p-type well 4 through the laminated gate insulating film 9.

  The stacked gate insulating film 9 of the memory MIS transistor includes a first potential barrier film 9a, a second potential barrier film 9c, and a charge holding film 9b formed therebetween. The first potential barrier film 9 a and the second potential barrier film 9 c are formed of, for example, a silicon oxide film, and function as a gate insulating film formed between the memory gate electrode 10 and the substrate 1.

  The potential barrier films (9a, 9c) made of the silicon oxide film also have a function as a tunnel insulating film. For example, the memory unit of the memory cell stores and erases information by injecting electrons from the substrate 1 into the charge holding film 9b through the first potential barrier film 9a or injecting holes into the charge holding film 9b. Therefore, the first potential barrier film 9a functions as a tunnel insulating film. The charge holding film 9b formed on the first potential barrier film 9a has a function of holding charges. Specifically, in the present embodiment, the charge holding film 9b is formed from a silicon nitride film.

  The memory gate electrode 10 is made of an n-type polycrystalline silicon film. Although not shown, the control gate electrode 8 is connected to the selection gate line, and the memory gate electrode 10 is connected to the word line.

In the p-type well 4 in the vicinity of the control gate electrode 8, an n ⁺ -type semiconductor region 17d that functions as a drain region common to _two memory cells (MC ₁ , MC ₂ ) is formed. The n ⁺ type semiconductor region 17d is connected to the bit line BL. The bit line BL is formed on the interlayer insulating film 23 that covers the memory cells (MC ₁ , MC ₂ ), and the plug 31 in the contact hole 24 formed in the interlayer insulating film 23 and the insulating film 22 therebelow is connected to the bit line BL. And is electrically connected to the n ⁺ type semiconductor region 17d. The bit line BL is made of a metal film mainly composed of Cu (copper), for example, and the plug 31 is made of a metal film mainly composed of W (tungsten), for example. The interlayer insulating film 23 is made of, for example, a silicon oxide film as an insulating film, and the underlying insulating film 22 is made of, for example, a silicon nitride film as an insulating film.

In the p-type well 4 in the vicinity of the memory gate electrode 10, an n ⁺ -type semiconductor region 17s that functions as a source region of the memory cell is formed. The n ⁺ type semiconductor region 17s is connected to the common source line SL. The common source line SL shown in FIG. 1 includes an n ⁺ type semiconductor region 17s formed in the p-type well 4, and is formed integrally with the source region.

An n ⁻ type semiconductor region 13d having an impurity concentration lower than that of the n ⁺ type semiconductor region 17d is formed in the p type well 4 in a region adjacent to the n ⁺ type semiconductor region (drain region) 17d. The n ⁻ type semiconductor region 13d is an extension region for relaxing the high electric field at the end of the n ⁺ type semiconductor region 17d and making the selection MIS transistor have an LDD (Lightly Doped Drain) structure. Further, an n ⁻ type semiconductor region 13s having an impurity concentration lower than that of the n ⁺ type semiconductor region 17s is formed in the p type well 4 in a region adjacent to the n ⁺ type semiconductor region (source region) 17s. The n ⁻ type semiconductor region 13s is an extension region for relaxing the high electric field at the end of the n ⁺ type semiconductor region 17s and making the memory MIS transistor have an LDD structure.

For example, a Co (cobalt) silicide layer 18 is formed as a silicide layer on the surface of each of the control gate electrode 8, the memory gate electrode 10, and the n ⁺ -type semiconductor regions 17d and 17s. The Co silicide layer 18 is formed to reduce the resistance of each of the control gate electrode 8, the memory gate electrode 10, and the n ⁺ -type semiconductor regions 17d and 17s and operate the memory cells (MC ₁ and MC ₂ ) at high speed. Yes. Of course, the silicide layer may be composed of a nickel (Ni) silicide layer, a nickel silicide layer containing platinum (Pt), a titanium (Ti) silicide layer, etc. in addition to the Co silicide layer 18.

  As shown in FIG. 3, between the stacked gate insulating film 9 formed on one side wall of the control gate electrode 8 and the memory gate electrode 10, a side wall insulating film 11 made of, for example, a silicon oxide film is formed as an insulating film. Is formed. That is, the control gate electrode 8 and the memory gate electrode 10 are electrically separated from each other by the sidewall insulating film 11 and the laminated gate insulating film 9.

As described above, in the memory cell (MC ₁ , MC ₂ ) of the present embodiment, the sidewall insulating film 11 is provided between the stacked gate insulating film 9 formed on the sidewall of the control gate electrode 8 and the memory gate electrode 10. ing. As a result, as the memory cell size is reduced, the thickness of the stacked gate insulating film 9 is reduced, and even when the distance between the control gate electrode 8 and the memory gate electrode 10 approaches, the control gate electrode 8 Since the distance between the Co silicide layer 18 formed on the surface of the memory gate electrode 10 is increased, a short circuit between the control gate electrode 8 and the memory gate electrode 10 due to the contact of the Co silicide layer 18 can be reliably avoided. 1 effect.

On the other side wall of the control gate electrode 8 and one side wall of the memory gate electrode 10 (side wall opposite to the side wall in contact with the side wall insulating film 11), side wall insulation made of, for example, a silicon oxide film is used as an insulating film. A film 12 is formed. These sidewall insulating films 12 are formed to separate the control gate electrode 8 from the n ⁺ type semiconductor region 17d and the memory gate electrode 10 from the n ⁺ type semiconductor region 17s by a predetermined distance.

  Hereinafter, specifically, conditions of the sidewall insulating film 11 formed between the control gate electrode 8 and the memory gate electrode 10 are considered. As shown in FIG. 3, the sum of the thickness of the second potential barrier film 9c formed on one side wall of the control gate electrode 8 and the thickness of the side wall insulating film 11 is a, The film thickness of the second potential barrier film 9c formed on the side is defined as b. At this time, it is desirable to form the sidewall insulating film 11 so that the relationship of a> b is established. That is, the film thickness of the oxide film formed between the charge holding film 9b and the memory gate electrode 10 is set to the film thickness of the oxide film between the charge holding film 9b and the memory gate electrode 10 on the lower side of the memory gate electrode 10. It is desirable to form it thicker than the thickness. For example, in the case of a semiconductor device with a design rule of 90 nm, a = about 5 to 10 nm. The thickness of the second potential barrier film 9c is about 3 to 5 nm. As a result, the distance between the control gate electrode 8 and the memory gate electrode 10 is increased, so that the distance between the Co silicide layers 18 formed on the respective surfaces of the control gate electrode 8 and the memory gate electrode 10 is also increased. A short circuit between the control gate electrode 8 and the memory gate electrode 10 due to the contact of the silicide layer 18 can be reliably avoided.

  In FIG. 3, the film thickness a is shown as the sum of the film thickness of the second potential barrier film 9 c formed on one side wall of the control gate electrode 8 and the film thickness below the side wall insulating film 11. From the viewpoint of preventing a short circuit between the control gate electrode 8 and the memory gate electrode 10 due to contact of the Co silicide layer 18, the Co silicide layer 18 formed on the surface of the control gate electrode 8 and the surface of the memory gate electrode 10 are formed. It can be said that it is desirable that the relationship of a> b is also established with the Co silicide layer 18 formed. In this case, the film thickness a is the sum of the film thickness of the second potential barrier film 9 c formed on one side wall of the control gate electrode 8 and the film thickness on the side wall insulating film 11. In other words, the shortest distance from the interface between the charge retention film 9b and the second potential barrier film 9c to the Co silicide layer 18 in the region between the control gate electrode 8 and the memory gate electrode 10 is the substrate 1 and the memory gate electrode 10. Is formed so as to be larger than the distance from the interface between the charge holding film 9b and the second potential barrier film 9c to the memory gate electrode 10 in the region between the two.

Next, the operation of the memory cells (MC ₁ , MC ₂ ) will be briefly described. Here, injection of electrons into the charge holding film 9b is defined as “writing”, and injection of holes into the charge holding film 9b is defined as “erasing”.

First, the writing operation is performed by hot electron writing called a so-called source side injection method (source side injection method). At the time of writing, for example, the voltage applied to the n ⁺ -type semiconductor region (source region) 17s is 5V, the voltage applied to the memory gate electrode 10 is 10V, and the voltage applied to the control gate electrode 8 is 1V. The voltage applied to the n ⁺ type semiconductor region 17d is controlled so that the channel current at the time of writing becomes a certain set value. The voltage at this time is determined by the set value of the channel current and the threshold voltage of the selection transistor having the control gate electrode 8, and is about 0.5 V, for example. The voltage applied to the p-type well 4 (substrate 1) is 0V. By applying a gate overdrive voltage higher than that of the substrate 1 to the memory gate electrode 10, the channel under the memory gate electrode 10 is turned on. Here, the potential of the control gate electrode 8 is turned on by setting the potential higher than the threshold voltage.

As described above, the channel region formed between the source region and the drain region by applying a potential difference between the voltage applied to the n ⁺ type semiconductor region 17s and the voltage applied to the n ⁺ type semiconductor region 17d. Electrons flow through. At this time, electrons flowing through the channel are accelerated into hot electrons in the channel region near the boundary between the control gate electrode 8 and the memory gate electrode 10. Then, hot electrons are injected into the charge holding film 9 b under the memory gate electrode 10 by a vertical electric field by a positive voltage applied to the memory gate electrode 10. As a result, electrons are accumulated in the charge holding film 9b and the threshold voltage of the memory MIS transistor is increased. In this way, the write operation is performed.

The erasing operation is performed by, for example, BTBT (Band to Band Tunnel) erasing using a band-to-band tunnel phenomenon. At the time of BTBT erase, for example, the voltage applied to the memory gate electrode 10 is −6 V, the voltage applied to the n ⁺ type semiconductor region 17 s is 6 V, the voltage applied to the control gate electrode 8 is 0 V, and the n ⁺ type semiconductor region 17 d is Open. By causing strong inversion at the end of the n ⁺ type semiconductor region 17s, holes are generated by the band-to-band tunneling phenomenon. The holes generated by the high voltage applied to the n ⁺ type semiconductor region (source region) 17s are accelerated to become hot holes. The generated hot holes are attracted by the bias of the memory gate electrode 10 and injected into the charge holding film 9b, whereby the threshold voltage of the memory MIS transistor is lowered and an erasing operation is performed.

At the time of reading, for example, a voltage applied to the control gate electrode 8 is 1.5 V, a voltage applied to the n ⁺ type semiconductor region 17 d is 1 V, a voltage applied to the n ⁺ type semiconductor region 17 s is 0 V, and the memory gate electrode 10 is applied. The voltage is set to 0 V, and the channel below the control gate electrode 8 is turned on. Here, an appropriate memory gate potential capable of discriminating the threshold voltage difference of the memory gate electrode 10 given by the write and erase states (that is, between the threshold voltage in the write state and the threshold voltage in the erase state) When the potential is applied, the stored charge information is read as a current. When the memory cell is in a write state and the threshold voltage is high, no current flows through the memory cell, and when the memory cell is in an erase state and the threshold voltage is low, a current flows through the memory cell. . As a result of comparing the read current with the reference current, if the read current is smaller than the reference current, it can be determined that the memory cell is in the write state.

  Here, for example, taking a write operation as an example, a voltage of 1 V is applied to the control gate electrode 8 of the split gate type memory cell, and a voltage of 10 V is applied to the memory gate electrode 10. That is, the potential difference between the control gate electrode 8 and the memory gate electrode 10 is increased. At this time, in the split gate type memory cell, the memory gate electrode 10 is formed on the side wall of the control gate electrode 8, and the control gate electrode 8 and the memory gate electrode 10 are close to each other. Accordingly, the electric field strength generated between the control gate electrode 8 and the memory gate electrode 10 is increased. As a result, the electric field strength applied to the stacked gate insulating film 9 (the first potential barrier film 9a, the charge holding film 9b, and the second potential barrier film 9c) formed between the control gate electrode 8 and the memory gate electrode 10. As a result, the leakage current flowing between the control gate electrode 8 and the memory gate electrode 10 through the stacked gate insulating film 9 increases.

  When the leakage current increases, the power consumption of the entire memory increases and there is a risk that normal operation cannot be ensured. That is, in the split gate type memory cell, the miniaturization can be promoted by forming the memory gate electrode 10 on the side wall of the control gate electrode 8, but the control gate electrode 8 and the memory gate electrode 10 are close to each other. Therefore, when a large potential difference is generated between the control gate electrode 8 and the memory gate electrode 10 as in writing, the electric field strength applied to the stacked gate insulating film 9 is increased and the stacked gate insulating film 9 is interposed. As a result, the leakage current generated between the control gate electrode 8 and the memory gate electrode 10 increases.

  However, in the split gate type memory cell according to the present embodiment, since the sidewall insulating film 11 is formed in addition to the laminated gate insulating film 9 between the control gate electrode 8 and the memory gate electrode 10, the control gate electrode The distance between 8 and the memory gate electrode 10 is increased. Since the electric field strength becomes smaller as the distance between the control gate electrode 8 and the memory gate electrode 10 becomes larger, the formation of the sidewall insulating film 11 reduces the electric field strength, and the control gate electrode 8 and the memory gate are reduced. There is also a second effect that leakage current flowing between the electrodes 10 can be reduced.

Next, a method for manufacturing a semiconductor device having the memory cells (MC ₁ , MC ₂ ) will be described in the order of steps with reference to FIGS. This semiconductor device is composed of a memory array and a peripheral circuit, and the peripheral circuit is further composed of a peripheral circuit composed of a low breakdown voltage complementary MISFET and a peripheral circuit composed of a high breakdown voltage complementary MISFET. For example, a first power supply voltage of 3.3 V is applied to the gate electrode or drain region of the low withstand voltage complementary MISFET, and higher than the first power supply voltage is applied to the gate electrode or drain region of the high withstand voltage complementary MISFET. For example, a second power supply voltage of 5.0 V is applied.

  The peripheral circuit configured by the low-voltage complementary MISFET is, for example, a processor such as a CPU, a control circuit, a sense amplifier, a column decoder, or a row decoder. The peripheral circuit configured by the high-voltage complementary MISFET is, for example, an input / output Circuit. Therefore, the figure shows a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region as peripheral circuit regions in addition to the memory array region. In addition, the shunt region located between the memory array region and the peripheral circuit region is a region that connects each of the control gate electrode 8 and the memory gate electrode 10 to the upper layer wiring. In addition, the manufacturing method demonstrated here shows the preferable one aspect | mode of this invention, and this invention is not limited by this.

  First, as shown in FIG. 4, an element isolation part (STI: Shallow Trench Isolation) 2 is formed on the main surface of the substrate 1. In order to form the element isolation part 2, for example, a groove is formed in the substrate 1 by dry etching using a silicon nitride film as a mask, and then a silicon oxide film is deposited on the substrate 1 by a CVD (Chemical Vapor Deposition) method. Thereafter, the silicon oxide film outside the groove may be removed by chemical mechanical polishing to leave the silicon oxide film inside the groove.

  Next, as shown in FIG. 5, B (boron) ions are implanted into the substrate 1 in the memory array region to form the p-type well 4. In the peripheral circuit region, B is ion-implanted into the substrate 1 in the region where the n-channel MISFET is to be formed to form the p-type well 4, and P (phosphorus) is applied to the substrate 1 in the region where the p-channel MISFET is to be formed. Are ion-implanted to form an n-type well 5.

  Next, as shown in FIG. 6, a gate insulating film 6 made of, for example, a silicon oxide film is formed as an insulating film on each surface of the p-type well 4 and the n-type well 5 in the high breakdown voltage MISFET formation region. Further, a gate insulating film 7 made of, for example, a silicon oxide film is formed as an insulating film on each surface of the p-type well 4 in the memory array region, the p-type well 4 and the n-type well 5 in the low breakdown voltage MISFET formation region. The gate insulating film 6 is formed with a thickness greater than that of the gate insulating film 7 in order to ensure the withstand voltage of the high withstand voltage MISFET.

  In order to form two types of gate insulating films 6 and 7 having different film thicknesses, the entire surface of the substrate 1 is first thermally oxidized to form a silicon oxide film, and then the p-type well 4 in the high breakdown voltage MISFET formation region. The silicon oxide film is left on the surface of each of the n-type wells 5 and the silicon oxide film in other regions is removed by etching. Subsequently, the entire surface of the substrate 1 is thermally oxidized once again, and a gate insulating film 7 is formed on each surface of the p-type well 4 in the memory array region, the p-type well 4 in the low breakdown voltage MISFET formation region, and the n-type well 5. . At this time, the silicon oxide film remaining on the surface of each of the p-type well 4 and the n-type well 5 in the high breakdown voltage MISFET formation region increases in thickness and becomes a gate insulating film 6 thicker than the gate insulating film 7. .

However, the gate insulating film 7 is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film 7 may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 7 and the substrate 1 may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film 7 can be improved, and the insulation resistance can be improved. Further, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film for the gate insulating film 7, it is possible to suppress a variation in threshold voltage caused by diffusion of impurities in the gate electrode toward the substrate 1 side. The silicon oxynitride film may be formed by heat-treating the substrate 1 in an atmosphere containing nitrogen such as NO, NO ₂ or NH ₃ , for example. Further, after forming a gate insulating film 7 made of a silicon oxide film on the surface of the substrate 1, the substrate 1 is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film 7 and the substrate 1. The same effect can be obtained.

  Further, the gate insulating film 7 may be formed of, for example, a high dielectric constant film having a dielectric constant higher than that of the silicon oxide film. Conventionally, a silicon oxide film has been used as the gate insulating film 7 from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film 7 is required to be extremely thin. Thus, when a thin silicon oxide film is used as the gate insulating film 7, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. If a high dielectric constant film is used, the physical film thickness can be increased even if the capacitance is the same, so that the leakage current can be reduced. In particular, the silicon nitride film is also a film having a higher dielectric constant than the silicon oxide film, but in this embodiment, it is desirable to use a high dielectric constant film having a higher dielectric constant than the silicon nitride film.

For example, a hafnium oxide (HfO ₂ ) film, which is one of hafnium (Hf) oxides, is used as a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film. Instead of the hafnium oxide film, an HfAlO film is used. Other hafnium-based insulating films such as (hafnium aluminate film), HfON film (hafnium oxynitride film), HfSiO film (hafnium silicate film), HfSiON film (hafnium silicon oxynitride film), and HfAlO film are used. You can also. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. These hafnium-based insulating films have a dielectric constant higher than that of a silicon oxide film or a silicon oxynitride film, similarly to the hafnium oxide film, so that the same effect as that obtained when a hafnium oxide film is used can be obtained.

  Next, as shown in FIG. 7, after depositing a non-doped polycrystalline silicon film (or non-doped amorphous silicon film) 8a on the substrate 1 by a CVD method, the non-doped polycrystalline silicon film 8a in the peripheral circuit region is coated with a photoresist film 40. Then, P is ion-implanted into the non-doped polycrystalline silicon film 8a in the memory array region and the shunt region to form an n-type polycrystalline silicon film 8n.

  Next, after the photoresist film 40 is removed, as shown in FIG. 8, the n-type polycrystalline silicon film 8n in the memory array region and the shunt region is dry-etched using the photoresist film 41 as a mask, thereby providing a memory array. A control gate electrode 8 is formed in the region, and a wiring 8 s for supplying a potential to the control gate electrode 8 is formed in the shunt region. The wiring 8s formed in the shunt region is electrically connected to the control gate electrode 8 in the memory array region in a region not shown.

  Next, after removing the photoresist film 41, as shown in FIGS. 9 and 10, the entire surface of the substrate 1 is made of a first potential barrier film 9a made of, for example, a silicon oxide film and a silicon nitride film as an insulating film. A laminated gate insulating film 9 composed of a three-layer film of a charge holding film 9b and a second potential barrier film 9c made of a silicon oxide film is formed. At this time, the silicon oxide film of the first potential barrier film 9a is deposited by a thermal oxidation method, a CVD method, or a combination of both, and the silicon nitride film of the charge retention film 9b is deposited by a CVD method. The silicon oxide film of the second potential barrier film 9c is formed by oxidizing the surface of the silicon nitride film of the charge holding film 9b. The oxidation of the surface of the silicon nitride film that is the charge holding film 9b is performed using, for example, an ISSG (In Situ Steam Generation) oxidation method. The first potential barrier film 9a has a thickness of about 3 to 5 nm, the charge holding film 9b has a thickness of about 8 to 10 nm, and the second potential barrier film 9c has a thickness of about 3 to 5 nm. .

  In the present embodiment, the charge retention film 9b is formed of a silicon nitride film. However, not only the silicon nitride film but also a film including discrete trap levels can be used to improve data retention characteristics. Can be planned. As the charge retention film 9b, for example, silicon nanodots in which silicon is formed into a plurality of grains, or an oxide film or a silicate film of any metal selected from the group consisting of tantalum, titanium, zirconium, hafnium, lanthanum, and aluminum It may be configured with such as.

  Next, as shown in FIG. 11, by depositing, for example, a silicon oxide film 11a as an insulating film by a CVD method on the stacked gate insulating film 9, the silicon oxide film 11a is anisotropically etched. As shown in FIGS. 12 and 13, a sidewall insulating film 11 is formed on the sidewall of the control gate electrode 8. As described above, the sidewall insulating film 11 is an insulating film for preventing a short circuit between the control gate electrode 8 and the memory gate electrode 10 formed in a later process. By forming the sidewall insulating film 11, the memory gate electrode 10 is controlled by the control gate electrode 8 by the thickness of the sidewall insulating film 11 as compared with the case where only the stacked gate insulating film 9 is formed in a later step. It can be formed away from.

In the above structure in which the side wall insulating film 11 is formed on the side wall of the control gate electrode 8, the thickness of the laminated gate insulating film 9 (between the memory gate electrode 10 and the p-type well 4 formed in a later step) Since b) does not increase in thickness, the erasing operation of the memory cell does not deteriorate. That is, when erasing information written in the memory cell, hot holes are injected into the stacked gate insulating film 9 from the n ⁺ -type semiconductor region (source region) 17s side, but the thickness of the stacked gate insulating film 9 ( Since b) does not become thick, the hot hole injection rate does not decrease. Even when erasing is performed using a Fowler-Nordheim tunnel current, the thickness (b) of the stacked gate insulating film 9 does not increase, so that the p-type well 4 is removed from the stacked gate insulating film 9. The rate of electron emission to the substrate does not decrease.

  In the above-described step of anisotropically etching the silicon oxide film 11a to form the sidewall insulating film 11, a three-layer insulating film (first potential barrier film 9a, charge holding film 9b is formed as shown in FIG. Since the second potential barrier film 9c formed on the surface portion of the laminated gate insulating film 9 made of the second potential barrier film 9c) is also a silicon oxide film, it is simultaneously etched when forming the sidewall insulating film 11, The film thickness of the second potential barrier film 9c may be reduced. In that case, as shown in FIG. 15, by newly forming a silicon oxide film on the charge retention film 9b, the thickness of the second potential barrier film 9c thinned by etching is increased to a desired thickness. It is desirable. At this time, in order to form the silicon oxide film, for example, the surface of the charge retention film 9b may be reoxidized by the ISSG oxidation method or the silicon oxide film may be deposited by the CVD method. A two-potential barrier film 9d is used. The film thickness of the second potential barrier film 9d is about 3 to 5 nm.

  In this case, the sum of the film thickness of the second potential barrier film 9d formed on one side wall of the control gate electrode 8 and the film thickness of the side wall insulating film is a, and is formed below the memory gate electrode 10. The film thickness of the second potential barrier film 9d thus formed is b. At this time, if the relationship of a> b is established, the distance between the Co silicide layers 18 formed on the respective surfaces of the control gate electrode 8 and the memory gate electrode 10 is increased in the following steps, and the Co silicide layer 18 It is possible to avoid a short circuit between the control gate electrode 8 and the memory gate electrode 10 due to the contact.

  Next, as shown in FIG. 16, after depositing an n-type polycrystalline silicon film 10n on the substrate 1 by CVD, the n-type polycrystalline silicon film 10n is anisotropically dry-etched as shown in FIG. Thus, the memory gate electrode 10 is formed on both side walls of the control gate electrode 8 formed in the memory array region, and the wiring 10s for supplying a potential to the memory gate electrode 10 is formed in the shunt region. The wiring 10s formed in the shunt region is electrically connected to the memory gate electrode 10 in the memory array region in a region not shown.

  Next, as shown in FIG. 18, the memory gate electrode 10 and the sidewall insulating film 11 on one side wall of the control gate electrode 8 are removed using the photoresist film 42 as a mask. Subsequently, after removing the photoresist film 42, as shown in FIGS. 19 and 20, the stacked gate insulating film 9 remaining in an unnecessary region is removed by wet etching using hydrofluoric acid and phosphoric acid.

  Next, as shown in FIG. 21, P or As (arsenic) ions are implanted into the non-doped polycrystalline silicon film 8a formed in the n-channel type MISFET formation region in the peripheral circuit region to form the n-type polycrystalline silicon film 8n. Then, B is ion-implanted into the non-doped polycrystalline silicon film 8a formed in the p-channel type MISFET formation region to form a p-type polycrystalline silicon film 8p.

  Next, as shown in FIG. 22, the n-type polycrystalline silicon film 8n and the p-type polycrystalline silicon film 8p in the peripheral circuit region are dry-etched using the photoresist film 43 as a mask, whereby the gate electrodes 14n, 14p, 15n and 15p are formed.

Next, after removing the photoresist film 43, as shown in FIG. 23, ions of P or As (arsenic) are implanted into the p-type well 4 in the peripheral circuit region to form an n ⁻ type semiconductor as a shallow low-concentration impurity diffusion region. Region 19n is formed. Also, P or As is ion-implanted into the p-type well 4 in the memory array region to form n ⁻ -type semiconductor regions 13d and 13s as shallow low-concentration impurity diffusion regions. Further, B is ion-implanted into the n-type well 5 in the peripheral circuit region to form a p ⁻ -type semiconductor region 19p as a shallow low-concentration impurity diffusion region.

  Next, as shown in FIGS. 24 and 25, the side walls of the gate electrodes 14n, 14p, 15n, and 15p in the peripheral circuit region, and the control gate electrode 8 and the memory gate electrode 10 in the memory array region, respectively. A sidewall insulating film 12 is formed on the sidewall. The sidewall insulating film 12 is formed by anisotropically etching a silicon oxide film deposited by, for example, a CVD method.

Subsequently, P or As is ion-implanted into the p-type well 4 in the peripheral circuit region to form an n ⁺ -type semiconductor region 20n as a deep high-concentration impurity diffusion region. Further, P ⁺ or As ions are implanted into the p-type well 4 in the memory array region to form n ⁺ -type semiconductor regions 17d and 17s. Further, B is ion-implanted into the n-type well 5 in the peripheral circuit region to form a p ⁺ -type semiconductor region 20p as a deep high-concentration impurity diffusion region. The n ⁺ type semiconductor region 20n functions as the source and drain regions of the n channel type MISFET in the peripheral circuit region, and the p ⁺ type semiconductor region 20p functions as the source and drain regions of the p channel type MISFET.

  As described above, the source region and the drain region are formed by the shallow low-concentration impurity diffusion region and the deep high-concentration impurity diffusion region, so that the source region and the drain region can have an LDD (Lightly Doped Drain) structure. Here, in the memory array region, when P or As is ion-implanted into the p-type well 4, the upper end of the control gate electrode 8, the upper end of the memory gate electrode 10, and the upper end of the stacked gate insulating film 9 are also formed. Ions such as P and As are implanted. In particular, when P or As is implanted into the upper end portion of the laminated gate insulating film 9 made of an insulating film, a phenomenon that the insulation resistance of the laminated gate insulating film 9 deteriorates occurs. Then, the leakage current flowing between the upper end portion of the control gate electrode 8 and the upper end portion of the memory gate electrode 10 that are insulated by the stacked gate insulating film 9 increases.

  However, in this embodiment, since the sidewall insulating film 11 is formed between the stacked gate insulating film 9 and the memory gate electrode 10, the upper end portion of the control gate electrode 8 and the upper end portion of the memory gate electrode 10 are The distance can be separated. This means that the electric field strength can be relaxed in the laminated gate insulating film 9 existing between the control gate electrode 8 and the memory gate electrode 10. Therefore, even if P or As is implanted into the upper end portion of the laminated gate insulating film 9 and the insulation resistance of the laminated gate insulating film 9 is deteriorated, the sidewall insulating film 11 is formed, and thus it is generated in the laminated gate insulating film 9. Since the electric field strength can be relaxed, the leakage current flowing through the control gate electrode 8 and the memory gate electrode 10 can be reduced.

Next, as shown in FIGS. 26 and 27, the control gate electrode 8 in the memory array region, the memory gate electrode 10, the n ⁺ type semiconductor regions 17d and 17s, the wiring 8s and 10s in the shunt region, and the gate electrode in the peripheral circuit region A Co silicide layer 18 is formed as a silicide layer on the surface of each of 14n, 14p, 15n, 15p, n ⁺ type semiconductor region 20n, and p ⁺ type semiconductor region 20p. In order to form the Co silicide layer 18, first, a Co film is deposited on the substrate 1 by sputtering, and then the substrate 1 is heat-treated to form a Co film and silicon (a single crystal silicon layer and a gate electrode constituting the substrate 1). Then, the unreacted Co film may be removed by wet etching.

  In this embodiment, the Co silicide layer 18 is formed. However, for example, a Ni silicide layer, a Ti silicide layer, a Pt silicide layer, or the like is formed as a silicide layer in place of the Co silicide layer 18. You may do it.

  At this time, in this embodiment, since the sidewall insulating film 11 is formed on the sidewall of the control gate electrode 8, the distance between the control gate electrode 8 and the upper end of the memory gate electrode 10 can be increased. This means that the distance between the Co silicide layer 18 formed on the surface of the control gate electrode 8 and the Co silicide layer 18 formed on the surface of the memory gate electrode 10 can be increased. Therefore, even when the memory cell is miniaturized, the Co silicide layer 18 formed on the surface of the control gate electrode 8 and the Co silicide layer 18 formed on the surface of the memory gate electrode 10 are in contact with each other. It is possible to suppress short-circuit defects that occur.

  Through the steps so far, the selection MIS transistor and the memory MIS transistor in the memory array region are completed, and the n-channel MISFET and the p-channel MISFET in the peripheral circuit region are completed.

Next, as shown in FIGS. 28 and 29, an insulating film 22 made of, for example, a silicon nitride film and an interlayer insulating film 23 made of a silicon oxide film are deposited as insulating films on the substrate 1 by CVD. Subsequently, using the photoresist film (not shown) formed on the interlayer insulating film 23 as a mask, the interlayer insulating film 23 and the insulating film 22 are dry-etched to contact the upper portion of the n ⁺ type semiconductor region 17d in the memory array region. Hole 24 is formed. At this time, the contact hole 25 is formed above the wiring 10s in the shunt region, and the contact hole 26 is formed above the wiring 8s. Further, contact holes 27 and 29 are formed above the n ⁺ type semiconductor region 20n in the peripheral circuit region, and contact holes 28 and 30 are formed above the p ⁺ type semiconductor region 20p.

  Next, as shown in FIGS. 30 and 31, plugs 31 are formed in the contact holes 24 to 30. In order to form the plug 31, for example, a Ti film, a TiN (titanium nitride) film, or a W film is deposited as a metal film inside the plug 31 and on the interlayer insulating film 23 by a sputtering method, and then a Ti film outside the plug 31 is formed. The TiN film and the W film may be removed by a chemical mechanical polishing method.

  Conventionally, in order to supply a potential to the memory gate electrode 10, a pad for forming a plug has been formed by extending the wiring 10 s portion onto the substrate 1. This is because when the plug 31 is formed on the wiring 10 s formed in the sidewall shape, the wiring 10 s and the control gate electrode 8 are separated by a distance corresponding to the film thickness of the stacked gate insulating film 9. This is to prevent the Co silicide layers 18 formed above the electrode 10 and the control gate electrode 8 from being short-circuited via the plug 31.

  However, in the present embodiment, since the sidewall insulating film 11 is formed between the stacked gate insulating film 9 and the memory gate electrode 10, it is formed on the respective surfaces of the control gate electrode 8 and the memory gate electrode 10. The distance between the Co silicide layers 18 is large. That is, the Co silicide layers 18 formed on the surfaces of the control gate electrode 8 and the wiring 10s are separated from each other. Therefore, as shown in FIG. 30, even if the plug 31 is formed directly on the wiring 10 s without forming a pad, the Co formed on the surfaces of the wiring 10 s and the control gate electrode 8 through the plug 31. Short-circuiting of the silicide layer 18 via the plug 31 can be suppressed. Further, since the plug 31 connected to the wiring 10s is formed on the element isolation portion 2, as shown in FIG. 30, even when the plug 31 is formed over the substrate 1 from the wiring 10s. There is no short circuit with the p-type well 4 formed in the substrate 1.

  Note that FIG. 30 illustrates a case where the plug 31 is formed only in one of the source region or the drain region of the low withstand voltage MISFET and the high withstand voltage MISFET in the peripheral circuit region for the sake of simplicity of explanation.

  Next, as shown in FIGS. 32 and 33, after the second interlayer insulating film 32 is deposited on the interlayer insulating film 23, the second interlayer insulating film 32 is dried using a photoresist film (not shown) as a mask. By etching, a wiring groove 33 is formed on each of the contact holes 24-30. The second interlayer insulating film 32 is formed of, for example, a laminated film of a SiCN film and a silicon oxide film deposited by a CVD method as an insulating film.

  Next, as shown in FIGS. 34 and 35, the bit line BL is formed in the wiring groove 33 in the memory array region, the first layer wirings 34 and 35 are formed in the wiring groove 33 in the shunt region, and the peripheral circuit region A first layer wiring 36 is formed in the wiring groove 33. In order to form the bit line BL and the first layer wirings 34, 35, 36, a metal film mainly composed of Cu is deposited inside the wiring trench 33 and on the second interlayer insulating film 32, and then outside the wiring trench 33. The metal film may be removed by a chemical mechanical polishing method.

  Thereafter, the deposition of the interlayer insulating film, the formation of the wiring trench and the formation of the wiring are repeated to form a plurality of layers of the upper layer wiring, but the description thereof is omitted.

  In the present embodiment, the short-circuit prevention side wall insulating film 11 formed on the side wall of the control gate electrode 8 is formed using silicon oxide as the insulating film, but is not limited to silicon oxide, and silicon oxide For example, a silicon nitride film may be used instead of the film. That is, in the process shown in FIG. 9, after forming the laminated gate insulating film 9, a silicon nitride film is deposited on the laminated gate insulating film 9 by the CVD method, and this silicon nitride film is anisotropically etched. Then, it may be left on the side wall of the control gate electrode 8.

  When the sidewall insulating film 11 is formed of silicon nitride, as shown in FIG. 36, the thickness of the sidewall insulating film 11 is a ′, and the second potential barrier film 9c formed under the memory gate electrode 10 is used. It is desirable to form the sidewall insulating film 11 so that the relationship of a ′> b is established, where b is the thickness of the film. In this case, when the silicon nitride film (sidewall insulating film 11) is etched, the surface portion of the laminated gate insulating film 9 (second potential barrier film 9c made of silicon oxide) is hardly etched. Therefore, after the sidewall insulating film 11 is formed, the process of re-oxidizing the surface of the charge holding film 9b made of silicon nitride by the above-described ISSG oxidation method becomes unnecessary, or the processing time of this re-oxidation is shortened. Can do.

  As described above, in the split gate type memory cell of the present embodiment, the sidewall insulating film 11 is formed between the stacked gate insulating film 9 formed on one sidewall of the control gate electrode 8 and the memory gate electrode 10. As a result, the memory gate electrode 10 and the control gate electrode 8 are electrically separated from each other by the sidewall insulating film 11 and the laminated gate insulating film 9, and the distance between the control gate electrode 8 and the upper end portion of the memory gate electrode 10. Therefore, even when the distance between the control gate electrode 8 and the memory gate electrode 10 becomes closer with the miniaturization of the memory cell, the short circuit between the control gate electrode 8 and the memory gate electrode 10 can be effectively avoided. can do.

(Embodiment 2)
FIG. 37 is a cross-sectional view showing the memory cells (MC ₁ , MC ₂ ) of the present embodiment. As shown in FIG. 37, each of the memory cells (MC ₁ , MC ₂ ) is composed of one selection MIS transistor and one memory MIS transistor formed in the p-type well 4 of the substrate 1. .

  The selection MIS transistor includes a gate insulating film 7 formed on the surface of the p-type well 4 and a control gate electrode 8 formed on the gate insulating film 7. A first cap insulating film 3a made of, for example, a silicon oxide film is formed as an insulating film on the control gate electrode 8, and a second cap made of, for example, a silicon nitride film as the insulating film is formed on the first cap insulating film 3a. A cap insulating film 3b is formed.

  The memory MIS transistor is partly formed on one side wall of the laminated film including the control gate electrode 8, the first cap insulating film 3a, and the second cap insulating film 3b, and the other part is the p-type well 4. A laminated gate insulating film 9 having an L-shaped cross section formed on the surface and one side wall of the control gate electrode 8 are electrically connected to the control gate electrode 8 and the p-type well 4 via the laminated gate insulating film 9. A separated memory gate electrode 10 is provided. The stacked gate insulating film 9 of the memory MIS transistor includes a first potential barrier film 9a, a second potential barrier film 9c, and a charge holding film 9b formed therebetween. The first potential barrier film 9a and the second potential barrier film 9c are formed of, for example, a silicon oxide film as an insulating film, and the charge holding film 9b is formed of, for example, a silicon nitride film as a film having a function of holding charges. Is formed.

In the p-type well 4 in the vicinity of the control gate electrode 8, an n ⁺ -type semiconductor region 17d that functions as a drain region common to _two memory cells (MC ₁ , MC ₂ ) is formed. The n ⁺ type semiconductor region 17d is connected to the bit line BL. The bit line BL is formed on the interlayer insulating film 23 that covers the memory cells (MC ₁ , MC ₂ ), and the plug 31 in the contact hole 24 formed in the interlayer insulating film 23 and the insulating film 22 therebelow is connected to the bit line BL. And is electrically connected to the n ⁺ type semiconductor region 17d.

In the p-type well 4 in the vicinity of the memory gate electrode 10, an n ⁺ -type semiconductor region 17s that functions as a source region of the memory cell is formed. The n ⁺ type semiconductor region 17s is connected to the common source line SL shown in FIG. The common source line SL is composed of an n ⁺ type semiconductor region 17s formed in the p-type well 4, and is formed integrally with the source region.

An n ⁻ type semiconductor region 13d having an impurity concentration lower than that of the n ⁺ type semiconductor region 17d is formed in the p type well 4 in a region adjacent to the n ⁺ type semiconductor region (drain region) 17d. Further, an n ⁻ type semiconductor region 13s having an impurity concentration lower than that of the n ⁺ type semiconductor region 17s is formed in the p type well 4 in a region adjacent to the n ⁺ type semiconductor region (source region) 17s. Further, for example, a Co silicide layer 18 is formed as a silicide layer on the surfaces of the memory gate electrode 10 and the n ⁺ -type semiconductor regions 17d and 17s. Since the first cap insulating film 3a and the second cap insulating film 3b are formed on the control gate electrode 8, the Co silicide layer 18 is not formed. This has the first effect that a short circuit between the Co silicide layer 18 formed on the surface of the memory gate electrode 10 and the upper portion of the control gate electrode 8 can be avoided.

  On the other hand, as shown in FIG. 38, between the stacked gate insulating film 9 formed on one side wall of the control gate electrode 8 and the memory gate electrode 10, as an insulating film, for example, a side wall insulating film made of a silicon oxide film 11 is formed. The other side wall of the control gate electrode 8 and one side wall of the memory gate electrode 10 (side wall opposite to the side wall in contact with the side wall insulating film 11) are made of, for example, a silicon oxide film as an insulating film. A sidewall insulating film 12 is formed.

  As will be described in detail later, in the process of manufacturing the memory cell, P or As is implanted into the upper end portion of the stacked gate insulating film 9, which may deteriorate the insulation resistance of the stacked gate insulating film 9. That is, the insulation resistance between the control gate electrode 8 and the memory gate electrode 10 may deteriorate. Therefore, the provision of the sidewall insulating film 11 reduces the electric field strength even when the potential difference between the control gate electrode 8 and the memory gate electrode 10 is increased by a write operation or the like, and the control gate electrode 8 and the memory gate are reduced. A second effect that the leakage current flowing between the electrodes 10 can be reduced is also obtained. The second effect is the same in the memory cell of the first embodiment.

  Here, the condition of the sidewall insulating film 11 formed between the control gate electrode 8 and the memory gate electrode 10 is considered. As shown in FIG. 38, the thickness of the second potential barrier film 9c formed on one side wall of the laminated film composed of the control gate electrode 8, the first cap insulating film 3a, and the second cap insulating film 3b, and the side wall The sum of the film thickness of the insulating film 11 is a, and the film thickness of the second potential barrier film 9c formed below the memory gate electrode 10 is b. At this time, it is desirable to form the sidewall insulating film 11 so that the relationship of a> b is established. That is, the film thickness of the oxide film formed between the charge holding film 9b and the memory gate electrode 10 is set to the film thickness of the oxide film between the charge holding film 9b and the memory gate electrode 10 on the lower side of the memory gate electrode 10. It is desirable to form it thicker than the thickness. For example, in the case of a semiconductor device with a design rule of 90 nm, a = about 5 to 10 nm. The thickness of the second potential barrier film 9c is about 3 to 5 nm.

  Thereby, since the distance between the control gate electrode 8 and the memory gate electrode 10 becomes long, even when the potential difference between the control gate electrode 8 and the memory gate electrode 10 becomes large, the electric field strength is relaxed, Leakage current flowing between the control gate electrode 8 and the memory gate electrode 10 can be reduced.

Next, a method for manufacturing a semiconductor device having the memory cells (MC ₁ , MC ₂ ) will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 39, after the element isolation portion 2, the p-type well 4 and the n-type well 5 are formed on the main surface of the substrate 1, the p-type well 4 and the n-type well 5 in the high breakdown voltage MISFET formation region are formed. A thick gate insulating film 6 is formed on each surface, and a thin gate insulating film 7 is formed on each surface of the p-type well 4 in the memory array region, the p-type well 4 and the n-type well 5 in the low breakdown voltage MISFET formation region. . The steps so far are the same as the steps shown in FIGS. 4 to 6 of the first embodiment.

  Next, as shown in FIG. 40, after depositing a non-doped polycrystalline silicon film (or non-doped amorphous silicon film) 8a on the substrate 1 by a CVD method, the non-doped polycrystalline silicon film 8a in the peripheral circuit region is coated with a photoresist film 40. Then, P is ion-implanted into the non-doped polycrystalline silicon film 8a in the memory array region to form an n-type polycrystalline silicon film 8n.

  Next, after removing the photoresist film 40, as shown in FIG. 41, the first cap insulating film 3a and the second cap insulating film are formed on the n-type polycrystalline silicon film 8n and the non-doped polycrystalline silicon film 8a, respectively. 3b is formed. The first cap insulating film 3a is formed by oxidizing the surfaces of the n-type polycrystalline silicon film 8n and the non-doped polycrystalline silicon film 8a by, for example, the ISSG oxidation method, and the second cap insulating film 3b is formed by, for example, the first cap insulating film 3b. It is formed by depositing a silicon nitride film on the film 3a by the CVD method.

  Next, as shown in FIG. 42, the photoresist film 41 is used as a mask to dry-etch the n-type polycrystalline silicon film 8n, the first cap insulating film 3a, and the second cap insulating film 3b in the memory array region and the shunt region. As a result, the control gate electrode 8 is formed in the memory array region. Further, a wiring 8 s for supplying a potential to the control gate electrode 8 is formed in the shunt region.

  Next, after removing the photoresist film 41, as shown in FIG. 43, the memory array region and a part of the shunt region are covered with the photoresist film 44, and the wiring 8s in the shunt region and the non-doped polycrystal in the peripheral circuit region are covered. The first cap insulating film 3a and the second cap insulating film 3b on each of the silicon films 8a are removed by dry etching. At this time, the first cap insulating film 3a functions as an etching stopper when the second cap insulating film 3b is etched.

  Next, after removing the photoresist film 44, as shown in FIGS. 44 and 45, the entire surface of the substrate 1 is made of, for example, a first potential barrier film 9a made of silicon oxide and a silicon nitride film as an insulating film. A laminated gate insulating film 9 composed of a three-layer film of a charge holding film 9b and a second potential barrier film 9c made of a silicon oxide film is formed. The method of forming the first potential barrier film 9a, the charge holding film 9b, and the second potential barrier film 9c may be the same as in the first embodiment. Similarly to the first embodiment, as the charge retention film 9b, for example, silicon nanodots in which silicon is formed into a plurality of particles, or any one selected from the group consisting of tantalum, titanium, zirconium, hafnium, lanthanum, and aluminum Such metal oxide film or silicate film may be used.

  Next, as shown in FIGS. 46 and 47, a sidewall insulating film 11 is formed on the sidewall of the control gate electrode 8. In order to form the sidewall insulating film 11, the silicon oxide film deposited on the upper portion of the laminated gate insulating film 9 by the CVD method may be anisotropically etched as in the first embodiment. At this time, since the first cap insulating film 3a and the second cap insulating film 3b are formed on the control gate electrode 8, the sidewall insulating film 11 includes the control gate electrode 8, the first cap insulating film 3a, And formed on the side wall of the laminated film made of the second cap insulating film 3b.

  Note that, as described in the first embodiment, in the above step of forming the sidewall insulating film 11 by anisotropically etching the silicon oxide film, the three-layer insulating film (first potential barrier film 9a, charge Since the second potential barrier film 9c formed on the surface portion of the laminated gate insulating film 9 composed of the holding film 9b and the second potential barrier film 9c) is also a silicon oxide film, when the sidewall insulating film 11 is formed, At the same time, the second potential barrier film 9c may become thin. In that case, as in the first embodiment, a second potential is obtained by forming a new silicon oxide film on the charge retention film 9b by, for example, the ISSG oxidation method or by depositing a silicon oxide film by the CVD method. It is desirable to increase the thickness of the barrier film 9c. In that case, the film thickness of the second potential barrier film 9c is about 3 to 5 nm.

  Next, as shown in FIG. 48, the memory gate electrode 10 is formed on both side walls of the control gate electrode 8 formed in the memory array region. A wiring 10 s for supplying a potential to the memory gate electrode 10 is formed in the shunt region. In order to form the memory gate electrode 10 and the wiring 10s, an n-type polycrystalline silicon film is deposited on the substrate 1 by the CVD method, and then the n-type polycrystalline silicon film is anisotropically dry-etched. Similarly to the sidewall insulating film 11, the memory gate electrode 10 is formed on the sidewall of the laminated film including the control gate electrode 8, the first cap insulating film 3a, and the second cap insulating film 3b.

  Next, as shown in FIG. 49, by dry etching using the photoresist film 42 as a mask, one sidewall of the laminated film composed of the control gate electrode 8, the first cap insulating film 3a, and the second cap insulating film 3b is formed. The memory gate electrode 10 and the sidewall insulating film 11 are removed. Subsequently, after removing the photoresist film 42, as shown in FIG. 50, the stacked gate insulating film 9 remaining in an unnecessary region is removed by wet etching using hydrofluoric acid and phosphoric acid.

  Next, as shown in FIG. 51, P or As is ion-implanted into the non-doped polycrystalline silicon film 8a formed in the n-channel MISFET forming region in the peripheral circuit region to form an n-type polycrystalline silicon film 8n. B is ion-implanted into the non-doped polycrystalline silicon film 8a formed in the p-channel type MISFET formation region to form a p-type polycrystalline silicon film 8p.

  Next, as shown in FIG. 52, the n-type polycrystalline silicon film 8n and the p-type polycrystalline silicon film 8p in the peripheral circuit region are dry-etched using the photoresist film 43 as a mask, whereby the gate electrodes 14n, 14p, 15n and 15p are formed.

Next, after removing the photoresist film 43, as shown in FIG. 53, P or As is ion-implanted into the p-type well 4 in the peripheral circuit region to form an n ⁻ -type semiconductor region 19n. N ^- type semiconductor regions 13d and 13s are formed by ion implantation of P or As into the p-type well 4. Further, p ⁻ type semiconductor region 19p is formed by ion implantation of B into n type well 5 in the peripheral circuit region.

  Next, as shown in FIG. 54, the side walls of the gate electrodes 14n, 14p, 15n, and 15p in the peripheral circuit region, the control gate electrode 8, the first cap insulating film 3a, and the second cap insulation in the memory array region. A sidewall insulating film 12 is formed on one side wall of the laminated film made of the film 3 b and one side wall of the memory gate electrode 10. The sidewall insulating film 12 is formed by depositing, for example, silicon oxide as an insulating film by, for example, a CVD method and anisotropically etching the silicon oxide film.

Subsequently, by ion implantation of P or As to form the n ⁺ -type semiconductor region 20n to p-type well 4 of the peripheral circuit region, n ⁺ -type by ion implanting P or As in the p-type well 4 in the memory array region Semiconductor regions 17d and 17s are formed. Further, B is ion-implanted into the n-type well 5 in the peripheral circuit region to form the p ⁺ -type semiconductor region 20p.

  At this time, as in the first embodiment, P or As is implanted into the upper end portion of the laminated gate insulating film 9. However, even in that case, since the sidewall insulating film 11 is formed between the stacked gate insulating film 9 and the memory gate electrode 10, the upper end portion of the control gate electrode 8 and the upper end portion of the memory gate electrode 10 are The distance can be separated. This means that the electric field strength can be relaxed in the laminated gate insulating film 9 existing between the control gate electrode 8 and the memory gate electrode 10. Therefore, even if P or As is implanted into the upper end portion of the laminated gate insulating film 9 and the insulation resistance of the laminated gate insulating film 9 is deteriorated, the electric field generated in the laminated gate insulating film 9 by forming the sidewall insulating film 11. Since the strength can be relaxed, the leakage current flowing between the control gate electrode 8 and the memory gate electrode 10 can be reduced.

Next, as shown in FIG. 55, the memory gate electrode 10 in the memory array region, the n ⁺ type semiconductor regions 17d and 17s, the wirings 8s and 10s in the shunt region, and the gate electrodes 14n, 14p, 15n, and 15p in the peripheral circuit region For example, a Co silicide layer 18 is formed as a silicide layer on the surface of each of the n ⁺ type semiconductor region 20n and the p ⁺ type semiconductor region 20p. At this time, since the first cap insulating film 3a and the second cap insulating film 3b are formed on the control gate electrode 8, the Co silicide layer 18 is not formed. For this reason, a short circuit between the Co silicide layer 18 formed on the surface of the memory gate electrode 10 and the upper portion of the control gate electrode 8 can be avoided.

  Through the steps so far, the selection MIS transistor and the memory MIS transistor in the memory array region are completed, and the n-channel MISFET and the p-channel MISFET in the peripheral circuit region are completed.

Next, as shown in FIG. 56, an insulating film 22 made of, for example, a silicon nitride film and an interlayer insulating film 23 made of a silicon oxide film are deposited as insulating films on the substrate 1 by CVD. Subsequently, using the photoresist film (not shown) formed on the interlayer insulating film 23 as a mask, the interlayer insulating film 23 and the insulating film 22 are dry-etched to contact the upper portion of the n ⁺ type semiconductor region 17d in the memory array region. Hole 24 is formed. At this time, the contact hole 25 is formed above the wiring 10s in the shunt region, and the contact hole 26 is formed above the wiring 8s. Further, contact holes 27 and 29 are formed above the n ⁺ type semiconductor region 20n in the peripheral circuit region, and contact holes 28 and 30 are formed above the p ⁺ type semiconductor region 20p.

  Subsequently, plugs 31 are formed inside the contact holes 24-30. In order to form the plug 31, for example, a Ti film, a TiN (titanium nitride) film, or a W film is deposited as a metal film inside the plug 31 and on the interlayer insulating film 23 by a sputtering method, and then a Ti film outside the plug 31 is formed. Then, the TiN film and the W film are removed by a chemical mechanical polishing method.

  At this time, the wiring 10s in the shunt region is formed on one side wall of the laminated film including the conductive film in the same layer as the control gate electrode 8, the first cap insulating film 3a, and the second cap insulating film 3b. Therefore, as shown in FIG. 56, even when the plug 31 for supplying power to the wiring 10s is formed so as to cover a part of the conductive film and the upper part of the wiring 10s, the conductive film and the wiring 10s are in the first state. Since the cap insulating film 3 a and the second cap insulating film 3 b are insulated, the conductive film and the wiring 10 s are not short-circuited via the plug 31.

  Further, since the plug 31 connected to the wiring 10s is formed above the element isolation portion 2, as shown in FIG. 56, when the plug 31 is formed over the substrate 1 from the wiring 10s. However, there is no short circuit with the p-type well 4 formed in the substrate 1. On the other hand, the first cap insulating film 3a and the second cap insulating film 3b deposited on the wiring 8s are removed in the step shown in FIG. Therefore, since the Co silicide layer 18 is formed on the wiring 8s, the plug 31 can be connected to the upper surface of the wiring 8s as shown in FIG.

  In FIG. 56, for simplification of description, the case where the plug 31 is formed only in one of the source region or the drain region of the low breakdown voltage MISFET and the high breakdown voltage MISFET in the peripheral circuit region is illustrated. Further, the subsequent steps are the same as those in the first embodiment, and the description thereof is omitted.

  In the present embodiment, the short-circuit prevention side wall insulating film 11 formed on the side wall of the control gate electrode 8 is formed using silicon oxide as the insulating film, but is not limited to silicon oxide, and silicon oxide For example, a silicon nitride film may be used instead of the film. That is, in the step shown in FIG. 44, after forming the laminated gate insulating film 9, a silicon nitride film is deposited on the laminated gate insulating film 9 by the CVD method, and this silicon nitride film is anisotropically etched. Then, it may be left on the side wall of the control gate electrode 8.

  When the sidewall insulating film 11 is formed of silicon nitride, as shown in FIG. 57, the thickness of the sidewall insulating film 11 is a ′, and the second potential barrier film 9c formed below the memory gate electrode 10 is used. It is desirable to form the sidewall insulating film 11 so that the relationship of a ′> b is established, where b is the thickness of the film. In this case, when the silicon nitride film (sidewall insulating film 11) is etched, the surface portion (second potential barrier film 9c) of the laminated gate insulating film 9 is hardly etched. Therefore, after the sidewall insulating film 11 is formed, the process of re-oxidizing the surface of the charge retention film 9b by the above-described ISSG oxidation method becomes unnecessary, or the re-oxidation processing time can be shortened.

  As described above, in the split gate type memory cell of the present embodiment, the first cap insulating film 3a and the second cap insulating film 3b are stacked on the control gate electrode 8, and the control gate electrode 8 and the first and second cap gate films are stacked. A side wall insulating film 11 is formed between the stacked gate insulating film 9 formed on one side wall of the stacked film made of the cap insulating films 3 a and 3 b and the memory gate electrode 10.

  As a result, the memory gate electrode 10 and the control gate electrode 8 are electrically separated from each other by the first and second cap insulating films 3a and 3b, the stacked gate insulating film 9 and the sidewall insulating film 11, and the control gate electrode 8 and the memory The distance from the upper end of the gate electrode 10 can be sufficiently separated. Therefore, even when the distance between the control gate electrode 8 and the memory gate electrode 10 becomes closer with the miniaturization of the memory cell, a short circuit between the control gate electrode 8 and the memory gate electrode 10 can be effectively avoided.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device having a split gate type memory cell.

DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 Element isolation | separation part 3a 1st cap insulating film 3b 2nd cap insulating film 4 p-type well 5 n-type well 6 Gate insulating film (high withstand voltage)
7 gate insulating film 8 control gate electrode 8a non-doped polycrystalline silicon film 8s wiring 8n n-type polycrystalline silicon film 8p p-type polycrystalline silicon film 9 stacked gate insulating film 9a first potential barrier film 9b charge holding film 9c second potential barrier Film 9d Second potential barrier film 10 Memory gate electrode 10n N-type polycrystalline silicon film 10s Wiring 11 Side wall insulating film 11a Silicon oxide film 12 Side wall insulating film 13d, 13s n ⁻ type semiconductor regions 14n, 14p, 15n, 15p Gate electrode 17d n ⁺ type semiconductor region (drain region)
17s n ⁺ type semiconductor region (source region)
18 Co silicide layer 19 n n ⁻ type semiconductor region 19 p p ⁻ type semiconductor region 20 n n ⁺ type semiconductor region (source, drain region)
20p p ⁺ type semiconductor region (source and drain regions)
22 insulating film 23 interlayer insulating film 24-30 contact hole 31 plug 32 second interlayer insulating film 33 wiring trenches 34, 35, 36 first layer wirings 40, 41, 42, 43, 44 photoresist film BL bit line MC ₁ , MC ₂ memory cell SL common source line

Claims (12)

A semiconductor device having a memory cell,
The memory cell is
A first gate insulating film formed on the semiconductor substrate;
A control gate electrode formed on the semiconductor substrate via the first gate insulating film;
A second potential barrier film is formed on one side wall of the control gate electrode and on the semiconductor substrate, and includes a first potential barrier film, a charge holding film, and a second potential barrier film formed in this order from the control gate electrode side. A gate insulating film;
A memory gate electrode insulated from the control gate electrode and the semiconductor substrate through the second gate insulating film;
A source region comprising a semiconductor region formed in the semiconductor substrate in the vicinity of the control gate electrode;
A drain region composed of a semiconductor region formed in the semiconductor substrate in the vicinity of the memory gate electrode;
Including
A silicide layer is formed on the control gate electrode and the memory gate electrode,
Wherein between the second gate insulating film formed on one side wall of the control gate electrode and between the memory gate electrode, the sidewall insulating films made of silicon oxide is formed,
The sum of the film thicknesses of the sidewall insulating film and the second potential barrier film formed on the sidewall of the control gate electrode is larger than the film thickness of the second potential barrier film formed below the memory gate electrode. A semiconductor device characterized by being thick.   2. The semiconductor device according to claim 1, wherein the first potential barrier film and the second potential barrier film are made of a silicon oxide film, and the charge holding film is made of a silicon nitride film. A semiconductor device having a memory cell,
The memory cell is
A first gate insulating film formed on the semiconductor substrate;
A control gate electrode formed on the semiconductor substrate via the first gate insulating film;
A second gate including a first potential barrier film, a charge holding film, and a second potential barrier film formed on one side wall of the control gate electrode and on the semiconductor substrate, and formed sequentially from the semiconductor substrate side. An insulating film;
A memory gate electrode insulated from the control gate electrode and the semiconductor substrate through the second gate insulating film;
A source region comprising a semiconductor region formed in the semiconductor substrate in the vicinity of the control gate electrode;
A drain region composed of a semiconductor region formed in the semiconductor substrate in the vicinity of the memory gate electrode;
Including
A silicide layer is formed on the control gate electrode and the memory gate electrode,
Wherein between the control and the second gate insulating film formed on one side wall of the gate electrode of the memory gate electrode, the sidewall insulating film made of silicon nitride is formed,
2. The semiconductor device according to claim 1, wherein a thickness of the sidewall insulating film is larger than a thickness of the second potential barrier film formed under the memory gate electrode. 4. The semiconductor device according to claim 3, wherein the first potential barrier film and the second potential barrier film are made of a silicon oxide film, and the charge holding film is made of a silicon nitride film. A method of manufacturing a semiconductor device having a memory cell,
The step of forming the memory cell includes:
(A) forming a well in the semiconductor substrate;
(B) forming a first gate insulating film on the semiconductor substrate;
(C) forming a control gate electrode on the first gate insulating film;
(D) After the step (b), a first potential barrier film, a charge holding film, and a second potential barrier film are sequentially formed on the semiconductor substrate, and the first potential barrier film, the charge holding film, and Forming a second gate insulating film comprising a laminated film of the second potential barrier film;
(E) depositing a first insulating film made of silicon oxide on the second gate insulating film;
(F) forming a sidewall insulating film made of the first insulating film on both side walls of the control gate electrode by patterning the first insulating film;
(G) After the step (f), a step of depositing a first conductive film on the semiconductor substrate;
(H) forming a memory gate electrode made of the first conductive film on both side walls of the control gate electrode by patterning the first conductive film;
(I) the memory gate electrode, the sidewall insulation film, and by patterning the second gate insulating film, leaving the memory gate electrode and the sidewall insulating film only on the one side wall of the control gate electrode, wherein Leaving a second gate insulating film on one side wall of the control gate electrode and a lower portion of the memory gate electrode;
(J) After the step (i), by introducing impurities into the semiconductor substrate, a source region is formed in the semiconductor substrate in the vicinity of the control gate electrode, and in the semiconductor substrate in the vicinity of the memory gate electrode Forming a drain region;
(K) forming a silicide layer on the control gate electrode and the memory gate electrode;
Including
The sum of the film thicknesses of the sidewall insulating film and the second potential barrier film formed on the sidewall of the control gate electrode is larger than the film thickness of the second potential barrier film formed below the memory gate electrode. A method of manufacturing a semiconductor device, wherein the semiconductor device is thick. After the step (f), prior to the step (g),
6. The method of manufacturing a semiconductor device according to claim 5 , further comprising the step of increasing the thickness of the second potential barrier film. 7. The method of manufacturing a semiconductor device according to claim 6 , wherein the process of increasing the thickness of the second potential barrier film is a process of reoxidizing the surface of the second potential barrier film by an ISSG oxidation method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first potential barrier film and the second potential barrier film are made of a silicon oxide film, and the charge retention film is made of a silicon nitride film. A method of manufacturing a semiconductor device having a memory cell,
The step of forming the memory cell includes:
(A) forming a well in the semiconductor substrate;
(B) forming a first gate insulating film on the semiconductor substrate;
(C) forming a control gate electrode on the first gate insulating film;
(D) After the step (b), a first potential barrier film, a charge holding film, and a second potential barrier film are sequentially formed on the semiconductor substrate, and the first potential barrier film, the charge holding film, and Forming a second gate insulating film comprising a laminated film of the second potential barrier film;
(E) depositing a first insulating film made of silicon nitride on the second gate insulating film;
(F) forming a sidewall insulating film made of the first insulating film on both side walls of the control gate electrode by patterning the first insulating film;
(G) After the step (f), a step of depositing a first conductive film on the semiconductor substrate;
(H) forming a memory gate electrode made of the first conductive film on both side walls of the control gate electrode by patterning the first conductive film;
(I) patterning the memory gate electrode, the sidewall insulating film, and the second gate insulating film to leave the memory gate electrode and the sidewall insulating film only on one sidewall of the control gate electrode; a step of leaving the second gate insulating film in the lower portion of said one side wall and the memory gate electrode of the control gate electrode,
(J) After the step (i), by introducing impurities into the semiconductor substrate, a source region is formed in the semiconductor substrate in the vicinity of the control gate electrode, and in the semiconductor substrate in the vicinity of the memory gate electrode Forming a drain region;
(K) forming a silicide layer on the control gate electrode and the memory gate electrode;
Including
The sidewall insulating film thickness of the film, a method of manufacturing a semiconductor device, characterized in that greater thickness than said second potential barrier layer formed in the lower portion of the memory gate electrode. After the step (f), prior to the step (g),
10. The method of manufacturing a semiconductor device according to claim 9 , further comprising the step of increasing the thickness of the second potential barrier film. 11. The method of manufacturing a semiconductor device according to claim 10 , wherein the process of increasing the thickness of the second potential barrier film is a process of reoxidizing the surface of the second potential barrier film by an ISSG oxidation method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first potential barrier film and the second potential barrier film are made of a silicon oxide film, and the charge holding film is made of a silicon nitride film.

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