JP5533398B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a via is provided in a semiconductor substrate.

  2. Description of the Related Art A technique is known in which a via is provided in a semiconductor substrate used in a semiconductor device and conduction is made between the front and back surfaces of the semiconductor device using the via. Such a semiconductor device is used, for example, in a device having a stack structure in which a plurality of them are stacked and electrically connected to each other.

Special table 2009-524220 JP 2007-165461 A

  When manufacturing a semiconductor device in which a via is provided in a semiconductor substrate, the manufacturing process may be complicated because the via is formed in the semiconductor substrate in addition to an element such as a transistor.

  According to an aspect of the present invention, a step of forming a first opening in a semiconductor substrate, a step of forming a first insulating film on an inner wall of the first opening, and the step of forming the first insulating film Forming a filling material in the first opening; a first dummy gate electrode on the first opening in which the filling material is formed; and a second dummy gate electrode on the semiconductor substrate on a region where a transistor is to be formed. Forming a dummy gate electrode; forming a second insulating film covering the first dummy gate electrode and the second dummy gate electrode on the semiconductor substrate; and A step of exposing the first dummy gate electrode and the second dummy gate electrode, the first dummy gate electrode, and the filling material formed in the first opening are removed to form a second opening. The second Removing the me gate electrode to form a third opening; forming a conductive material in the second opening and the third opening; forming a via in the second opening; and Forming a gate electrode on the part, and a method for manufacturing a semiconductor device.

  According to the disclosed method, a semiconductor device having a via provided in a semiconductor substrate can be manufactured while suppressing the complexity of the manufacturing process.

It is explanatory drawing (the 1) of an example of a semiconductor device formation method. It is explanatory drawing (the 2) of an example of a semiconductor device formation method. It is explanatory drawing (the 3) of an example of a semiconductor device formation method. It is explanatory drawing (the 4) of an example of a semiconductor device formation method. It is explanatory drawing (the 5) of an example of a semiconductor device formation method. It is explanatory drawing (the 6) of an example of a semiconductor device formation method. It is explanatory drawing (the 7) of an example of a semiconductor device formation method. It is explanatory drawing (the 8) of an example of a semiconductor device formation method. It is explanatory drawing (the 9) of an example of a semiconductor device formation method. It is explanatory drawing (the 10) of an example of a semiconductor device formation method. It is explanatory drawing (the 11) of an example of a semiconductor device formation method. It is explanatory drawing (the 12) of an example of a semiconductor device formation method. It is explanatory drawing (the 13) of an example of a semiconductor device formation method. It is explanatory drawing (the 14) of an example of a semiconductor device formation method. It is explanatory drawing (the 15) of an example of a semiconductor device formation method. It is explanatory drawing of the modification of the semiconductor device formation method.

  1 to 15 are explanatory diagrams of an example of a semiconductor device forming method. Here, a method for forming a semiconductor device having a transistor structure including a metal gate electrode and a through silicon via (TSV) filled with metal will be described as an example. Hereinafter, the formation method will be described in order.

  First, the process shown in FIG. 1 will be described. 1A is a schematic cross-sectional view of the main part of the trench forming process, FIG. 1B is a schematic cross-sectional view of the main part of the insulating film forming process, and FIG. 1C is a schematic cross-sectional view of the main part of the insulating film polishing process. is there.

  Here, a silicon (Si) substrate 1 is used as the semiconductor substrate. First, a silicon oxide (SiO) film 2 and a silicon nitride (SiN) film 3 are formed on a Si substrate 1 as shown in FIG. The SiO film 2 is formed with a film thickness of 10 nm, for example. The SiN film 3 is formed with a film thickness of 90 nm, for example. Next, as shown in FIG. 1A, a trench 4 that penetrates the SiN film 3 and the SiO film 2 and reaches the inside of the Si substrate 1 is formed. The trench 4 is formed, for example, at a depth of 300 nm from the surface of the Si substrate 1.

After the trench 4 is formed, a SiO film 5 is formed so as to fill the trench 4 as shown in FIG. The SiO film 5 is formed with a film thickness of 500 nm, for example.
After the trench 4 is filled with the SiO film 5, as shown in FIG. 1C, the SiO film 5 formed on the upper surface of the SiN film 3 is removed by polishing using the SiN film 3 as a stopper. This polishing can be performed by CMP (Chemical Mechanical Polishing).

  Through the steps so far, an STI (Shallow Trench Isolation) 5a in which the SiO film 5 is buried in the trench 4 is formed. Note that a region defined by the STI 5a is a region (element region) AR for forming a transistor structure.

Next, the process shown in FIG. 2 will be described. FIG. 2A is a schematic cross-sectional view of the main part of the via hole forming process, and FIG. 2B is a schematic cross-sectional view of the main part of the insulating film forming process.
After the formation of the STI 5a, a via hole (opening) 6 that penetrates the SiN film 3 and the SiO film 2 and reaches the inside of the Si substrate 1 is formed. The via hole 6 is formed in a region where a TSV that finally penetrates the Si substrate 1 is formed. Here, as an example, a case where via holes 6 are formed at four locations outside the element region AR is shown. Each via hole 6 is formed with a depth of 30 μm to 50 μm and a diameter of 100 nm to 200 nm from the surface of the Si substrate 1, for example.

  After the via hole 6 is formed, an insulating film 7 is formed on the inner wall of the via hole 6 as shown in FIG. For example, when a material containing metal is embedded in the via hole 6 as described later, the insulating film 7 suppresses diffusion of such a material into the Si substrate 1 and silicidation of the surface of the Si substrate 1. 1 serves to suppress the occurrence of a leak current to 1. As such an insulating film 7, for example, a SiO film having a film thickness of 5 nm to 20 nm is formed.

When an SiO film is formed as the insulating film 7, the SiO film can be formed, for example, by oxidizing the Si substrate 1 exposed on the inner surface of the via hole 6. The thickness of the SiO film formed by oxidation can be controlled by heat treatment conditions. For example, after the via hole 6 is formed, heat treatment is performed in an oxidizing atmosphere (for example, an atmosphere containing oxygen (O ₂ ) and hydrogen chloride (HCl)) at 900 ° C. for 30 minutes, thereby forming a Si substrate on the inner surface of the via hole 6. 1 is thermally oxidized. By performing thermal oxidation, a SiO film with good film quality can be formed as the insulating film 7 on the inner surface of the via hole 6. FIG. 2B illustrates the case where an SiO film is formed as the insulating film 7 using such a thermal oxidation method.

  The SiO film formed as the insulating film 7 can be formed by using, for example, a CVD (Chemical Vapor Deposition) method in addition to such a thermal oxidation method. For example, CVD is performed under a relatively high temperature condition such as 700 ° C. to form a SiO film. Although not shown here, when the SiO film is formed using the CVD method in this way, the SiO film is formed not only on the inner surface of the via hole 6 but also on the upper surface of the SiN film 3. Become.

  As described above, the insulating film 7 can be formed by a thermal oxidation method or a CVD method, but when the insulating film 7 is formed, a relatively high temperature condition of 500 ° C. or higher can be used. This is because even if high-temperature heat treatment is performed at this stage, the transistor structure is not yet formed in the element region AR, so that the transistor structure is not defective when heated at a high temperature.

Next, the process shown in FIG. 3 will be described. FIG. 3A is a schematic cross-sectional view of the main part of the first sacrificial layer forming step, and FIG. 3B is a schematic cross-sectional view of the main part of the first sacrificial layer polishing step.
After the formation of the insulating film 7, a sacrificial layer 8a (filling material) is formed on the surface including the inside of the via hole 6 as shown in FIG. As the sacrificial layer 8a, for example, a polysilicon layer having a thickness of 200 nm to 300 nm is formed.

  After the formation of the sacrificial layer 8a, as shown in FIG. 3B, the sacrificial layer 8a formed on the upper surface of the SiN film 3 is removed by polishing using the SiN film 3 as a stopper. This polishing can be performed by CMP. As a result, the via hole 6 is filled with the sacrificial layer 8a.

Next, the process shown in FIG. 4 will be described. FIG. 4A is a schematic cross-sectional view of the relevant part in the insulating film removing step, and FIG. 4B is a schematic cross-sectional view of the relevant part in the gate insulating film forming step.
After filling the via hole 6 with the sacrificial layer 8a, the SiN film 3 and the SiO film 2 formed on the surface of the Si substrate 1 are removed, thereby obtaining a state as shown in FIG. Here, the SiN film 3 is selectively removed using phosphoric acid (H ₃ PO ₄ ), for example. The SiO film 2 is selectively removed using, for example, hydrofluoric acid (HF). When the SiO film 2 is selectively removed using HF, the portion of the STI 5a protruding from the Si substrate 1 can also be removed, and FIG. 4A illustrates such a state.

  After the removal of the SiN film 3 and the SiO film 2, as shown in FIG. 4B, the gate insulating film 9 is formed on the Si substrate 1 including the STI 5a and the via hole 6 in which the insulating film 7 and the sacrificial layer 8a are formed. Form. The gate insulating film 9 is formed with a film thickness of 3 nm, for example.

  For the gate insulating film 9, for example, a high dielectric constant (High-k) material is used. For example, the gate insulating film 9 having a stacked structure including a high-k film such as hafnium oxide (HfO) on the upper layer side and an SiO film on the lower layer side is formed. In this case, nitrogen (N), Si, or the like may be added to the upper HfO film (HfON film, HfOSi film, HfONSi film), and N may be added to the lower SiO film. (SiON film). The gate insulating film 9 having such a stacked structure can be formed, for example, by forming a high-k film on the Si substrate 1 and then performing a heat treatment in an oxidizing atmosphere. Here, an HfO-based film is exemplified as the High-k film, but a zirconium oxide (ZrO) -based film can also be formed.

  Although not shown here, a work function control layer for controlling the work function of a gate electrode (metal gate electrode) to be formed later may be formed on the gate insulating film 9. For the work function control layer, for example, titanium nitride (TiN) or titanium aluminum nitride (TiAlN) to which aluminum (Al) is added can be used. Whether to form TiN or TiAlN may be selected according to the channel conductivity type of the transistor structure to be formed. The work function control layer is formed with a film thickness of 3 nm to 10 nm, for example.

Next, the process shown in FIG. 5 will be described. FIG. 5A is a schematic cross-sectional view of a relevant part in a gate insulating film removing step, and FIG. 5B is a schematic cross-sectional view of a relevant part in a second sacrificial layer and hard mask forming step.
After the gate insulating film 9 is formed (when the work function control layer is formed, after forming the work function control layer), resist formation, exposure and development are performed, and as shown in FIG. A resist pattern 10 having an opening 10 a is formed in a region corresponding to 6. Then, etching is performed using the resist pattern 10 as a mask, and the gate insulating film 9 (or the gate insulating film 9 and the work function control layer) on the via hole 6 is removed. Thereby, the state as shown in FIG.

After the etching using such a resist pattern 10, the resist pattern 10 is removed.
After the resist pattern 10 is removed, as shown in FIG. 5B, a sacrificial layer 8b is formed on the surface after the resist pattern 10 is removed, and a hard mask 11 is further formed thereon. As the sacrificial layer 8b, for example, a polysilicon layer with a thickness of 80 nm is formed. As the hard mask 11, for example, a SiN film having a thickness of 50 nm is formed. The hard mask 11 serves as a mask for processing a dummy gate, which will be described later, and as a stopper during CMP.

  The sacrificial layer 8b formed here and the sacrificial layer 8a previously formed in the via hole 6 are finally removed as will be described later. In order to remove the sacrificial layer 8a formed in the via hole 6, the gate insulating film 9 on the via hole 6 (except on the insulating film 7) is removed at this stage as described above. In this case, it is preferable that the gate insulating film 9 is not left inside the insulating film 7 on the via hole 6. If the gate insulating film 9 remains on the inner side of the insulating film 7 on the via hole 6, the opening of the via hole 6 is narrowed by the gate insulating film 9, and depending on the removal method of the sacrificial layer 8a, This is because the embedded sacrificial layer 8b may be difficult to remove.

  From this point of view, when forming the resist pattern 10 shown in FIG. 5A, a resist pattern 10 having an opening 10a larger than the diameter of the via hole 6 is formed in a region corresponding to the via hole 6, and this is used as a mask. Etching may be performed.

  FIG. 5A illustrates the case where the gate insulating film 9 (or the gate insulating film 9 and the work function control layer) on each via hole 6 is removed. However, a wider area including a plurality of via holes 6 is illustrated. For the region, the gate insulating film 9 and the like may be removed. FIG. 16 shows a schematic cross-sectional view of an essential part of another example of the gate insulating film removing step.

  For example, as shown in FIG. 16, a resist pattern 10 having an opening 10b is formed in a region including a plurality (here, four) of via holes 6, and etching is performed using the resist pattern 10 as a mask. Thereby, the gate insulating film 9 and the like on each via hole 6 and its surroundings are also removed. After removing the gate insulating film 9 and the like as shown in FIG. 16, the resist pattern 10 is removed and the sacrificial layer 8b and the hard mask 11 may be formed in the same manner as described above.

However, in the following description, the case where the gate insulating film 9 and the like are removed by the method shown in FIG. 5 will be described as an example.
The sacrificial layers 8a and 8b can be made of the same material or different materials, but are preferably made of the same material in order to simplify the removal process.

  Next, the process shown in FIG. 6 will be described. 6A is a schematic cross-sectional view of the main part of the dummy gate processing step, FIG. 6B is a schematic cross-sectional view of the main part of the first impurity diffusion region forming step, and FIG. 6C is the formation of the second impurity diffusion region and the like. It is a principal part cross-sectional schematic diagram of a process.

  After the formation of the sacrificial layer 8b and the hard mask 11, dummy gate processing is performed using the hard mask 11 as shown in FIG. Thereby, dummy gate electrodes 12a and 12b are formed on the element region AR defined by the STI 5a and on the via hole 6 filled with the sacrificial layer 8a, respectively. Here, the laminated structure portion of the sacrificial layer 8b and the hard mask 11 is referred to as dummy gate electrodes 12a and 12b.

  The dummy gate processing for forming such dummy gate electrodes 12a and 12b can be performed by etching. In that case, first, etching for patterning the hard mask 11 into a predetermined shape is performed, and the sacrificial layer 8b is etched using the etching as a mask. After the dummy gate electrodes 12a and 12b are thus formed, the lower gate insulating film 9 (or the gate insulating film 9 and the work function control layer) is further etched using the hard mask 11 as a mask.

  After the above processing, as shown in FIG. 6B, extension regions (source and drain regions) are formed in the Si substrate 1 on both sides of the dummy gate electrode 12a formed in the element region AR. An impurity diffusion region 13 to be a part of is formed. The impurity diffusion region 13 is formed by implanting ions of a predetermined conductivity type into a relatively shallow region at a relatively low concentration.

  After the formation of the impurity diffusion region 13, first, as shown in FIG. 6C, sidewalls 14 are formed on the sidewalls of the dummy gate electrodes 12a and 12b. For the sidewall 14, for example, a SiO film is used. When the sidewall 14 is formed, a SiO film is formed on the Si substrate 1 after the formation of the impurity diffusion region 13 so as to cover the dummy gate electrodes 12a and 12b obtained after the above processing (for example, 10 nm). ) And etch back it. As a result, sidewalls 14 as shown in FIG. 6C are formed on the sidewalls of the dummy gate electrodes 12a and 12b.

  After the sidewall 14 is formed, as shown in FIG. 6C, impurity diffusion regions 15 to be a source region and a drain region are formed in the Si substrate 1 on both sides of the dummy gate electrode 12a formed in the element region AR. Form. The impurity diffusion region 15 is formed by implanting ions of a predetermined conductivity type into a relatively deep region at a relatively high concentration.

  After the process up to the formation of the impurity diffusion region 15 is performed in this manner, a predetermined heat treatment is performed to activate the impurity implanted into the impurity diffusion region 15 and the impurity diffusion region 13 formed earlier.

  A silicide layer 16 may be formed on the surface layer portion of the impurity diffusion region 15 in the element region AR, as shown in FIG. For example, a metal such as nickel (Ni) or cobalt (Co) is deposited, heat treated to react with the Si substrate 1 (surface layer portion of the impurity diffusion region 15), and then unreacted metal is removed, thereby forming a silicide. Layer 16 is formed.

  As described above, the transistor structure TR including the dummy gate electrode 12a having the sidewalls 14 formed on the sidewalls, the source region, and the drain region is formed in the element region AR. A dummy gate electrode 12b having a sidewall 14 formed on the side wall is formed on the via hole 6.

  When forming the transistor structure TR as shown in FIG. 6, the insulating film 7 has already been formed on the inner wall of the via hole 6 as shown in FIG. 2. Therefore, when forming the transistor structure TR, temperature conditions suitable for the formation (temperature conditions when forming the impurity diffusion regions 13 and 15 and the silicide layer 16) can be used. In other words, when the insulating film 7 is formed on the inner wall of the via hole 6, the insulating film 7 can be formed using conditions higher than the temperature suitable for forming the transistor structure TR.

  If the insulating film 7 on the inner wall of the via hole 6 is to be formed after the transistor structure TR is formed, it is difficult to apply a high temperature in order to suppress unnecessary impurity diffusion from the formed impurity diffusion regions 13 and 15. Although depending on the form of the transistor structure TR, when a relatively high temperature such as 500 ° C. or higher is applied, such unnecessary impurity diffusion is likely to occur. Further, if the via hole 6 as described above is formed after the transistor structure TR having a metal gate electrode such as an Al gate electrode is formed, and the insulating film 7 is formed on the inner wall thereof, the metal gate electrode is formed. Therefore, it is difficult to form the insulating film 7 under high temperature conditions.

  On the other hand, as described above, when the via hole 6 is formed before the transistor structure TR is formed and the insulating film 7 is formed on the inner wall thereof, the insulating film 7 can be formed under a relatively high temperature condition. Thus, since the insulating film 7 can be formed under high temperature conditions, the insulating film 7 with good film quality can be formed on the inner wall of the via hole 6. Therefore, even when a material containing a metal is buried in the via hole 6 as will be described later, the insulating film 7 having a good film quality suppresses diffusion or the like of the material into the Si substrate 1, Leakage current can be effectively suppressed.

Next, the process shown in FIG. 7 will be described. FIG. 7A is a schematic cross-sectional view of the relevant part in the dummy gate electrode covering step, and FIG. 7B is a schematic cross-sectional view of the relevant part in the dummy gate electrode exposing step.
After the formation of the dummy gate electrodes 12a and 12b and the transistor structure TR, as shown in FIG. 7A, an insulating film 17 is formed on the Si substrate 1 so as to cover the dummy gate electrodes 12a and 12b. As the insulating film 17, for example, a 300 nm-thickness SiO film is formed.

  After the formation of the insulating film 17, a process for exposing the dummy gate electrodes 12a and 12b from the insulating film 17 is performed as shown in FIG. Here, CMP is performed using the hard mask 11 as a stopper, and the insulating film 17 is polished until the upper surfaces (hard mask 11) of the dummy gate electrodes 12a and 12b are exposed.

Next, the process shown in FIG. 8 will be described. FIG. 8A is a schematic cross-sectional view of the main part of the hard mask removing process, and FIG. 8B is a schematic cross-sectional view of the main part of the sacrificial layer removing process.
After the dummy gate electrodes 12a and 12b are exposed from the insulating film 17, first, the exposed hard mask 11 of the dummy gate electrodes 12a and 12b is removed to obtain a state as shown in FIG. The removal of the hard mask 11 can be performed by wet etching or dry etching. As described above, by forming the hard mask 11 with SiN, the insulating film 17 with SiO, and the sacrificial layer 8b with polysilicon, the SiN hard mask 11 is formed with the SiO insulating film 17 and the polysilicon. The sacrificial layer 8b can be selectively removed.

  After the hard mask 11 is removed, the sacrificial layers 8a and 8b are removed to obtain a state as shown in FIG. The sacrifice layers 8a and 8b can be removed by wet etching or dry etching. As described above, the sacrificial layers 8a and 8b are formed of polysilicon, the insulating films 7 and 17 are formed of SiO, and the gate insulating film 9 is formed of a high-k material. 8b can be selectively removed with respect to the insulating films 7, 17, and the like.

  The sacrificial layer 8b on the element region AR side and the sacrificial layers 8a and 8b on the via hole 6 side can be removed by the same process. That is, both the element region AR side and the via hole 6 side are exposed to the same etching (wet etching or dry etching) environment, and the sacrificial layers 8a and 8b are removed.

  Further, the sacrificial layer 8b on the element region AR side and the sacrificial layers 8a and 8b on the via hole 6 side can be removed by separate processes. For example, the sacrificial layer 8b is removed by exposing the element region AR side to the etching environment by masking the via hole 6 side, and then the via hole 6 side is exposed to the etching environment by masking the element region AR side. The sacrificial layers 8a and 8b are removed. Of course, after the sacrificial layers 8a and 8b on the via hole 6 side are removed first, the sacrificial layer 8b on the element region AR side may be removed.

  By removing the hard mask 11 and the sacrificial layers 8a and 8b as described above, the dummy gate electrode 12a (the hard mask 11 and the sacrificial layer 8b) is formed on the element region AR side as shown in FIG. 8B. An opening 18 is formed in the portion from which is removed. Further, as shown in FIG. 8B, an opening 19 is formed on the via hole 6 side in a portion where the dummy gate electrode 12b (hard mask 11 and sacrificial layer 8b) and the sacrificial layer 8a therebelow are removed. The

  Since the sacrificial layers 8a and 8b are removed in this way, the gate insulating film 9 on the via hole 6 is removed in advance as described above (FIG. 5 or FIG. 16). If the gate insulating film 9 remains inside the insulating film 7 on the via hole 6, the gate insulating film 9 looks like a ridge and the opening of the via hole 6 becomes narrow. In that case, depending on the etching conditions, for example, it may be difficult to remove the sacrificial layer 8a by dry etching. In addition, during wet etching, the etchant may easily stay in the via hole 6. From such a viewpoint, as shown in FIG. 5 or FIG. 16, the gate insulating film 9 is preferably removed from the via hole 6 so as not to remain inside the insulating film 7.

  Next, the process shown in FIG. 9 will be described. FIG. 9A is a schematic cross-sectional view of the main part of the barrier metal film and conductive material forming step, and FIG. 9B is a schematic cross-sectional view of the main part of the barrier metal film and conductive material polishing step.

  After the openings 18 and 19 are formed, first, as shown in FIG. 9A, a barrier metal film 20 is formed in the openings 18 and 19 and on the upper surface of the insulating film 17. For the barrier metal film 20, for example, one or more of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and TiN can be used. For example, a TiN film having a thickness of 5 nm is formed as the barrier metal film 20.

  After the barrier metal film 20 is formed, a conductive material 21 is formed thereon as shown in FIG. Both the openings 18 and 19 are filled with the conductive material 21. Here, a metal material such as Al is used as the conductive material 21. For example, an Al film having a thickness of 200 nm to 300 nm is formed using a CVD method.

  After the barrier metal film 20 and the conductive material 21 are formed in this way, as shown in FIG. 9B, the conductive material 21 and the barrier metal film 20 formed on the upper surface of the insulating film 17 are removed by polishing. To do. This polishing can be performed by CMP using the insulating film 17 as a stopper. 9B, the conductive material 21 embedded in the opening 18 on the element region AR side and the conductive material 21 embedded in the opening 19 on the via hole 6 side are separated. . Thereby, the gate electrode 18a (metal gate electrode) is formed in the opening 18 on the element region AR side, and the transistor structure TR including the gate electrode 18a is formed. On the other hand, the via 19a is formed in the opening 19 on the via hole 6 side. Is formed. That is, the gate electrode 18a and the via 19a are simultaneously formed at this stage.

  In addition, since the insulating film 7 having a good film quality formed under a relatively high temperature condition is formed on the inner wall of the via hole 6 provided in the Si substrate 1, the Si substrate 1 of the conductive material 21 of the via 19a is formed. And the reaction (silicidation) between the barrier metal film 20 and the Si substrate 1 can be suppressed. Thereby, the leakage current from the via 19a to the Si substrate 1 can be effectively suppressed.

  As described above, when the gate electrode 18a is formed, the via 19a is also formed at the same time. Henceforth, a wiring structure such as a multilayer wiring is formed on the substrate after the gate electrode 18a and the via 19a are formed. Can do.

Next, the process shown in FIG. 10 will be described. FIG. 10A is a schematic cross-sectional view of the relevant part in the interlayer insulating film forming step, and FIG. 10B is a schematic cross-sectional view of the relevant part in the plug forming step.
After the formation of the gate electrode 18a and the via 19a, first, as shown in FIG. 10A, an interlayer insulating film 31 is formed on the substrate after the formation of the gate electrode 18a and the via 19a. For example, a 200 nm-thickness SiO film is formed as the interlayer insulating film 31.

  After the formation of the interlayer insulating film 31, as shown in FIG. 10B, the interlayer insulating film 31 and the insulating film 17 are penetrated, and the source region and drain region (impurity diffusion regions 13 and 15 and silicide layer) of the transistor structure TR The plug 32a reaching 16) is formed. Further, a plug 32b that penetrates the interlayer insulating film 31 and reaches the via 19a is also formed. For the plugs 32a and 32b, for example, a metal material such as tungsten (W) can be used. The plugs 32a and 32b can have a structure in which a metal material such as W is formed via a barrier metal film containing Ti, Ta, or the like.

Next, the process shown in FIG. 11 will be described. FIG. 11 is a schematic cross-sectional view of the relevant part in the first wiring layer forming step.
After the formation of the plugs 32a and 32b, as shown in FIG. 11, an insulating film 33 that functions as an etching stopper or a diffusion preventing film is formed, and an interlayer insulating film 34 is further formed thereon. As the insulating film 33, for example, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film having a thickness of 30 nm is formed. Further, as the interlayer insulating film 34, for example, a silicon carbide oxide (SiOC) film having a thickness of 100 nm is formed.

  After the formation of the insulating film 33 and the interlayer insulating film 34, wirings 35a and 35b are formed which penetrate through them and are electrically connected to the previously formed plugs 32a and 32b. Such wirings 35a and 35b can be formed by, for example, a damascene process. For the wirings 35a and 35b, for example, a metal material such as copper (Cu) can be used. The wirings 35a and 35b can have a structure in which a metal material such as Cu is formed through a barrier metal film containing Ti or Ta.

The first wiring layer L1 is formed by the process shown in FIG.
Next, the process shown in FIG. 12 will be described. FIG. 12 is a schematic cross-sectional view of the relevant part in the second wiring layer forming step.

  After the formation of the wirings 35a and 35b, as shown in FIG. 12, an insulating film 36 that functions as an etching stopper or a diffusion prevention film is formed, and an interlayer insulating film 37 is further formed thereon. For example, a 30 nm-thick SiC film or SiCN film is formed as the insulating film 36. Further, as the interlayer insulating film 37, for example, a SiOC film having a thickness of 200 nm to 300 nm is formed.

  After the formation of the insulating film 36 and the interlayer insulating film 37, a via 38 and a wiring 39a electrically connected to the wiring 35a or the transistor structure TR, and a wiring 39b electrically connected to the wiring 35b are formed. Such vias 38 and wirings 39a and 39b can be formed by, for example, a dual damascene process. For the via 38 and the wirings 39a and 39b, for example, a metal material such as Cu can be used. The via 38 and the wirings 39a and 39b can have a structure in which a metal material such as Cu is formed through a barrier metal film containing Ti or Ta.

By the process shown in FIG. 12, the second wiring layer L2 is formed.
In the case of forming a multilayer wiring including three or more wiring layers, the third wiring layer L3 to the nth wiring layer electrically connected to the first and second wiring layers L1 and L2 in the same manner thereafter. Up to Ln is formed.

Next, the process shown in FIG. 13 will be described. FIG. 13 is a schematic sectional view showing an important part of a plug and pad forming process.
After the process up to the formation of the n-th wiring layer Ln, as shown in FIG. 13, insulating films 40 and 41 are formed, and for example, a plug 42 electrically connected to the via 19a is formed. As the insulating film 40, for example, a SiC film or a SiCN film with a thickness of 30 nm is formed, and as the insulating film 41, for example, a SiO film with a thickness of 200 nm is formed. For the plug 42, for example, a metal material such as W can be used. The plug 42 can have a structure in which a metal material such as W is formed through a barrier metal film containing Ti, Ta, or the like.

  After the plug 42 is formed, a pad 43 electrically connected to the plug 42 is formed and covered with a protective film 44. For the pad 43, for example, a metal material such as Al can be used. The protective film 44 is formed of, for example, a 100 nm-thickness SiO film, and plays a role of protecting the pad 43 formed of Al or the like from moisture.

  After the formation of the pad 43 and the protective film 44, the cover film 45 is formed. As the cover film 45, for example, a SiN film having a film thickness of 500 nm is formed. A polyimide film 46 is formed on the cover film 45. Thereafter, an opening 47 reaching the pad 43 is formed through the polyimide film 46, the cover film 45, and the protective film 44, and the surface of the pad 43 is partially exposed. A bump 48 is formed on the exposed pad 43.

Through the steps shown in FIGS. 10 to 13, the wiring structure 30 formed on the substrate that has been formed up to the formation of the gate electrode 18a and the via 19a is obtained.
When forming a via that reaches the inside of the Si substrate during or after the formation of the wiring structure including the wiring layer, when forming the via hole by etching, films of different materials are repeatedly formed. It is necessary to etch. This complicates the etching process for forming a via hole reaching the inside of the Si substrate. Further, in the wiring structure, dummy wiring is often provided in order to ensure flatness of each layer by CMP performed in the formation process. However, when a via that reaches the inside of the Si substrate is formed during or after the formation of the wiring structure, the position where the via can be formed is affected by the arrangement of the dummy wiring. . Alternatively, it may happen that the flatness of each wiring layer in the wiring structure cannot be ensured by arranging the dummy wiring while avoiding the position where the via is formed.

  On the other hand, in the above forming method, the gate electrode 18a and the via 19a are completed at the same time (FIG. 9), and thereafter, the wiring structure 30 can be formed on them (FIGS. 10 to 13). Therefore, it is possible to prevent the etching process from becoming complicated. Even when dummy wirings are arranged in the wiring structure 30, it is possible to increase the degree of freedom of the arrangement and form the wiring structure 30 with good flatness. Furthermore, it is possible to suppress the position where the via 19a is formed from being affected by such dummy wiring.

Next, the process shown in FIG. 14 will be described. FIG. 14 is a schematic cross-sectional view of the main part of the back grinding process.
After the wiring structure 30 is formed as described above, back grinding is performed from the back side of the Si substrate 1 (the side opposite to the wiring structure 30 side). This back grinding is performed until the via 19a is exposed. Thereby, a TSV penetrating the Si substrate 1 is formed.

Next, the process shown in FIG. 15 will be described. FIG. 15 is a schematic sectional view showing an important part of a bump forming process.
After the TSV that exposes the via 19a on the back surface of the Si substrate 1 is formed as described above, the bump 49 is formed on the via 19a that is exposed on the back surface of the Si substrate 1. For example, a polyimide film 51 having an opening 50 in the formation region of the via 19 a is formed on the back surface of the Si substrate 1, and a bump 49 is formed in the opening 50.

  Through the above steps, a semiconductor device is obtained in which the bumps 48 and 49 on the front and back surfaces are electrically connected by the conductive portion including the via 19a, the plugs 32b and 42, and the wirings 35b and 39b to be conductive. .

  As described above, in the above method for forming a semiconductor device, the via hole 6 for TSV is formed before the transistor structure TR is formed, and the insulating film 7 with good film quality is formed on the inner wall thereof. Thereafter, the gate electrode 18a of the transistor structure TR and the via 19a for TSV are simultaneously formed by embedding the same conductive material and polishing it. Such a method makes it possible to manufacture a highly reliable semiconductor device having a TSV while suppressing the complexity of the manufacturing process.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Additional remark 1) The process of forming a 1st opening part in a semiconductor substrate,
Forming a first insulating film on the inner wall of the first opening;
Forming a filling material in the first opening in which the first insulating film is formed;
Forming a first dummy gate electrode on the first opening in which the burying material is formed and a second dummy gate electrode on a region of the semiconductor substrate where a transistor is to be formed;
Forming a second insulating film covering the first dummy gate electrode and the second dummy gate electrode on the semiconductor substrate;
Exposing the first dummy gate electrode and the second dummy gate electrode from the second insulating film;
The first dummy gate electrode and the filling material formed in the first opening are removed to form a second opening, and the second dummy gate electrode is removed to form a third opening. Process,
Forming a conductive material in the second opening and the third opening, forming a via in the second opening, and forming a gate electrode in the third opening;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 2) The said 1st insulating film is formed by oxidizing the said semiconductor substrate exposed to the inner surface of the said 1st opening part, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Supplementary Note 3) After the step of forming the filling material, before the step of forming the first dummy gate electrode and the second dummy gate electrode,
Forming a gate insulating film on a surface of the semiconductor substrate including a region where the transistor is formed and the first opening where the filling material is formed;
Selectively removing the gate insulating film on the first opening in which the filling material is formed;
The method for manufacturing a semiconductor device according to appendix 1 or 2, characterized by comprising:

  (Supplementary Note 4) After the step of forming the first dummy gate electrode and the second dummy gate electrode, and before the step of forming the second insulating film, a source region is formed in the semiconductor substrate in the region where the transistor is formed. And a method of manufacturing a semiconductor device according to any one of appendices 1 to 3, further comprising a step of forming a drain region.

  (Supplementary Note 5) The method of manufacturing a semiconductor device according to any one of Supplementary notes 1 to 4, wherein the filling material, the first dummy gate electrode, and the second dummy gate electrode are made of the same material.

(Supplementary Note 6) After the step of forming the second opening and the third opening, and before the step of forming the conductive material, in the second opening, in the third opening, and on the second insulating film Including a step of forming a barrier metal film,
The step of forming the conductive material includes:
Forming the conductive material on the barrier metal film;
Removing the conductive material and the barrier metal film formed on the second insulating film by polishing;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 5, characterized in that:

  (Supplementary Note 7) The method includes forming a wiring layer including conductive portions electrically connected to the via and the gate electrode, respectively, on a surface of the semiconductor substrate where the via and the gate electrode are formed. A method for manufacturing a semiconductor device according to any one of appendices 1 to 6.

  (Additional remark 8) The said semiconductor substrate is ground from the surface side opposite to the formation surface side of the said via | veer and the said gate electrode, The process of exposing the said via | veer to the said opposite surface side is included, The additional notes 1 thru | or characterized by the above-mentioned. 8. A method for manufacturing a semiconductor device according to claim 7.

1 Si substrate 2, 5 SiO film 3 SiN film 4 Trench 5a STI
6 Via hole 7, 17, 33, 36, 40, 41 Insulating film 8a, 8b Sacrificial layer 9 Gate insulating film 10 Resist pattern 10a, 10b, 18, 19, 47, 50 Opening 11 Hard mask 12a, 12b Dummy gate electrode 13 , 15 Impurity diffusion region 14 Side wall 16 Silicide layer 18a Gate electrode 19a, 38 Via 20 Barrier metal film 21 Conductive material 30 Wiring structure 31, 34, 37 Interlayer insulating film 32a, 32b, 42 Plug 35a, 35b, 39a, 39b Wiring 43 Pad 44 Protective film 45 Cover film 46, 51 Polyimide film 48, 49 Bump AR element region TR transistor structure L1-Ln Wiring layer

Claims (5)

Forming a first opening in a semiconductor substrate;
Forming a first insulating film on the inner wall of the first opening;
Forming a filling material in the first opening in which the first insulating film is formed;
Forming a first dummy gate electrode on the first opening in which the burying material is formed and a second dummy gate electrode on a region of the semiconductor substrate where a transistor is to be formed;
Forming a second insulating film covering the first dummy gate electrode and the second dummy gate electrode on the semiconductor substrate;
Exposing the first dummy gate electrode and the second dummy gate electrode from the second insulating film;
The first dummy gate electrode and the filling material formed in the first opening are removed to form a second opening, and the second dummy gate electrode is removed to form a third opening. Process,
Forming a conductive material in the second opening and the third opening, forming a via in the second opening, and forming a gate electrode in the third opening;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed by oxidizing the semiconductor substrate exposed on an inner surface of the first opening. 3. After the step of forming the filling material, before the step of forming the first dummy gate electrode and the second dummy gate electrode,
Forming a gate insulating film on a surface of the semiconductor substrate including a region where the transistor is formed and the first opening where the filling material is formed;
Selectively removing the gate insulating film on the first opening in which the filling material is formed;
The method for manufacturing a semiconductor device according to claim 1, wherein:   After the step of forming the first dummy gate electrode and the second dummy gate electrode and before the step of forming the second insulating film, a source region and a drain region are formed in the semiconductor substrate in the region where the transistor is to be formed. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming the semiconductor device. After the step of forming the second opening and the third opening, and before the step of forming the conductive material, a barrier metal film is formed in the second opening, in the third opening, and on the second insulating film. Including the step of forming
The step of forming the conductive material includes:
Forming the conductive material on the barrier metal film;
Removing the conductive material and the barrier metal film formed on the second insulating film by polishing;
5. The method of manufacturing a semiconductor device according to claim 1, comprising:

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