JP5527262B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a capacitor structure for removing high frequency noise.

  Conventionally, as disclosed in Patent Document 1, for the purpose of removing high-frequency noise, a capacitor constituted by another component is connected to a wiring pattern connected to the semiconductor chip on a circuit board on which the semiconductor chip is mounted. . However, such a noise elimination structure has a problem in that as the number of required capacitors increases, a space for arranging the capacitors is required, and the circuit board becomes large.

  Therefore, the structure shown in Patent Document 2 has been proposed. Specifically, a chip (interposer) with a built-in capacitor is prepared instead of on a circuit board, and this chip and a semiconductor chip are stacked and desired pads of each chip are electrically connected to each other. . With such a structure, it is possible to eliminate the need for a capacitor arrangement space and to reduce the size.

JP 57-188122 A JP 2002-334958 A

  However, in the structure in which a semiconductor chip and a chip with a built-in capacitor as described in Patent Document 2 are stacked, an empty area in the chip increases when the number of required capacitors is small. Also, if you want to change the capacitance of the capacitor, you must change the chip to something completely different. Furthermore, in a structure in which a semiconductor chip and a chip with a built-in capacitor are mounted, frequency adjustment cannot be individually performed later, making adjustment and maintenance difficult.

  In addition, there is a problem of misalignment when mounting a semiconductor chip and a chip with a built-in capacitor, and it is necessary to manufacture a chip with a built-in capacitor or mount it with a semiconductor chip in a complicated process. Therefore, the yield is low. Further, when only a part of the capacitor built in the chip is defective, there is a problem that the chip becomes defective.

  In view of the above, the present invention has a structure capable of removing high-frequency noise without using a chip incorporating a plurality of capacitors and without requiring a capacitor arrangement space on the circuit board. It is an object to provide a semiconductor device.

  In order to achieve the above object, in the first aspect of the present invention, a circuit including a signal line and a ground line is formed, and is connected to the chip signal line pad (41) connected to the signal line on one side and the ground line. The chip ground line pad (42) formed on the semiconductor chip (1), the chip signal line pad (41) and the chip ground line pad (42) are mounted alone, and the chip signal line pad (41) and The semiconductor device is constituted by a structure having a capacitor structure portion (2) electrically connected to the chip ground line pad (42). The capacitor structure part (2) includes a capacitor signal line (21) having a rod-like line part (21c) and a dielectric (22) surrounding the outer periphery of the line part (21c) provided in the capacitor signal line (21). ) And a capacitor ground line (23) having an annular portion (23a) surrounding the outer periphery of the dielectric (22), and a signal line outside the semiconductor chip (1) on one end side of the line portion (21c) Are electrically connected to the chip signal line pad (41) provided in the semiconductor chip (1) on the other end side of the line portion (21c) and the semiconductor chip (1). It is electrically connected to the chip grounding line pad (42) provided in (4).

  In this way, the single capacitor structure (2) is formed and mounted on the capacitor signal line pad (41) and the capacitor ground line pad (42) of the semiconductor chip (1). For example, when the capacitor structure (2) is mounted at a plurality of locations on the semiconductor chip (1), a pair of capacitor structures (2) are provided at each location, that is, one capacitor structure (2). Even with the capacitor structure (2) having such a structure, high-frequency noise can be removed. Further, it is not necessary to use a chip incorporating a plurality of capacitors, and the capacitor structure (2) can be individually arranged at a required place, so that a capacitor arrangement space is required on the circuit board. There is nothing.

  Therefore, it is possible to provide a semiconductor device having a structure capable of removing high-frequency noise without using a chip incorporating a plurality of capacitors and without requiring a capacitor arrangement space on the circuit board. .

  In the second aspect of the present invention, the capacitor structure portion (2) has the line portion (21c) divided into a plurality of portions, and the outer periphery of each of the divided line portions (21c) is surrounded by the annular portion (23a). A plurality of capacitor structures are provided, and a plurality of divided line portions (21c) are all connected to the same chip signal line pad (41).

  Thus, it can also be set as the structure provided with the several capacitor structure in one capacitor structure part (2). As a result, the capacity can be increased, and more effective noise removal can be achieved.

  In the invention according to claim 3, the first pad (21a) electrically connected to the line portion (21c) is provided on the upper surface of the capacitor structure portion (2) opposite to the semiconductor chip (1). The capacitor structure (2) is electrically connected to the signal line outside the semiconductor chip (1) through the first pad (21a).

  As described above, the first pad (21a) is provided on the upper surface of the capacitor structure (2), and the capacitor structure (2) and the signal line outside the semiconductor chip (1) are connected via the first pad (21a). The electrical connection can be made. For example, as described in claim 4, by connecting a bonding wire (7) to the first pad (21a), the capacitor structure (2) and the semiconductor chip (1) are connected via the bonding wire (7). Can be electrically connected to an external signal line.

  The invention according to claim 5 is characterized in that the bonding wire (7) is connected to a position corresponding to the line portion (21c) in the first pad (21a).

  The connecting position of the bonding wire (7) may be anywhere on the first pad (21a), but if it is made to coincide with the position corresponding to the line portion (21c), it is made of a flexible metal material. Since the thick line portion (21c) is present, it is possible to suppress the occurrence of cracks during bonding.

  In the invention described in claim 6, recesses (34, 81) having the same shape as the capacitor structure (2) are provided on one surface side of the semiconductor chip (1), and the semiconductor chip (1) The formed chip signal line pad (41) and chip ground line pad (42) are exposed in the recesses (34, 81), and the capacitor structure (2) is disposed in the recesses (34, 81). Thus, the capacitor signal line (21) and the chip signal line pad (41) are electrically connected to each other and the capacitor ground line (23) and the chip ground line pad (42) are arranged on the semiconductor chip (1). ) Is electrically connected.

  With such a structure, it is possible to easily align the semiconductor chip (1) and the capacitor structure (2) by fitting the capacitor structure (2) into the recesses (34, 81). It becomes. The capacitor structure portion (2) is electrically connected to the chip signal line pad (41) and the chip ground line pad (42) exposed from the recesses (34, 81). It is also possible to make an electrical connection between (2) and a signal line or a ground line formed on the semiconductor chip (1).

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is the perspective view of the semiconductor device shown in FIG. 1, and the elements on larger scale which expanded the capacitor structure part 2 among them. 2 is a cross-sectional view of the capacitor structure portion 2 and the semiconductor chip 1 and a diagram showing a planar layout at a broken line in the cross-sectional view. FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the capacitor structure 2 shown in FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing process of the capacitor structure 2 following FIG. 4. It is the figure which showed the cross-sectional view of the capacitor structure part 2 concerning 2nd Embodiment of this invention, and the semiconductor chip 1, and the planar layout in the broken-line location in the cross-sectional view. It is the figure which showed the cross-sectional view of the capacitor structure part 2 concerning 3rd Embodiment of this invention, and the semiconductor chip 1, and the plane layout in the broken-line location in the cross-sectional view. It is the figure which showed the cross-sectional view of the capacitor structure part 2 demonstrated by the modification of 3rd Embodiment, and the semiconductor chip 1, and the planar layout in the broken-line location in the cross-sectional view. It is sectional drawing of the capacitor structure part 2 and semiconductor chip 1 concerning 4th Embodiment of this invention. It is the figure which showed the cross-sectional view of the capacitor structure part 2 demonstrated by the modification of 4th Embodiment, and the semiconductor chip 1, and the planar layout in the broken-line location in the cross-sectional view. (A)-(d) is the figure which showed the planar layout of the capacitor structure part 2 and the recessed parts 34 and 81 which are demonstrated by other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. First, the configuration of the semiconductor device according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, a capacitor structure 2 is provided on the surface of a semiconductor chip 1. The semiconductor chip 1 is an LSI chip or the like in which elements are formed on a silicon substrate or the like, and a semiconductor integrated circuit including elements or the like is formed therein although not shown. An interlayer insulating film 3 is formed on the surface of the semiconductor chip 1, and contact holes 31 and 32 are formed in the interlayer insulating film 3, and pads 41 and 42 pass through the contact holes 31 and 32 in the semiconductor integrated circuit. Are electrically connected to a signal line and a GND line (not shown). Then, the signal line and the GND line of the capacitor structure part 2 are electrically connected to the signal line and the GND line of the semiconductor integrated circuit with respect to the pads 41 and 42, so that the signal line and the GND line of the capacitor structure part 2 are connected. It is structured to be electrically connected to signal lines and GND lines in the semiconductor integrated circuit. The pads 41 and 42 here correspond to a chip signal line pad and a chip ground line pad.

  The semiconductor chip 1 is mounted on the lead frame 5, and the back surface of the semiconductor chip 1 is bonded to the lead frame 5 via a bonding material 6. For example, when the back surface of the semiconductor chip 1 is a GND plane, the GND plane and the GND plane of the lead frame 5 are joined by bonding the GND plane to the lead frame 5 via solder, conductive adhesive or the like. Can be electrically connected.

  The capacitor structure 2 and the external connection terminal 51 of the lead frame 5 are electrically connected via the bonding wire 7, whereby the signal line of the capacitor structure 2 is electrically connected to the outside through the external connection terminal 51. It has a structure that can be connected to. Each part in such a form is molded with a mold resin (not shown), and a part of the external terminal 51 is exposed from the mold resin, so that the semiconductor device is configured.

  Next, a detailed structure of the capacitor structure unit 2 provided in the semiconductor device configured as described above will be described. FIG. 2 is a perspective view of the semiconductor device shown in FIG. 1 and a partially enlarged view of the capacitor structure 2 thereof. FIG. 3 is a cross-sectional view of the capacitor structure portion 2 and the semiconductor chip 1 and a plan layout at a broken line in the cross-sectional view.

  As shown in FIG. 2 and FIG. 3, the capacitor structure 2 includes a signal line (capacitor signal line) 21, a dielectric 22, a GND line (capacitor ground line) 23, and an insulating film 24.

  The signal line 21 is provided so as to reach the lower surface from the upper surface of the capacitor structure portion 2, and the first pad 21 a is formed at the exposed portion of the upper surface and the second pad 21 b is formed at the exposed portion of the lower surface. And the signal line 21 is comprised by providing the line part 21c from the 1st pad 21a to the 2nd pad 21b. The first pad 21a is a portion connected to the bonding wire 7 and is an external connection terminal in this embodiment. Only the first pad 21 a is formed on the upper surface side of the capacitor structure portion 2. The second pad 21 b is connected to a pad 41 that is connected to the signal line of the semiconductor chip 1. In the present embodiment, the first pad 21a, the second pad 21b, and the line portion 21c have a rectangular cross section as can be seen from the planar layout of FIG.

  The dielectric 22 is formed so as to surround the periphery of the line portion 21 c in the signal line 21. Since the thickness of the dielectric 22 is substantially constant, the cross section becomes a quadrangle corresponding to the line portion 21c as can be seen from the planar layout of FIG.

  The GND line 23 is configured to have an annular portion 23a surrounding the periphery of the line portion 21c in the signal line 21 with the dielectric 22 interposed therebetween, and a GND pad 23b exposed from the lower surface. The GND pad 23 b is connected to the pad 42 connected to the GND line of the semiconductor chip 1, so that the GND line 23 is electrically connected to the GND line of the semiconductor chip 1.

  The insulating film 24 is formed so as to cover the periphery of the annular portion 23 a and the upper surface side and the lower surface side of the capacitor structure portion 2. Contact holes 24a, 24b, and 24c are formed in the insulating film 24, and the line portion 21c and the first pad 21a or the second pad 21b in the signal line 21 are connected through the contact holes 24a and 24b. In addition, the annular portion 23a and the GND pad 23b in the GND line 23 are connected through the contact hole 24c.

  With this structure, the capacitor structure 2 is configured. In such a capacitor structure 2, the second pad 21b of the signal line 21 and the pad 41 of the semiconductor chip 1 are connected, and the GND pad 23b of the GND line 23 and the pad 42 of the semiconductor chip 1 are connected. Bonded directly or via solder.

  The capacitor structure 2 having such a structure is formed as follows. 4 to 5 are cross-sectional views showing the manufacturing process of the capacitor structure 2. With reference to these drawings, a method of manufacturing the capacitor structure 2 will be described.

  First, as shown in FIG. 4A, a silicon substrate 10 is prepared as a semiconductor substrate having a front surface and a back surface. Next, as shown in FIG. 4B, the recess 10 a is formed by performing photo-etching on the surface of the silicon substrate 10. The recess 10a at this time is set to be approximately equal to the outer dimension of the insulating film 24 provided in the capacitor structure 2, for example.

  Subsequently, as shown in FIG. 4C, an insulating film 11, a first metal film 12, a dielectric film 13, and a second metal film 14 are sequentially formed on the surface of the silicon substrate 10 including the inside of the recess 10a. . Then, the front surface side and the back surface side of the silicon substrate 10 are planarized in order by a planarization process such as CMP (Chemical Mechanical Polishing). Specifically, as shown in FIG. 5A, the surface of the silicon substrate 10 is flattened until the surface of the silicon substrate 10 is exposed, and further, on the back side of the silicon substrate 10, the bottom of the recess 10a is The two metal films 14 are flattened until exposed.

  Thus, the second metal film 14 forms the line portion 21c of the signal line 21, and the dielectric film 13 arranged so as to surround the periphery of the line portion 21c forms the dielectric body 22. The first metal film 12 arranged so as to surround the periphery of the dielectric 22 constitutes the annular portion 23a of the GND line 23, and the insulating film 11 arranged so as to surround the periphery of the annular portion 23a. Thus, a portion of the insulating film 24 surrounding the annular portion 23a is configured.

  Subsequently, as shown in FIG. 5B, after the insulating film 15 is formed on each of the front and back surfaces of the silicon substrate 10, the insulating film 15 is photo-etched, so that the contact holes 15 a to 15 c are formed in the insulating film 15. Form. The insulating film 15 constitutes portions of the insulating film 24 covering the upper surface side and the lower surface side of the capacitor structure portion 2, and the contact holes 24 a of the insulating film 24 are formed by the contact holes 15 a to 15 c formed in the insulating film 15. ~ 24c are configured.

  After that, as shown in FIG. 5C, a metal film 16 is formed on the surface of the insulating film 15 by deposition or plating, and patterned as necessary, so that the first through the contact holes 15a and 15b. The metal film 16 is left only in the contact portion with the second metal film 14 and the contact portion with the first metal film 12 through the contact hole 15c. Thereby, the 1st pad 21a, the 2nd pad 21b, and the GND pad 23b are comprised. In this way, the basic structure of the capacitor structure 2 is formed, and thereafter, the capacitor structure 2 of the present embodiment can be formed by removing the silicon substrate 10 by performing dicing cut or the like. It becomes. In this embodiment, the silicon substrate 10 is completely removed (see FIGS. 1 and 3), but the silicon substrate 10 may remain. In particular, if the silicon substrate 10 is non-doped, it can be handled as being similar to a part of the insulating film 24.

  As described above, in the present embodiment, the capacitor structure portion 2 constituting one capacitor is formed and mounted on the pads 41 and 42 of the semiconductor chip 1 as a single unit. That is, when the capacitor structure 2 is mounted at a plurality of locations on the semiconductor chip 1, a pair of capacitor structures 2 are provided at each location, that is, one capacitor structure 2 is provided. Then, by connecting the bonding wire 7 to the capacitor structure 2, the semiconductor chip 1 can be electrically connected to the outside through the capacitor structure 2. The connection position of the bonding wire 7 may be anywhere on the first pad 21a, but if it is made to coincide with the position corresponding to the line portion 21c, the thick line portion 21c made of a flexible metal material is formed. By being present, it is possible to suppress the occurrence of cracks during bonding.

  Even with the capacitor structure 2 having such a structure, high-frequency noise removal can be performed. In addition, it is not necessary to use a chip incorporating a plurality of capacitors, and the capacitor structure portion 2 can be individually arranged at a required place, so that a capacitor arrangement space is required on the circuit board. Absent.

  Therefore, it is possible to provide a semiconductor device having a structure capable of removing high-frequency noise without using a chip incorporating a plurality of capacitors and without requiring a capacitor arrangement space on the circuit board. .

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the configuration of the capacitor structure 2 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  FIG. 6 is a cross-sectional view of the capacitor structure portion 2 and the semiconductor chip 1 according to the present embodiment, and a diagram showing a planar layout at broken lines in the cross-sectional view.

  As shown in this figure, the capacitor structure portion 2 of the present embodiment eliminates the portion of the insulating film 24 that covers the lower surface of the capacitor structure portion 2, and the second pad 21 b of the signal line 21 and the GND line 23. The GND pad 23b is eliminated. The line portion 21c of the signal line 21 and the annular portion 23a of the GND line 23 are exposed as they are from the insulating film 24, and the shape of the pads 41 and 42 on the semiconductor chip 1 side is also the line portion 21c and The shape is the same as that of the annular portion 23a.

  Even with such a structure, the capacitor structure portion 2 can be individually mounted on the pads 41 and 42 of the semiconductor chip 1 as in the first embodiment. Therefore, the semiconductor device of this embodiment can obtain the same effect as that of the first embodiment. Since the pad 42 is formed so as to surround the pad 41, the signal line side is surrounded by the GND line side. For example, if a method such as forming the surface of the semiconductor chip 1 with a multilayer wiring structure is adopted. The signal lines and the GND lines in the semiconductor integrated circuit in the semiconductor chip 1 can be laid out regardless of the shapes of the pads 41 and 42.

(Third embodiment)
A third embodiment of the present invention will be described. In this embodiment, the configuration of the capacitor structure unit 2 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  FIG. 7 is a view showing a cross-sectional view of the capacitor structure portion 2 and the semiconductor chip 1 according to the present embodiment and a planar layout at a broken line in the cross-sectional view.

  As shown in this figure, the capacitor structure portion 2 of the present embodiment has a structure including a plurality of capacitor structures for each capacitor structure portion 2. Specifically, four rectangular capacitor structures are arranged in a lattice pattern. That is, four line portions 21c of the signal lines 21 are arranged in a lattice pattern, and an annular portion 23a of the GND line 23 is arranged so as to surround each line portion 21c. An insulating film 24 is also embedded between the annular portions 23a, and the annular portions 23a are connected to each other on the outermost side. In the planar layout, the four line portions 21c are connected to the first pad 21a and the second pad 21b near the center (inside) of the capacitor structure 2, and the four annular portions 23a are connected to the GND pad 23b on the outer edge side. It is connected.

  As described above, a single capacitor structure 2 may have a plurality of capacitor structures. As a result, the capacity can be increased, and more effective noise removal can be achieved.

(Modification of the third embodiment)
In the third embodiment, when one capacitor structure 2 includes a plurality of capacitor structures, the insulating film 24 is also disposed between the annular portions 23a of the GND lines 23 included in each capacitor structure. . However, the insulating film 24 may not be provided between the annular portions 23a. FIG. 8 is a cross-sectional view of the capacitor structure 2 and the semiconductor chip 1 in this case, and a diagram showing a planar layout at a broken line in the cross-sectional view. As shown in this figure, for example, in a structure in which four capacitor structures are provided in one capacitor structure portion 2, an insulating film 24 is not provided between the annular portions 23a, and the annular portions 23a are connected to each other. May be.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. This embodiment is different from the first embodiment in that the configuration on the semiconductor chip 1 side instead of the capacitor structure portion 2 is changed with respect to the first embodiment, and the other aspects are the same as the first embodiment. Only the part will be described.

  FIG. 9 is a cross-sectional view of the capacitor structure 2 and the semiconductor chip 1 according to the present embodiment. In the present embodiment, a recess having a shape corresponding to the capacitor structure 2 is provided on the semiconductor chip 1 side. Specifically, as shown in FIG. 9, a multilayer wiring 33 is formed in the interlayer insulating film 3, and a protective film 8 is formed on the surfaces of the multilayer wiring 33 and the interlayer insulating film 3, and this protective film 8 is formed with a concave portion 81 having a shape corresponding to that of the capacitor structure portion 2, thereby exposing the multilayer wiring 33 from the concave portion 81 to form pads 41 and 42.

  With such a structure, it is possible to easily align the semiconductor chip 1 and the capacitor structure portion 2 by fitting the capacitor structure portion 2 into the recess 81. Then, by electrically connecting the second pad 21b or the GND pad 23b of the capacitor structure 2 and the pads 41 and 42 exposed from the recess 81, the semiconductor formed in the capacitor structure 2 and the semiconductor chip 1 It is also possible to make an electrical connection with a signal line or a GND line in the integrated circuit.

(Modification of the fourth embodiment)
In the fourth embodiment, the recesses 81 are formed in the protective film 8 so that the pad 42 is exposed from the bottom surface of the recesses 81. On the other hand, the structure shown in FIG. FIG. 10 is a cross-sectional view of the capacitor structure portion 2 and the semiconductor chip 1 and a plan layout at a broken line in the cross-sectional view. As shown in this figure, a recess 34 is formed in the interlayer insulating film 3, a pad 42 is disposed on the side wall portion of the recess 34, and a pad portion 41 provided on the semiconductor chip 1 is disposed on the bottom of the recess 34. The capacitor structure 2 may be configured by a line portion 21 c of the signal line 21, a dielectric 22, and an annular portion 23 a of the GND line 23. In such a structure, by inserting the capacitor structure portion 2 into the recess 34, the line portion 21 c of the signal line 21 is connected to the pad 41 connected to the signal line of the semiconductor integrated circuit of the semiconductor chip 1, and the GND line 23 The annular portion 23a can be connected to the pad 42 connected to the GND line of the semiconductor integrated circuit.

(Other embodiments)
In the said embodiment, although an example of the structure of the capacitor structure part 2, etc. was shown, you may make it another structure. For example, the planar layout of the capacitor structure 2 may be changed to a shape other than a quadrangle. Further, as in the fourth embodiment (including a modification of the fourth embodiment), the concave portion 81 of the protective film 8 or the concave portion 34 of the interlayer insulating film 3 and the capacitor structure portion 2 are formed in the same shape, and the capacitor structure portion For example, when 2 is fitted in the recesses 34 and 81, the shape shown in FIG. That is, as shown in FIGS. 11A to 11D, the line portion 21c of the signal line 21 is formed into a cross shape, an octagon, a convex shape having a protrusion on one side of a quadrangle, a trapezoid, or the like, The annular portion 23a of the dielectric 22 surrounding the periphery of 21c and the GND line 23 can also have a shape corresponding to the shape of the line portion 21c. Even with such a shape, the capacitor structure 2 and the semiconductor chip 1 can be easily aligned.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Capacitor structure part 3 Interlayer insulating film 5 Lead frame 6 Bonding material 7 Bonding wire 8 Protective film 10 Silicon substrate 21 Signal line (capacitor signal line)
21a First pad 21b Second pad 21c Line part 22 Dielectric 23 GND line (capacitor ground line)
23a Annular part 23b GND pad 24 Insulating film 34 Recessed part 41 Pad (chip signal line pad)
42 pads (chip grounding wire pads)
51 External connection terminal 51 External terminal 81 Recess

Claims (6)

A semiconductor chip in which a circuit including a signal line and a ground line is formed, and a chip signal line pad (41) connected to the signal line and a chip ground line pad (42) connected to the ground line are formed on one side. (1) and
The chip signal line pad (41) and the chip ground line pad (42) are mounted alone and electrically connected to the chip signal line pad (41) and the chip ground line pad (42). A capacitor structure (2)
The capacitor structure (2)
A capacitor signal line (21) having a rod-shaped line portion (21c);
A dielectric (22) surrounding an outer periphery of the line portion (21c) provided in the capacitor signal line (21);
A capacitor ground line (23) having an annular portion (23a) surrounding the outer periphery of the dielectric (22);
Electrical connection with an external signal line of the semiconductor chip (1) is performed on one end side of the line portion (21c), and the semiconductor chip (1) is connected on the other end side of the line portion (21c). It is electrically connected to the chip signal line pad (41) provided in the semiconductor chip and electrically connected to the chip ground line pad (42) provided in the semiconductor chip (1). A semiconductor device.   The capacitor structure portion (2) has a plurality of capacitor structures in which the line portion (21c) is divided into a plurality of portions, and the outer periphery of each of the divided line portions (21c) is surrounded by the annular portion (23a). The semiconductor device according to claim 1, wherein the plurality of line portions (21 c) are all connected to the same chip signal line pad (41).   Only the first pad (21a) electrically connected to the line part (21c) is provided on the upper surface of the capacitor structure part (2) opposite to the semiconductor chip (1), The electrical connection between the capacitor structure (2) and a signal line outside the semiconductor chip (1) is performed via a first pad (21a). Semiconductor device.   A bonding wire (7) is connected to the first pad (21a), and an electrical connection between the capacitor structure (2) and a signal line outside the semiconductor chip (1) is made via the bonding wire (7). The semiconductor device according to claim 3, wherein connection is performed.   The semiconductor device according to claim 4, wherein the bonding wire (7) is connected to a position corresponding to the line portion (21c) in the first pad (21a). On one surface side of the semiconductor chip (1), recesses (34, 81) having the same shape as the capacitor structure (2) are provided,
The chip signal line pad (41) and the chip ground line pad (42) formed on the semiconductor chip (1) are exposed in the recesses (34, 81), and the capacitor structure (2) is By being disposed in the recesses (34, 81), the capacitor signal line (21) and the chip signal line pad (41) are electrically connected to each other while being positioned on the semiconductor chip (1). 6. The semiconductor device according to claim 1, wherein connection and electrical connection between the capacitor ground line (23) and the chip ground line pad (42) are performed.

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