JP5517726B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device.

  Liquid crystal display devices are widely used as display devices for information communication terminals such as computers and television receivers. The liquid crystal display device changes the orientation of the liquid crystal composition enclosed between two substrates by changing the electric field, and controls the degree of transmission of light passing through the two substrates and the liquid crystal composition to display an image. It is a device to display.

  In a display device that applies a voltage corresponding to a predetermined gradation value to each pixel of the screen, such as a liquid crystal display device, a pixel transistor for applying a voltage corresponding to the gradation value is arranged in each pixel. . In general, the gate electrodes of the pixel transistors for one line of the screen are connected to one signal line (referred to as “scanning line”), and the scanning line is sequentially turned on each line by a driving circuit called a shift register circuit. Is controlled so as to output an active voltage for conducting.

  Patent Document 1 discloses an example of a shift register circuit that stably controls active / inactive of each line among such shift registers.

JP 2007-95190 A

  Due to recent demands for miniaturization / low power consumption in portable information terminals, digital cameras, and the like, it is required to reduce the circuit scale while maintaining the performance of the shift register circuit as described above.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display device having a reduced circuit scale while maintaining the performance of a shift register circuit.

  The liquid crystal display device of the present invention is a liquid crystal display device comprising a thin film transistor substrate having a pixel transistor for controlling the orientation of the liquid crystal composition of each pixel arranged in the display region by forming an electric field, wherein the thin film transistor substrate is An alignment film arranged to cover the display region and determining the alignment of the liquid crystal composition when the electric field is not generated; and a transparent conductive film arranged to dam the alignment film on an outer edge of the alignment film And a shift register circuit having an output wiring for applying a voltage to the gate electrode of the pixel transistor, wherein the output wiring is one of the source and drain electrodes. The alignment transistor blocking conductive film forms a part of the shift register circuit. Is a liquid crystal display device according to claim.

  In the liquid crystal display device of the present invention, the alignment film blocking conductive film is electrically connected to the gate electrode of the output transistor, and on the surface of the thin film transistor substrate via the output wiring and the insulating film. A capacitance may be formed in cooperation with the output wiring by being formed so as to overlap the output wiring when projected in the vertical direction.

  In the liquid crystal display device of the present invention, the shift register circuit has an inactive potential when the gate electrode of the output transistor has an active potential for conducting the output transistor, and the gate electrode of the output transistor has an inactive potential. In this case, when the output control wiring having an active potential is further provided, and the alignment film blocking conductive film is projected in a vertical direction on the surface of the thin film transistor substrate through the output control wiring and the insulating film, The output control wiring and the capacitor may be formed by overlapping with the output control wiring.

  Further, in the liquid crystal display device of the present invention, the thin film transistor substrate has a pixel electrode connected to one of the source / drain electrodes of the pixel transistor and the pixel electrode for aligning the liquid crystal composition. A common electrode that forms an electric field, and the alignment film blocking electrically conductive film may be electrically connected to the common electrode.

  The liquid crystal display device according to the present invention is one of the wirings of the source and drain electrodes of the output transistor, and the output electrode wiring connected to the output wiring has a visual field perpendicular to the surface of the thin film transistor substrate. The gate electrode film of the output transistor and the input electrode wiring are overlapped with each other so that the overlapping area of the gate electrode film and the input electrode wiring overlaps the gate electrode film and the output electrode wiring. It may be smaller than the area.

  In the liquid crystal display device of the present invention, the gate electrode film of the output transistor covers the semiconductor film of the output transistor in a visual field perpendicular to the surface of the thin film transistor substrate.

  In the liquid crystal display device of the present invention, the gate electrode film of the transistor in the shift register circuit covers the semiconductor film of the transistor in a visual field perpendicular to the surface of the thin film transistor substrate. it can.

  In the liquid crystal display device of the present invention, the gate electrode films of all the transistors in the shift register circuit cover the respective semiconductor films of the transistors in a visual field perpendicular to the surface of the thin film transistor substrate. It can be said.

It is a figure which shows schematically the portable terminal device which concerns on one Embodiment of the liquid crystal display device of this invention. It is a figure which shows the partial cross section at the time of cut | disconnecting the display part of the portable terminal device of FIG. 1 by the II-II line | wire. It is a top view of the thin-film transistor substrate shown about the mode of arrangement | positioning of the alignment film blocking electrically conductive film. It is a figure which shows the circuit structure of a shift register circuit. 5 is a timing chart of the operation of the shift register circuit of FIG. It is a figure shown about the partial cross section of the vicinity of the alignment film damming conductive film of a thin-film transistor substrate. It is a figure shown about another partial cross section of the vicinity of the alignment film damming conductive film of a thin-film transistor substrate. It is a figure which shows the mode of arrangement | positioning at the time of projecting in the perpendicular direction on the surface of a thin-film transistor substrate about the gate electrode of a certain transistor, an amorphous silicon layer, a source electrode, and a drain electrode contained in a shift register circuit. It is a figure which shows the mode of arrangement | positioning at the time of projecting in the orthogonal | vertical direction on the surface of a thin-film transistor substrate about the gate electrode of the transistor near the display area included in a shift register circuit, an amorphous silicon layer, a source electrode, and a drain electrode. FIG. 5 is a diagram illustrating a state of arrangement when a gate electrode, an amorphous silicon layer, a source electrode, and a drain electrode of the transistor T5 in FIG. 4 are projected in a direction perpendicular to the surface of the thin film transistor substrate.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 schematically shows a portable terminal device 100 according to an embodiment of the liquid crystal display device of the present invention. As shown in FIG. 1, the mobile terminal device 100 includes an operation unit 104 that gives an instruction by key input so that the user can use the functions of the mobile terminal device 100, a response to the user's instruction, and wireless communication A display unit 106 for outputting the situation, a casing 102 for fixing the operation unit 104 and the display unit 106, a central processing unit (not shown) that performs arithmetic processing of each function, and the like are provided.

  FIG. 2 is a diagram illustrating a partial cross section when the display unit 106 of the mobile terminal device 100 of FIG. 1 is cut along a line II-II. As shown in FIG. 2, the display unit 106 includes a first frame 108 and a second frame 110 that support the liquid crystal display module 200 inside the housing 102, and the liquid crystal display module 200. In the display area, a backlight device 201 that is disposed on the opposite side of the display surface and irradiates light toward the display surface, and an optical sheet that changes light from the backlight device 201 into uniform light over the entire screen 203, a thin film transistor substrate 207 that controls the orientation of the liquid crystal composition by generating an electric field, a first polarizing plate 205 that is installed on the backlight device 201 side of the thin film transistor substrate 207 and passes only a certain polarization component, and a thin film transistor It is installed on the liquid crystal layer side of the substrate 207 and determines the orientation of the liquid crystal composition when no electric field is generated. Alignment film 209, liquid crystal layer 211 filled with a liquid crystal composition, and a color filter that changes light that has passed through liquid crystal layer 211 into light of red (R), green (G), and blue (B) colors A substrate 215, an alignment film 213 that is disposed on the liquid crystal layer side of the color filter substrate 215 and determines the alignment of the liquid crystal composition when no electric field is generated, and a second polarizing plate that allows only a certain polarization component to pass therethrough 217.

  The liquid crystal display module 200 further includes a seal 223 for sealing the liquid crystal composition between the thin film transistor substrate 207 and the color filter substrate 215 in a so-called frame region outside the display region shown in the figure. A black matrix 225 defining a frame region on the display surface side of the seal 223, a shift register circuit 219 formed on the thin film transistor substrate 207 on the backlight side of the seal 223, and the shift register circuit 219 from the backlight device 201 Is one of the thin film patterns on the thin film transistor substrate 207 and is used for blocking the alignment film 209 formed of ITO (Indium Tin Oxide), which is a transparent conductive film. And an alignment film wetting conductive film 221.

  FIG. 3 is a plan view of the thin film transistor substrate 207 showing how the alignment film blocking conductive film 221 is arranged. As shown in FIG. 3, the shift register circuit 219 is formed on both sides of the display region 230, and the alignment film blocking conductive film 221 is formed so as to surround the display region 230. The alignment film 209 is printed so as to cover the display region, but spreads due to the fluidity of the alignment film 209. The alignment film blocking conductive film 221 blocks the spread of the alignment film 209, the alignment film 209 erodes the frame region, and the seal 223 is formed on the alignment film blocking film 221 to cause a sealing defect. It is preventing.

Figure 4 is a diagram showing a circuit configuration of the shift register circuit 219 for outputting an output G _i, Fig. 5 is a timing chart of the operation of the shift register circuit 219 of FIG. 4. As shown in FIG. 4, the shift register circuit 219 is divided into a main drive circuit unit 219A and a low fixed circuit unit 219B.

First, the operation of the main drive circuit unit 219A will be described. Here, _{V i} is the clock signal, VST denotes a start signal, the drawing period, the potential of VGPL is fixed to Low, VGPH is fixed to High. All of these signals are input from the outside. Further, time t in FIG. 5 is written every 2H (two horizontal synchronization periods).

Main drive circuit section 219A, first, at the timing of time t2 in FIG. 5, the node _{N1 i-2} is a 2 horizontal drive period prior to the signal of the node N1 _i is High, the node _{N1 i-2} is the transistor T7A Since the transistor T7A is turned on, the node N2 is connected to VGPL and becomes Low. Further, since the output Gi _-2 is input to the diode-connected transistor T1, the node N1 connected thereto becomes High, causing a potential difference in the capacitor C1 and making the transistor T5 conductive. Since the node N1 is also a gate signal of the transistor T4, the node N2 is also connected to VGPL by the transistor T4 and becomes Low.

Next, at time t3, the clock signal V _i is High, the potential of one electrode of the capacitor C1 since the transistor T5 is conducting the next High, the transistor T5, which is the other electrode side by a so-called bootstrap The gate potential is pushed up more. Thereby, the high level of the output G _i is determined, and the voltage based on the applied gradation value is held in the pixel when the output G _i falls at time t4 described later.

When the clock signal V _i becomes low at time t4, the output G _i also becomes low. To determine this, the output G _{i + 2} that has become high at the same time t4 is input to the gates of the transistor TG and the transistor T9. Te, made conductive transistor TG and the transistor T9, and connect the output _{G i} and node N1 VGPL respectively, and both Low output _{G i} and node N1.

On the other hand, the clock signal V _{i + 2} that goes High at the same time t4 is input to the gate of the transistor T3, and the transistor T3 is turned on, whereby the node N2 is connected to VGPH and the node N2 is High. The high level of the node N2 is input to the low fixed circuit unit 219B described later.

The low fixed circuit portion 219B receives AC signals VGL_AC1, VGL_AC1B, VGL_AC2, and VGL_AC2B that are inverted at 2V (two vertical synchronization periods). In the timing chart of FIG. 5, VGL_AC1 is High and VGL_AC2 is VGL_AC2. A partial period in 2V (two vertical synchronization periods) which is Low is shown. In FIG. 5, the transistors TA1 and TA4 that receive a high gate signal are turned on, and the transistors TA3 and TA2 that receive a low gate signal are turned off. Here, the signal of the node N2 that is High at the time t4 passes through the transistor TA1 that is turned on, and is input to the gates of the transistors T2 and T6, thereby turning on these transistors. The transistor T2 and the transistor T6 includes a VGL_AC2 a Low signal, connects the node N1 and the output _{G i,} respectively.

FIG. 6 is a diagram showing a partial cross section of the thin film transistor substrate 207 near the alignment film blocking conductive film 221 formed thereon. As shown in FIG. 6, in this section, which appear wire output G _i and a node N1 in the circuit diagram of FIG. 4, it has a cross section in the vicinity of the capacitance C1. In this figure, the alignment film blocking conductive film 221 is divided into two portions, thereby forming three independent alignment film blocking conductive films 221a, 221b, and 221c. Here, the alignment film blocking conductive films 221a and 221c are electrically connected to the common electrode Vcom that forms an electric field in cooperation with the pixel electrode, and have the potential of the common electrode Vcom. On the other hand, the alignment film blocking conductive film 221b is electrically connected to the node N1, by being formed so as to overlap with the wiring of the output G _i when projected in a direction perpendicular to the plane of the thin film transistor substrate 207, electrical Capacity is formed. Thus, the alignment film blocking conductive film 221b only area fraction of the overlapping portion between the wiring of the output G _i, because it increases the electrical capacitance of the capacitor C1, the wiring of the output G _i and the wiring of the node N1 Even if the area of the overlapping portion is reduced, the capacity can be secured. Therefore, as a result, since the area occupied by the circuit of the capacitor C1 can be reduced, the area occupied by the shift register circuit 219 can be reduced, and as a result, the frame region can be reduced.

  FIG. 7 shows a partial cross section of a portion different from FIG. 6 in the vicinity of the alignment film blocking conductive film 221 of the thin film transistor substrate 207. As shown in FIG. 7, in this section, the wiring of the input VGPL and the node N2 in the circuit diagram of FIG. 4 appears, and the section is in the vicinity of the capacitor C3. Here, the alignment film blocking conductive film 221d is electrically connected to the common electrode Vcom and has the potential of the common electrode Vcom, similarly to the alignment film blocking conductive films 221a and 221c of FIG. The alignment film blocking conductive film 221d is formed so as to overlap with the node N2 when projected in a direction perpendicular to the display surface with an insulating film interposed above the wiring of the node N2. A large capacity is formed. As a result, the signal of the node N2, which is kept low for a long time during operation, is prevented from floating by being fixed by the electric capacity with the alignment film blocking conductive film 221d.

  FIG. 8 shows an arrangement of the gate electrode 10g, the amorphous silicon layer 10a, the source electrode 10s, and the drain electrode 10d included in the shift register circuit 219 when projected onto the surface of the thin film transistor substrate 207 in the vertical direction. FIG. 9 is a diagram showing the gate electrode 20g, the amorphous silicon layer 20a, the source electrode 20s, and the drain electrode 20d of other transistors included in the shift register circuit 219 in the same field of view as FIG. .

  Here, as shown in FIG. 2, at the position of the shift register circuit 219, light from the backlight device 201 is shielded by the light shielding tape 227 so that the shift register circuit 219 is not irradiated as much as possible. This is because when the amorphous silicon layer of the transistor is irradiated with light, the source and the drain of the transistor are conducted like the photoconductor. However, because the shift register circuit 219 is arranged near the display area in order to reduce the frame area, there is a possibility that light is irradiated to a circuit near the display area.

  Therefore, as shown in FIG. 9, in part of the shift register circuit 219, the gate electrode 20g is formed so as to completely cover the amorphous silicon layer 20a, thereby preventing the amorphous silicon layer 20a from being exposed to light. Transistors are used.

  On the other hand, when the configuration as shown in FIG. 9 is applied to all transistors, the area of the shift register circuit 219 itself increases, resulting in an increase in the frame area. Accordingly, the transistor having the configuration as shown in FIG. 9 is applied only to the transistor closer to the display region, and in the region far from the display region and difficult to receive light, the transistor shown in FIG. The scale of the register circuit 219 can be further reduced. Further, in the present embodiment, in FIG. 4, the transistors T3 and T10 whose threshold Vth is depleted when the energization time is increased, and the transistors TA2 and TA4 which are substantially unaffected even when the transistor is energized when the transistor is turned off. Uses a transistor having a small circuit area in FIG.

  FIG. 10 is a diagram showing the arrangement of the gate electrode 30g, the amorphous silicon layer 30a, the source electrode 30s, and the drain electrode 30d of the transistor T5 in FIG. 4 when projected onto the surface of the thin film transistor substrate 207 in the vertical direction. As shown in FIG. 10, as compared with FIG. 9, the transistor T5 has the source electrode 30s arranged outside the drain electrode 30d while maintaining the capacitance between the drain electrode 30d and the source electrode 30s. By reducing the overlapping area between 30d and gate electrode 30g, the capacitance between drain electrode 30d and gate electrode 30g is reduced.

A drain electrode 30d of the transistor T5, the transistor T5 is constant clock signal V _i even without conducting is input, repeated charging and discharging between the drain electrode 30d and the gate electrode 30g. Therefore, by reducing the capacitance between this drain electrode 30d and the gate electrode 30g can reduce this load, it is possible to reduce power consumption, it is possible to suppress the waveform blunting of the clock signal V _i . The source electrode 30s is connected to the output G _i, because the capacity is large, even if the increased capacity in the transistor T5 is affected is small.

  Therefore, according to the present embodiment, since the circuit scale can be reduced without impairing the performance of the shift register circuit 219, the display device can be reduced in size and power consumption.

  In the present embodiment, the alignment film blocking conductive films 221a, 221c, and 221d are connected to the common electrode Vcom. However, they may be connected to other wirings, and are independently floating. It may be.

  In the present embodiment, the liquid crystal display device is a portable terminal device, but other liquid crystal display devices such as a television and a digital camera may be used.

  In addition, the liquid crystal display device of the above-described embodiment does not specify a method, but any of liquid crystal displays of an IPS (In-Plane Switching) method, a VA (Vertically Aligned) method, and a TN (Twisted Nematic) method. Even an apparatus can be applied.

  DESCRIPTION OF SYMBOLS 100 Portable terminal device, 102 Housing | casing, 104 Operation part, 106 Display part, 108,110 frame, 200 Liquid crystal display module, 201 Backlight apparatus, 203 Optical sheet, 205 Polarizing plate, 207 Thin-film transistor substrate, 209 Alignment film, 211 Liquid crystal Layer, 213 alignment film, 215 color filter substrate, 217 polarizing plate, 219 shift register circuit, 219A main drive circuit section, 219B fixed circuit section, 221 alignment film wetting conductive film, 223 seal, 225 black matrix, 227 shading tape, 230 Display area, 10s, 20s, 30s Source electrode, 10d, 20d, 30d Drain electrode, 10a, 20a, 30a Amorphous silicon layer.

Claims (7)

A liquid crystal display device comprising a thin film transistor substrate having a pixel transistor for controlling the orientation of a liquid crystal composition of each pixel arranged in a display region by forming an electric field,
The thin film transistor substrate is
An alignment film that is disposed so as to cover the display region and determines the alignment of the liquid crystal composition when the electric field is not generated;
An alignment film damming conductive film which is a transparent conductive film arranged to dam the alignment film on the outer edge of the alignment film;
A shift register circuit having an output wiring for applying a voltage to the gate electrode of the pixel transistor,
The shift register circuit includes:
An output transistor in which the output wiring is connected to one of the source and drain electrodes ;
An output control wiring that becomes an inactive potential when the gate electrode of the output transistor is at an active potential for conducting the output transistor, and becomes an active potential when the gate electrode of the output transistor is at an inactive potential. ,
The alignment film blocking conductive film is formed so as to overlap with the output control wiring when projected on the surface of the thin film transistor substrate through the insulating film in the vertical direction, thereby reducing the capacity of the output control wiring and the capacitance. A liquid crystal display device characterized by being formed .   The alignment film blocking conductive film is electrically connected to the gate electrode of the output transistor, and the output when projected in a direction perpendicular to the surface of the thin film transistor substrate through the output wiring and the insulating film. The liquid crystal display device according to claim 1, wherein a capacitor is formed in cooperation with the output wiring by being formed so as to overlap with the wiring. The thin film transistor substrate is
A pixel electrode connected to one of the source and drain electrodes of the pixel transistor;
A common electrode that forms an electric field for aligning the liquid crystal composition together with the pixel electrode;
The alignment layer dammed conductive film, a liquid crystal display device according to claim 1 or 2, wherein the common electrode and are electrically connected, it is characterized. The output electrode wiring connected to the output wiring is one of the wirings of the source / drain electrodes of the output transistor, and the output electrode wiring connected to the output wiring of the wirings of the source / drain electrodes in a visual field perpendicular to the surface of the thin film transistor substrate. The area where the gate electrode film of the output transistor overlaps with the input electrode wiring is smaller than the area of overlap between the gate electrode film and the output electrode wiring, which is wired outside the other input electrode wiring. Item 4. The liquid crystal display device according to any one of Items 1 to 3 . In the field of view of the direction perpendicular to the plane of the thin film transistor substrate, a gate electrode film of said output transistor, according to any one of claims 1 to 4, characterized in that, covering the semiconductor film of said output transistor Liquid crystal display device. In the field of view of the direction perpendicular to the plane of the thin film transistor substrate, a gate electrode film of a transistor in said shift register circuit, any one of claims 1 to 5, characterized in that, covering the semiconductor film of the transistor The liquid crystal display device according to item. 2. The gate electrode film of each of all the transistors in the shift register circuit covers each semiconductor film of the transistor in a visual field perpendicular to the surface of the thin film transistor substrate. or liquid crystal display device according to any one of 6.

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