JP5514231B2 - Heterojunction field effect transistor - Google Patents

Description

  The present invention relates to a heterojunction field effect transistor made of a nitride semiconductor.

  Nitride semiconductors typified by GaN have characteristics such as high breakdown field strength, high thermal conductivity, and high saturation electron velocity, and are expected to be applied to high-frequency power devices, switching elements, and the like. The crystal growth of the nitride semiconductor is performed by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBF).

  FIG. 6 is a cross-sectional view showing a conventional heterojunction field effect transistor (see Non-Patent Document 1, for example). As shown in the figure, a nucleation layer 2 is formed on a substrate 1 made of sapphire, SiC, Si or the like. The nucleation layer 2 is formed according to the type of the substrate 1. When the substrate 1 is made of sapphire, the substrate 1 is once cleaned in a hydrogen atmosphere at 1000 ° C. or higher, and then the substrate temperature is lowered to 400 to 700 ° C. When GaN or AlN is formed and the substrate 1 is made of SiC or Si, the substrate 1 is cleaned in a hydrogen atmosphere at 1000 ° C. or higher, and then the substrate temperature is raised to 1000 ° C. or higher to form AlN or AlGaN. A buffer layer 3 made of undoped GaN is formed on the nucleation layer 2, and a barrier layer 4 made of undoped AlGaN is formed on the buffer layer 3. Further, the source electrode 5 and the drain electrode 6 are formed on the barrier layer 4 by ohmic junction, the gate electrode 7 is formed on the barrier layer 4 by Schottky junction, and the source electrode 5 and the drain electrode 6 are connected to the gate electrode 7. Further, they are arranged at a predetermined interval.

  In this heterojunction field effect transistor, a two-dimensional electron gas 8 is formed in the vicinity of the barrier layer 4 side interface in the buffer layer 3 due to a piezo effect and a spontaneous polarization effect generated between the barrier layer 4 and the buffer layer 3. The The heterojunction field effect transistor is operated by controlling the flow of the two-dimensional electron gas 8 between the region under the source electrode 5 and the region under the drain electrode 6 by the voltage applied to the gate electrode 7. . That is, in this heterojunction field effect transistor, a current flows between the source and the drain without applying a voltage to the gate electrode 7, and a so-called normally-on operation is realized. Further, since electrons as carriers move into the channel layer made of undoped (low impurity) GaN as the two-dimensional electron gas 8, scattering due to impurities is suppressed, and the electrons can move at high speed.

  On the other hand, when considering the ease of designing a circuit using a heterojunction field effect transistor and the reduction of standby power consumption, no current flows between the source and drain without applying a voltage to the gate. A so-called normally-off type heterojunction field effect transistor is considered advantageous.

  FIG. 7 is a sectional view showing a conventional normally-off type heterojunction field effect transistor. As shown in the figure, the barrier layer 4 in the portion where the gate electrode 7 is formed is partially etched by dry etching, and the gate electrode 7 is formed in the portion where the thickness of the barrier layer 4 is reduced. That is, in order to realize a normally-off type heterojunction field effect transistor, a recess gate technique using dry etching is employed.

  In this heterojunction field effect transistor, since the thickness of the barrier layer 4 immediately below the gate electrode 7 is reduced, the concentration of the two-dimensional electron gas 8 in the buffer layer 3 immediately below the gate electrode 7 is reduced. A normally-off type heterojunction field effect transistor is realized.

TakeshiKawasaki, KenNakataandSeijiYaegassi, ExtendAbstractsofthe2005InternationalConferenceonSolidStateDevicesandMaterials, Kobe, 2005, p.206-207. MasatakaHigashiwakiandToshikiMatsui, Jpn.J.App1.Phys., Vo1.43, p.L768-770 (2004). J.Kuzmik, Semicond.Sci.Techno1.Vo1.17, p.540-544 (2002)

  However, in the heterojunction field effect transistor shown in FIG. 7, in order to realize normally-off, the thickness of the barrier layer 4 immediately below the gate electrode 7 needs to be 10 nm or less. This causes a problem that the leakage current increases.

  For this reason, it is conceivable to increase the film thickness of the barrier layer 4 immediately below the gate electrode 7 by reducing the Al composition of the barrier layer 4, but the height of the Schottky barrier with respect to the gate electrode 7 is the Al composition. As a result, the leakage current of the gate cannot be suppressed.

  In addition to AlGaN, InAlN may be used as the material for the barrier layer of the heterojunction field effect transistor (for example, Non-Patent Document 2). InAlN is lattice-matched to GaN when the In composition is around 0.17. This means that the barrier layer can be formed with the Al composition of InAlN increased, and the two-dimensional electron gas concentration can be increased by increasing the spontaneous polarization. For this reason, when InAlN is used for the barrier layer, the resistance of the entire device can be reduced, so that the operating speed of the heterojunction field effect transistor can be improved.

  However, in order to realize a normally-off type heterojunction field effect transistor using InAlN in the vicinity where the In composition is lattice-matched to GaN, it is necessary to make the barrier layer thinner than when using AlGaN. Thus, further increase in gate leakage current has been a problem.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a normally-off type heterojunction field effect transistor with a small gate leakage current.

In order to achieve this object, in the present invention, a buffer layer made of GaN is formed on a substrate, a barrier layer is formed on the buffer layer, and a gate electrode, a source electrode, and a drain electrode are formed on the barrier layer. In the heterojunction field effect transistor, the barrier layer has a first layer on the buffer layer side and a second layer on the first layer, and the first layer has In _x Al _1-x N, the second layer is made of In _y Al _1-y N having a smaller In composition than the first layer, and the gate electrode is formed as a part of the second layer. It has a structure formed on the removed part, that is, the first layer .

In this case, the thickness of the first layer is 20 nm, the In composition x is 0.25 ≦ x ≦ 0.43, and the In composition y of the second layer is 0 <y ≦ 0.18.

In these cases, Si may be added as an impurity to the second layer .

  In these cases, the substrate may be made of sapphire, SiC, or Si.

  In the heterojunction field effect transistor according to the present invention, since the barrier layer includes the first layer and the second layer, the first layer having a sufficient thickness can be formed. The current can be reduced.

  When a contact layer made of InAlN is formed on the second layer and the In composition z of the contact layer is changed from the In composition y to 0.43 to 1 from the second layer side to the opposite side, Since the Schottky barrier height between the source and drain electrodes and the surface semiconductor is reduced, the contact resistance of the source and drain can be reduced.

  Further, when Si is added as an impurity to at least one of the second layer and the contact layer, the contact resistance of the source and drain can be reduced.

Theoretically, in a heterojunction field effect transistor using GaN as a buffer layer and InAlN as a barrier layer, the concentration of the two-dimensional electron gas generated at the heterointerface of InAlN / GaN varies depending on the In composition of InAlN. (Non-patent Document 3). FIG. 2 is a graph showing changes in sheet resistance of experimentally obtained heterojunction field effect transistor epiwafers using GaN as a buffer layer and InAlN as a barrier layer, depending on the In composition. As is clear from this graph, when the In composition of InAlN is lower than 0.17 (In composition lattice-matched to GaN), the sheet resistance is further reduced, and when the In composition of InAlN is higher than 0.17, Sheet resistance increases rapidly. The standard of sheet resistance for realizing a normally-off type heterojunction field effect transistor is 5000 ohm / sq. Or more. Further, the standard of sheet resistance that can sufficiently generate two-dimensional electron gas and reduce parasitic resistance is 1000 ohm / sq. Or less. Therefore, the first barrier layer made of In _x Al _1-x N (0.2 ≦ x ≦ 0.43) whose In composition is adjusted so that the sheet resistance is high (5000 ohm / sq. Or more). The layer is formed on a buffer layer made of GaN. That is, as apparent from FIG. 2, when the In composition of InAlN is 0.2 or more, the sheet resistance is 5000 ohm / sq. Or more, and almost no two-dimensional electron gas is generated at the InAlN / GaN interface. It is also known that when the In composition is 0.43, the two-dimensional electron gas at the InAlN / GaN interface is completely zero. That is, when InAlN having an In composition of 0.2 to 0.43 is used for the first layer of the barrier layer (the layer on the buffer layer side), a normally-off heterojunction field effect transistor is realized. It will be. In addition, since the sheet resistance in which the two-dimensional electron gas is generated is 1000 ohm / sq. Or less, the first layer is made of In _y Al _1-y N (0 ≦ y ≦ 0.18) having an In composition smaller than that of the first layer. Two layers are formed on the first layer. By the formation of the second layer, a two-dimensional electron gas is generated at the heterointerface between the first layer and the buffer layer 13. Furthermore, if the gate electrode is formed in a portion where a part of the second layer is removed, the two-dimensional electron gas is reduced immediately below the gate electrode, and there is sufficient two-dimensional electron gas in the other portions. A normally-off electronic state can be formed.

FIG. 1 is a sectional view showing a heterojunction field effect transistor according to the present invention. As shown in the figure, a nucleation layer 12 made of GaN having a thickness of 30 nm is formed on a substrate 11 made of sapphire, and a buffer layer 13 made of GaN having a thickness of 2 μm is formed on the nucleation layer 12. A first layer 14 made of InAlN having a film thickness of 20 nm and an In composition of 0.25 is formed on the buffer layer 13, and a film thickness of 20 nm and an In composition of 0.1 nm are formed on the first layer 14. A second layer 15 made of 15 InAlN is formed, and the first layer 14 and the second layer 15 constitute a barrier layer 16. Further, the source electrode 17 and the drain electrode 18 made of Al / Ti or Ti / Au are formed on the second layer 15 of the barrier layer 16 by ohmic junction, and the portion where the second layer 15 is removed, that is, the first layer. A gate electrode 19 made of Ni / Au is formed on the layer 14. That is, a recess gate structure is formed. The distance between the gate electrode 19 and the source electrode 17 and the drain electrode 18 is 11 μm, and the length and width of the gate electrode 19 are 1.5 μm and 100 μm, respectively.

  Next, a method for manufacturing the heterojunction field effect transistor shown in FIG. 1 will be described. First, the nucleation layer 12, the buffer layer 13, the first layer 14, and the second layer 15 are formed on the substrate 11 by MOCVD. At this time, trimethylgallium (TMG), trimethylaluminum (TMA), and trimethylindium (TMI) are used as the group III source gas, and ammonia (NH3) is used as the group V source gas. Further, the substrate temperature when forming the nucleation layer 12 is 500 ° C., the substrate temperature when forming the buffer layer 13 is 1050 ° C., and the substrate when forming the first layer 14 and the second layer 15. The temperature is 750 ° C. Next, the source electrode 17 and the drain electrode 18 are formed on the second layer 15 by photolithography and electrode deposition. Next, the source electrode 17 and the drain electrode 18 are ohmicized by heat treatment in nitrogen at 600 ° C. Next, a part of the second layer 15 is removed by photolithography and dry etching. In this case, reactive ion etching (ICP-RIE) using boron chloride (BCl 3) is used for dry etching, and the time is adjusted so that only the second layer 15 is removed. Next, a gate electrode 19 is formed on the portion where the second layer 15 is partially removed, that is, the first layer 14 by photolithography and metal vapor deposition to form a recessed gate structure.

  In the heterojunction field effect transistor shown in FIG. 1, a first layer 14 made of InAlN having an In composition of 0.25 is formed on the buffer layer 13, and an In composition of 0. 1 is formed on the first layer 14. Since the second layer 15 made of 15 InAlN is formed, and the gate electrode 19 is formed on the first layer 14, the recess gate structure is formed, so that the two-dimensional electron gas 20 is directly below the gate electrode 19. It is possible to form an ideal normally-off electronic state in which the two-dimensional electron gas 20 is present in other portions. Since the first layer 14 made of InAlN having an In composition of 0.25 is formed on the buffer layer 13 and the gate electrode 19 is formed on the first layer 14, the film of the first layer 14 Even if the thickness is increased, almost no two-dimensional electron gas 20 is generated immediately below the gate electrode 19. For this reason, the first layer 14 having a sufficient thickness can be formed in spite of the normally-off type, so that the gate leakage current can be reduced.

  FIG. 3 is a graph showing the relationship between the current Ids between the source and drain of the heterojunction field effect transistor shown in FIG. 1 and the voltage Vds between the source and drain, and the lines a to d have a gate voltage Vgs of 0 V, The case of 1V, 2V, 3V is shown. As is apparent from this graph, when the gate voltage Vgs is 0 V, the current Ids is zero, and it has been confirmed that a normally-off heterojunction field effect transistor having good pinch-off characteristics has been realized.

  FIG. 4 is a graph showing the relationship between the current Igs between the source and gate of the heterojunction field effect transistor shown in FIG. 1 and the voltage Vgs. As is apparent from this graph, the current Igs (leakage current) when a reverse voltage was applied was about 1 × 10 −12 A / mm. On the other hand, when a similar heterojunction field effect transistor is fabricated using AlGaN as a barrier layer, the current Igs is about 1 × 10 −6 A / mm, so that the gate leakage current is greatly reduced by the present invention. I was able to confirm.

In the above-described embodiment, the case where the first layer 14 made of InAlN having an In composition of 0.25 and the second layer 15 made of InAlN having an In composition of 0.15 has been described. Thus, the In composition of the first layer can be designed in the composition range of 0.2 to 0.43, and the In composition of the second layer can be designed in the composition range of 0 to 0.18. it can. Furthermore, in the above-described embodiment, the film thicknesses of the first layer 14 and the second layer 15 are each 20 nm, but the film thicknesses of the first layer 14 and the second layer 15 are 10 to 100 nm. Is possible. That is, the InAlN layer has a lattice mismatch relationship with GaN except for the case where the In composition is 0.17. However, since the mismatch is small, the first layer 14 and the second layer 15 have several tens of layers. It can be designed with a film thickness of 10 nm (10 to 100 nm).

FIG. 5 is a cross-sectional view showing a reference example of another heterojunction field effect transistor. As shown in the figure, a nucleation layer 22 made of GaN having a thickness of 30 nm is formed on a substrate 21 made of sapphire, and a buffer layer 23 made of GaN having a thickness of 2 μm is formed on the nucleation layer 22. A first layer 24 made of InAlN having a film thickness of 20 nm and an In composition of 0.25 is formed on the buffer layer 23, and a film thickness of 20 nm and an In composition of 0.1 nm are formed on the first layer 24. A second layer 25 made of 15 InAlN is formed, and the first layer 24 and the second layer 25 constitute a barrier layer 26. Further, a contact layer 27 made of InAlN having a thickness of 10 to 100 nm and an In composition z changing from 0.15 (In composition of the second layer 25) to 0.43 to 1 on the second layer 25. Is formed. Further, the source electrode 28 and the drain electrode 29 are formed on the contact layer 27 by ohmic junction, and the gate electrode 30 is formed on the portion where the contact layer 27 and the second layer 25 are removed, that is, on the first layer 24. Yes. That is, a recess gate structure is formed.

  In this heterojunction field effect transistor, since the contact layer 27 is formed on the second layer 25, the source electrode 28, the drain electrode 29, and the Schottky barrier height of the surface semiconductor are reduced. The drain contact resistance can be reduced. For example, in the heterojunction field effect transistor shown in FIG. 1, the contact resistance of the source and drain is about 10 Ω · mm, whereas in the heterojunction field effect transistor shown in FIG. The resistance was reduced to about 1 Ω · mm.

  Note that when Si is added to at least one of the second layer 25 and the contact layer 27 as an impurity, the contact resistance of the source and drain can be further reduced.

  Moreover, although the case where the board | substrates 11 and 21 which consist of sapphire were used was demonstrated in the said embodiment, the same effect can be anticipated also when the board | substrate which consists of Si and SiC used for the crystal growth of a nitride semiconductor is used. .

It is sectional drawing which shows the heterojunction field effect transistor which concerns on this invention. It is a graph which shows the change by In composition of the sheet resistance of a heterojunction field effect transistor epiwafer. 2 is a graph showing a relationship between a current Ids between a source and a drain and a voltage Vds between the source and the drain of the heterojunction field effect transistor shown in FIG. 1. 3 is a graph showing a relationship between a current Igs between a source and a gate of the heterojunction field effect transistor shown in FIG. 1 and a voltage Vgs. It is sectional drawing which shows the reference example of another heterojunction field effect transistor. It is sectional drawing which shows the conventional heterojunction field effect transistor. It is sectional drawing which shows the conventional normally-off type heterojunction field effect transistor.

DESCRIPTION OF SYMBOLS 11 ... Substrate 13 ... Buffer layer 14 ... 1st layer 15 ... 2nd layer 16 ... Barrier layer 17 ... Source electrode 18 ... Drain electrode 19 ... Gate electrode 21 ... Substrate 23 ... Buffer layer 24 ... 1st layer 25 ... Second layer 26 ... barrier layer 27 ... contact layer 28 ... source electrode 29 ... drain electrode 30 ... gate electrode

Claims (3)

A heterojunction field effect transistor in which a buffer layer made of GaN is formed on a substrate, a barrier layer is formed on the buffer layer, and a gate electrode, a source electrode, and a drain electrode are formed on the barrier layer,
The barrier layer has a first layer on the buffer layer side and a second layer on the first layer;
The first layer is made of In _x Al _1-x N;
The second layer is made of In _y Al _1-y N having a smaller In composition than the first layer,
Forming the gate electrode on a portion from which the second layer is partially removed, that is, on the first layer;
The film thickness of the first layer is 20 nm, the In composition x is 0.25 ≦ x ≦ 0.43, and the In composition y of the second layer is 0 <y ≦ 0.18. Heterojunction field effect transistor.   The heterojunction field effect transistor according to claim 1, wherein Si is added as an impurity to the second layer. 3. The heterojunction field effect transistor according to claim 1, wherein the substrate is made of sapphire, SiC or Si.