JP5505520B2 - Signal modulation circuit, signal modulation apparatus, and signal modulation method - Google Patents

Description

  The present invention relates to a signal modulation circuit, a signal modulation device, and a signal modulation method.

  Conventionally, a technique using a ΔΣ digital modulator that modulates an analog signal into a digital signal is known. As an example of such a technique, a technique of a servo driver or a power amplifier that supplies power according to an analog signal input from the outside is known.

  The ΔΣ digital modulator used in such a technique samples an analog signal input from the outside at a predetermined frequency, and modulates the sampled analog signal into a PDM (Pulse Density Modulation) signal. The ΔΣ digital modulator transmits the modulated PDM signal to a power element circuit that supplies power to a servo motor or the like. The power element circuit has an FET (Field Effect Transistor), operates the FET in accordance with the PDM signal transmitted from the ΔΣ digital modulator, and supplies power to the servo motor and the like.

  Hereinafter, the ΔΣ digital modulator will be specifically described with reference to the drawings. First, each circuit of the ΔΣ digital modulator will be described with reference to FIG. FIG. 15 is a block diagram for explaining the ΔΣ digital modulator.

  In the example shown in FIG. 15, the ΔΣ digital modulator samples the value of the input analog signal and calculates a difference value between the sampled analog signal value and a value fed back from a quantization circuit described later. Have In addition, the ΔΣ digital modulator has an integration circuit that calculates the sum of the difference value calculated by the difference circuit and the integration value held in its own device, and holds the calculated total as a new integration value. In addition, the ΔΣ digital modulator has a quantization circuit that outputs a pulse of the PDM signal when the integration value calculated by the integration circuit exceeds a predetermined threshold.

  Next, processing in which the ΔΣ digital modulator outputs a PDM signal will be described with reference to FIGS. FIG. 16 is a diagram (1) for explaining an example of the operation of the ΔΣ modulator. FIG. 17 is a diagram (2) for explaining an example of the operation of the ΔΣ modulator. FIG. 18 is a diagram (3) for explaining an example of the operation of the ΔΣ modulator. In the following description, when the sampling frequency is 100 MHz and a value of “1024” or more is output from the integrating circuit, the quantizing circuit outputs a pulse.

For example, in the example shown in FIG. 16, “256” is input to the difference circuit as the value of the analog signal. In such a case, the integration circuit outputs a value of “1024” at a cycle of 0.4 × 10 ⁻⁷ seconds. For this reason, the quantization circuit outputs a pulse having a wavelength of 0.1 × 10 ⁻⁷ seconds as a PDM signal at a cycle of 0.4 × 10 ⁻⁷ seconds.

In the example illustrated in FIG. 17, “512” is input to the difference circuit as the value of the analog signal. In such a case, the integration circuit outputs a value of “1024” with a period of once every 0.2 × 10 ⁻⁷ seconds. For this reason, the quantization circuit outputs a pulse having a wavelength of 0.1 × 10 ⁻⁷ seconds as a PDM signal at a cycle of 0.2 × 10 ⁻⁷ seconds.

In the example shown in FIG. 18, “768” is input to the difference circuit as the value of the analog signal. In such a case, the integration circuit outputs a value of “1024” or more three times in 0.4 × 10 ⁻⁷ seconds. For this reason, the quantization circuit outputs a pulse having a wavelength of 0.3 × 10 ⁻⁷ seconds as a PDM signal at a cycle of 0.4 × 10 ⁻⁷ seconds.

  Next, the frequency of the PDM signal output from the ΔΣ digital modulator will be described with reference to FIGS. FIG. 19 is a diagram (1) for explaining an example of the output of the ΔΣ digital modulator. FIG. 20 is a diagram (2) for explaining an example of the output of the ΔΣ digital modulator.

  For example, in the example shown in FIG. 19, the ΔΣ digital modulator has a sampling frequency of 100 kHz, an input resolution of 10 bits, and converts a 1 kHz analog signal indicated by a dotted line in FIG. 19 into a PDM signal. The PDM signal indicated by the solid line is output. For example, in the example shown in FIG. 9, the ΔΣ digital modulator converts the 10 Hz analog signal shown by the dotted line in FIG. 9 into a PDM signal with a sampling frequency of 1000 Hz and an input resolution of 10 bits. A PDM signal indicated by a solid line is output.

  That is, as shown in FIGS. 19 and 20, the ΔΣ digital modulator outputs a high-frequency PDM signal in a range where the change in the input analog signal is large, and in a range where the change in the input analog signal is small. A low frequency PDM signal is output.

  Here, when the value of the signal input to the ΔΣ digital modulator is Din, the input resolution is N, and the sampling frequency is Fs, the frequency Fcyc of the PDM signal output from the ΔΣ digital modulator is expressed by the following equation (1) ).

  Therefore, when the ΔΣ digital modulator modulates a numerical value from 1 to 1023 with a sampling frequency of 100 MHz and an input resolution of 10 bits, as shown in A in FIG. 21, the input value is “512”. Output the highest frequency PDM signal. FIG. 21 is a diagram for explaining an input value and an output frequency.

  On the other hand, in the power element circuit, since the FET that performs power switching has time characteristics, when a PDM signal having a frequency higher than a predetermined frequency is received, the FET cannot appropriately perform power switching. For this reason, a technique is known in which the frequency of the PDM signal output from the ΔΣ digital modulator is lowered by lowering the frequency at which the analog signal is sampled.

  For example, in the example shown by B in FIG. 22, the FET of the power element circuit cannot properly operate at a frequency higher than 25 MHz, and even if a PDM signal having a frequency higher than 25 MHz is received, Power switching cannot be performed. For this reason, the ΔΣ digital modulator reduces the maximum frequency of the PDM signal to ½ and operates the power element circuit as shown by C in FIG. 22 by setting the sampling frequency to ½. FIG. 22 is a diagram for explaining an operable region of the power element circuit.

JP 2007-068254 A

  However, the above-described technique for reducing the sampling frequency of the ΔΣ digital modulator reduces the frequency at which the pulse of the PDM signal is output regardless of the value of the input analog signal. For this reason, the ΔΣ digital modulator has a problem that the range in which the power element circuit can perform an appropriate operation is narrowed when the minimum frequency is set for power switching performed by the power element circuit. .

  For example, when controlling the servo system, the minimum frequency for switching power is determined in advance as shown by D in FIG. 23 in order to maintain the responsiveness to the input analog signal. However, as shown by the solid line in FIG. 23, the ΔΣ digital modulator reduces the frequency of the PDM signal by half regardless of the value of the input analog signal when the sampling frequency is lowered by half. Lower. For this reason, the ΔΣ digital modulator widens the range in which the PDM signal having a frequency lower than the lowest frequency is output. As a result, as shown by E in FIG. 23, the power element circuit can perform an appropriate operation. Will narrow. FIG. 23 is a diagram for explaining the problem of the ΔΣ digital modulator.

  In one aspect, the technology disclosed in the present application widens the range in which the power element circuit can perform an appropriate operation.

  In one aspect, the technology disclosed in the present application is a signal modulation circuit including an integration circuit that integrates and outputs a differential signal corresponding to an input value that is continuously input at a predetermined time interval. The signal modulation circuit also includes a quantization circuit that outputs a quantized signal obtained by quantizing the output of the integration circuit. In addition, the signal modulation circuit, when the quantized signal is output by the quantizing circuit, after a predetermined time interval has passed since the quantized signal was output, the difference corresponding to the quantized signal and the input value It has a difference circuit that calculates a signal and inputs the calculated difference signal to the integration circuit. The signal modulation circuit also includes a determination circuit that monitors the input value and determines whether or not the input value falls within a predetermined range. In addition, the integration circuit included in the signal modulation circuit integrates the differential signal after a predetermined time interval elapses when the determination circuit determines that the input value falls within the predetermined range. And output. Further, the difference circuit included in the signal modulation circuit calculates the difference signal according to the quantized signal and the input value when the determination circuit determines that the input value is included in the predetermined range. The difference signal is input to the integration circuit after a time interval obtained by extending a predetermined time interval elapses.

  In one aspect, the range in which the power element circuit can perform an appropriate operation is widened.

FIG. 1 is a diagram for explaining the signal modulation circuit according to the first embodiment. FIG. 2 is a diagram for explaining a range in which the frequency of the output PDM signal does not exceed a predetermined frequency. FIG. 3 is a diagram for explaining a circuit that executes the same processing as in the prior art. FIG. 4 is a diagram for explaining a range in which the frequency of the output PDM signal is lowered. FIG. 5 is a diagram for explaining a circuit that executes processing for reducing the frequency of the PDM signal. FIG. 6 is a diagram for comparing the integral value calculated by the conventional ΔΣ digital modulator with the integral value calculated by the signal modulation circuit according to the first embodiment. FIG. 7 is a diagram for explaining a PDM signal output from a conventional ΔΣ digital modulator. FIG. 8 is a diagram for explaining the PDM signal output from the signal modulation circuit according to the first embodiment. FIG. 9 is a diagram illustrating the frequency of the PDM signal output from the signal modulation circuit according to the first embodiment. FIG. 10 is a diagram for comparing the frequency of the PDM signal output from the signal modulation circuit according to the first embodiment and the frequency of the PDM signal output from the conventional ΔΣ digital modulator. FIG. 11 is a diagram for comparing the integrated value of the PDM signal output from the signal modulation circuit according to the first embodiment and the integrated value of the PDM signal output from the conventional ΔΣ digital modulator. FIG. 12 is a diagram for explaining an integral value of the output PDM signal. FIG. 13 is a diagram for explaining the ΔΣ digital modulation circuit having the signal modulation circuit according to the first embodiment. FIG. 14 is a flowchart for explaining the flow of processing executed by the signal modulation circuit. FIG. 15 is a block diagram for explaining the ΔΣ digital modulator. FIG. 16 is a diagram (1) for explaining an example of the operation of the ΔΣ modulator. FIG. 17 is a diagram (2) for explaining an example of the operation of the ΔΣ modulator. FIG. 18 is a diagram (3) for explaining an example of the operation of the ΔΣ modulator. FIG. 19 is a diagram (1) for explaining an example of the output of the ΔΣ digital modulator. FIG. 20 is a diagram (2) for explaining an example of the output of the ΔΣ digital modulator. FIG. 21 is a diagram for explaining an input value and an output frequency. FIG. 22 is a diagram for explaining an operable region of the power element circuit. FIG. 23 is a diagram for explaining the problem of the ΔΣ digital modulator.

  Hereinafter, a signal modulation circuit, a signal modulation device, and a signal modulation method according to the present application will be described with reference to the accompanying drawings.

  In the following first embodiment, a signal modulation circuit according to the first embodiment will be described.

  First, the signal modulation circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining the signal modulation circuit according to the first embodiment. In the example illustrated in FIG. 1, the signal modulation circuit 10 includes a difference circuit 11, an integration circuit 15, an XOR (exclusive or / exclusive disjunction) circuit 20, a counter 21, a quantization circuit 23, and a delay circuit 24. . The signal modulation circuit 10 is connected to a Din 22 that is a memory that holds an input value obtained by sampling an analog signal.

  The difference circuit 11 includes a first differentiator 12, a second differentiator 13, and a switch 14. The integration circuit 15 includes an adder 16, a first flip-flop 17, a second flip-flop 18, and a switch 19.

  In the following description, it is assumed that the signal modulation circuit 10 modulates an input analog signal into a PDM (Pulse Density Modulation) signal with an input resolution of 10 bits and a sampling frequency of 100 MHz.

  In addition, each of the units 11 to 21 included in the signal modulation circuit 10 operates according to the synchronization signal Fs having the same frequency as the sampling frequency. That is, it is assumed that the timings of the processes executed by the units 11 to 24 included in the signal modulation circuit 10 are synchronized. Further, it is assumed that an FET (Field Effect Transistor) of a power element circuit installed at the subsequent stage of the quantization circuit 23 can appropriately operate at a frequency of 25 MHz or less.

  When the quantization circuit 23 outputs the PDM signal, the difference circuit 11 converts the PDM signal and the value held in the Din 22 after a time corresponding to one synchronization signal has elapsed since the output of the PDM signal. The corresponding difference value is calculated. Then, the difference circuit 11 inputs the calculated difference value to the integration circuit 15. In addition, when the difference circuit 11 determines that the value held in the Din 22 by the XOR 20 is included in the predetermined range, the difference circuit 11 calculates the difference after a time interval longer than one synchronization signal has elapsed. The value is input to the integrating circuit 15.

  The integration circuit 15 calculates an integration value obtained by integrating the difference value input by the difference circuit 11 at a time interval corresponding to one synchronization signal, and outputs the calculated integration value. Further, when the integration circuit 15 determines that the value held in the Din 22 by the XOR 20 is included within a predetermined range, the integration circuit 15 integrates and outputs the difference value at a time interval longer than one synchronization signal. .

  The XOR 20 monitors the value held in the Din 22 and determines whether or not the value held in the Din 22 is included within a predetermined range. The counter 21 outputs a counter signal at a time interval longer than the synchronization signal. The quantization circuit 23 outputs a PDM signal obtained by quantizing the output of the integration circuit 15. The delay circuit 24 delays the feedback signal output from the quantization circuit 23 by one synchronization signal and inputs the delayed signal to the difference circuit 11.

  Hereinafter, each part which the difference circuit 11 and the integration circuit 15 which the signal modulation circuit 10 has will be described. First, each part of the difference circuit 11 will be described. When the PDM signal is output by the quantization circuit 23, the first differentiator 12 responds to the PDM signal and the value held in the Din 22 after a predetermined time interval has elapsed since the output of the PDM signal. The difference signal obtained is calculated. Then, the first differentiator 12 outputs the calculated difference signal after a predetermined time interval has elapsed. Specifically, the first differentiator 12 calculates a value obtained by subtracting a value indicated by a feedback signal acquired from the delay circuit 24 described later from the value held in the Din 22. Then, the first differentiator 12 transmits the calculated value to the switch 14.

  Here, the delay circuit 24 delays the feedback signal by one synchronization signal. That is, the first differentiator 12 calculates the difference signal according to the feedback signal corresponding to the PDM signal and the value held in the Din 22 after the time corresponding to one synchronization signal has elapsed since the output of the PDM signal. To do.

  When the PDM signal is output by the quantization circuit 23, the second differentiator 13 responds to the PDM signal and the value held in the Din 22 after a predetermined time interval has elapsed since the output of the PDM signal. The difference signal obtained is calculated. The second subtractor 13 outputs the calculated difference signal after a time interval longer than one synchronization signal has elapsed. That is, the second differentiator 13 operates at a frequency slower than that of the first differentiator 12, and a value held in Din 22 that is a value obtained by sampling an analog signal and feedback received from a delay circuit 24 described later. The difference from the value indicated by the signal is calculated.

  Specifically, when the second differentiator 13 does not receive the counter signal from the counter 21 described later, the value indicated by the feedback signal acquired from the delay circuit 20 described later from the value held in the Din 22. The value obtained by subtracting is calculated. Then, the second differentiator 13 transmits the calculated value to the switch 14. The second subtractor 13 holds the calculated value in its own device. Further, when the second subtractor 13 receives a counter signal from the counter 21 described later, the second subtractor 13 calculates the value immediately before and transmits the held value to the switch 14. That is, the second subtractor 13 is a subtractor that outputs the calculated difference signal after receiving the next output signal when the counter signal output by the counter 21 is received.

  For example, when the counter 21 receives the synchronization signal twice, when the counter 21 transmits the counter signal to the second difference 13 and the second flip-flop 18, the second difference 13 is half of the first difference 12. It is a differentiator that operates at a frequency.

  When the switch 14 determines that the value held in Din 22 by the XOR 20 described later is not included in the predetermined range, the switch 14 adds the difference signal output by the first differentiator 12 to the adder 16 of the integration circuit 15. To enter. Further, when the switch 14 determines that the value held in the Din 22 by the XOR 20 is included within a predetermined range, the switch 14 converts the difference signal output by the second differentiator 13 into the adder 16 of the integrating circuit 15. To enter.

  Specifically, the switch 14 receives the value calculated by the first subtractor 12 and the value calculated by the second subtractor 13. The switch 14 receives a signal for selecting the first subtractor 12 or a signal for selecting the second subtractor 13 from the XOR circuit 20 described later. When the switch 14 receives a signal for selecting the first subtractor 12 from the XOR circuit 20, the switch 14 transmits the value received from the first subtractor 12 to the adder 16 of the integration circuit 15 described later. Further, when the switch 14 receives a signal for selecting the second differentiator 13 from the XOR circuit 20, the switch 14 transmits the value received from the second differentiator 13 to the adder 16 of the integrating circuit 15 described later.

  That is, the difference circuit 11 is a difference circuit that operates at the same frequency as the difference circuit included in the conventional ΔΣ digital modulator when the value calculated by the first differencer 12 is output. Further, the difference circuit 11 is a difference circuit that operates at a half frequency of the difference circuit included in the conventional ΔΣ digital modulator when the value calculated by the second difference unit 13 is output.

  Next, each part of the integration circuit 15 will be described. The adder 16 calculates a value obtained by adding a value received from the switch 14 and a value received from the switch 19 described later at a predetermined time interval. Then, the adder 16 transmits the calculated value to the first flip-flop 17, the second flip-flop 18, and the quantization circuit 23. That is, the adder 16 calculates the integral value of the difference calculated by the difference circuit 11 and transmits the calculated integral value to the first flip-flop 17, the second flip-flop 18, and the quantization circuit 23.

  When a new integration value is calculated by the adder 16, the first flip-flop 17 temporarily holds the calculated integration value, and after the predetermined time interval has elapsed, Output. Specifically, the first flip-flop 17 receives the value calculated by the adder 16 when receiving the synchronization signal. When receiving the synchronization signal again, the first flip-flop 17 transmits the received value to the switch 19 and acquires the value newly calculated by the adder 16. In other words, the first flip-flop 17 is a delay circuit that receives a signal indicating the value calculated by the adder 16, delays the received signal by one synchronization signal, and then feeds back the signal to the adder 16.

  When a new integrated value is calculated by the adder 16, the second flip-flop 18 temporarily holds the calculated integrated value, a predetermined time interval has elapsed, and the predetermined time interval has been extended. After the time interval elapses, the held integral value is output. Specifically, the second flip-flop 18 acquires the value calculated by the adder 16. When the second flip-flop 18 does not receive the counter signal from the counter 21, the second flip-flop 18 transmits the value acquired from the adder 16 to the switch 19 and holds the transmitted value.

  Further, when receiving the counter signal, the second flip-flop 18 transmits the value held immediately before to the switch 19 and acquires the value newly calculated by the adder 16. That is, when the second flip-flop 18 receives the counter signal from the counter 21, the second flip-flop 18 outputs the held value and holds the value acquired from the adder 16 until the next output signal is received. Holding circuit.

  The switch 19 transmits the integrated value output from the first flip-flop 17 to the adder 16 when the XOR 20 determines that the input value is not included in the predetermined range. In addition, when the XOR 20 determines that the input value is included in the predetermined range, the switch 19 transmits the integrated value output by the second flip-flop 18 to the adder 16. Specifically, the value transmitted from the first flip-flop 17 is received. The switch 19 receives the value transmitted from the second flip-flop 18. The switch 19 receives a signal for selecting the first flip-flop 17 or a signal for selecting the second flip-flop 18 from the XOR circuit 20 described later.

  When the switch 19 receives a signal for selecting the first flip-flop 17 from the XOR circuit 20, the switch 19 transmits the value received from the first flip-flop 17 to the adder 16. When the switch 19 receives a signal for selecting the second flip-flop 18 from the XOR circuit 20, the switch 19 transmits the value received from the second flip-flop 18 to the adder 16.

  That is, the integration circuit 15 is an integration circuit that operates at the same frequency as the integration circuit of the conventional ΔΣ digital modulator when the integration value is calculated using the first flip-flop 17. Further, the integration circuit 15 is an integration circuit that operates at a half frequency of the integration circuit included in the conventional ΔΣ digital modulator when the integration value is calculated using the second flip-flop 18.

  Next, the XOR 20, the counter 21, the quantization circuit 23, and the delay circuit 24 included in the signal modulation circuit 10 will be described in detail. The XOR circuit 20 monitors the value held in the Din 22 and determines whether or not the value held in the Din 22 is included in a predetermined range. Specifically, the XOR 20 compares the two most significant bits among the values held in the Din 22, and determines whether or not the two bits are the same value. If the XOR circuit 20 determines that the two most significant bits are both the same value, the XOR circuit 20 transmits a signal for selecting the first differentiator 12 to the switch 14. If the XOR circuit 20 determines that the two most significant bits have the same value, the XOR circuit 20 transmits a signal for selecting the first flip-flop 17 to the switch 19.

  If the XOR circuit 20 determines that the values of the two most significant bits are different, the XOR circuit 20 transmits a signal for selecting the second differentiator 13 to the switch 14. Further, when the XOR circuit 20 determines that the values of the two most significant bits are different, the XOR circuit 20 transmits a signal for selecting the second flip-flop 18 to the switch 19.

  Here, among the values held in Din22, when the most significant two bits are the same, the value obtained by sampling the analog signal with “10” bits is within the range of “1-255” or “768-1023”. Indicates that Also, the case where the most significant two bits of the values held in Din22 are different indicates that the value obtained by sampling the analog signal with “10” bits is within the range of “256 to 767”.

  In other words, the signal modulation circuit 10 uses the first differentiator 12 and the first flip-flop 17 when the sampled value of the analog signal is included in the range of “1-255” or “768-1023”. Perform analog signal modulation. Further, when the value obtained by sampling the analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 modulates the analog signal using the second difference unit 13 and the second flip-flop 18. Run.

  Here, in the case where the conventional ΔΣ digital modulation circuit has an input resolution of 10 bits and a sampling frequency of 100 MHz, the value obtained by sampling the analog signal is 25 MHz or more in the range of “256 to 767” from the equation (1). The PDM signal is transmitted.

  On the other hand, when the value obtained by sampling the analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 uses the second differentiator 13 that operates at half the frequency of the first differencer 12, The difference circuit 11 is operated. Further, when the value obtained by sampling the analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 uses the second flip-flop 18 that operates at half the frequency of the first flip-flop 17. The integrating circuit 15 is operated.

  That is, when the value obtained by sampling the analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 outputs the PDM signal at a frequency half that of the PDM signal output by the conventional ΔΣ digital modulator. . Further, when the value obtained by sampling the analog signal is in the range of “1-255” or “768-1023”, the signal modulation circuit 10 has the same frequency as the PDM signal output from the conventional ΔΣ digital modulator. PDM signal is output.

  For this reason, when the frequency of the PDM signal to be output exceeds the frequency range in which the FET can be appropriately operated, the signal modulation circuit 10 outputs the PDM signal while suppressing the frequency to one half. Further, the signal modulation circuit 10 outputs the PDM signal at the same frequency as the conventional ΔΣ digital modulator when the frequency of the PDM signal to be output is included in the frequency range in which the FET can be appropriately operated.

  As a result, the signal modulation circuit 10 maintains the responsiveness to the input analog signal even when controlling the servo system, and sets the frequency of the output PDM to a frequency at which the FET can appropriately operate. Can fit. For this reason, the signal modulation circuit 10 can widen the range in which the power element circuit can perform an appropriate operation.

  The counter 21 outputs a signal to the second differentiator 13 and the second flip-flop 18 at a time interval longer than the synchronization signal. That is, the counter 21 outputs a counter signal to the second differentiator 13 and the second flip-flop 18 at a frequency lower than the sampling frequency. Specifically, the counter 21 acquires an arbitrary initial value “m” preset by the user. Further, the counter 21 sets the counter value to the initial value “m”, and counts down the counter value every time the synchronization signal Fs is received.

  When the counter value reaches “0”, the counter 21 transmits a counter signal to the second differentiator 13 and the second flip-flop 18 and resets the counter value.

  For example, when m = “1”, the counter 21 transmits a counter signal to the second differentiator 13 and the second flip-flop 18 every time the synchronization signal Fs is received twice. That is, the second differentiator 13 and the second flip-flop 18 operate at half the frequency of the first differentiator 12 and the first flip-flop 17 when m = “1”.

  When the integrated value calculated by the integrating circuit 15 is larger than a predetermined value, the quantizing circuit 23 outputs a pulse having a predetermined length as a PDM signal. The quantization circuit 23 transmits a feedback signal to the delay circuit 24 when the integration value calculated by the integration circuit 15 is larger than a predetermined value.

Specifically, the quantization circuit 23 acquires the integration value calculated by the integration circuit 15. Then, when the acquired integrated value is “1024” or more, the quantization circuit 23 outputs a pulse having a wavelength of 0.1 × 10 ⁻⁷ seconds and indicating the value “1”. Further, when the acquired integral value is “1024” or more, the quantization circuit 23 transmits a feedback signal indicating “1024” to the delay circuit 24. Further, when the acquired integral value is less than “1024”, the quantization circuit 23 does not transmit a feedback signal to the delay circuit 24.

  The delay circuit 24 is a delay circuit that, when receiving a feedback signal from the quantization circuit 23, delays the received feedback signal by one synchronization signal and transmits it to the difference circuit 11.

[Processing of signal modulator]
Next, a specific example of processing executed by the signal modulation circuit 10 will be described with reference to FIGS. First, the processing executed by the signal modulation circuit 10 when the value of the analog signal is included in the ranges of “1 to 255” and “768 to 1023” will be described with reference to FIGS. FIG. 2 is a diagram for explaining a range in which the frequency of the PDM signal to be output does not exceed a predetermined frequency. FIG. 3 is a diagram for explaining a circuit that executes the same processing as in the prior art.

  As shown in FIG. 2, in the signal modulation circuit 10, when the value of the input analog signal is included in “1-255” and “768-1023”, the frequency of the output PDM signal is 25 MHz or less. Therefore, the same processing as the conventional ΔΣ digital modulator is performed.

  That is, when the value of the input analog signal is included in the range of “1 to 255” and “768 to 1023”, the signal modulation circuit 10 includes the first subtractor as shown by the solid line in FIG. 12. The difference between the input analog signals is calculated using a circuit including the switch 14. Further, when the value of the analog signal is included in the range of “1-255” and “768-1023”, the signal modulation circuit 10 adds the adder 16 and the first flip-flop as indicated by the solid line in FIG. The integrated value of the calculated difference is calculated using a circuit including the switch 17 and the switch 19.

  Then, the signal modulation circuit 10 outputs a pulse as a PDM signal from the quantization circuit 23 based on the calculated integration value. That is, the signal modulation circuit 10 outputs a PDM signal having the same frequency as the PDM signal output from the conventional ΔΣ digital modulator.

  Next, processing executed by the signal modulation circuit 10 when the value of the analog signal is included in the range of “256 to 767” will be described with reference to FIGS. FIG. 4 is a diagram for explaining a range in which the frequency of the output PDM signal is lowered. FIG. 5 is a diagram for explaining a circuit that executes processing for reducing the frequency of the PDM signal.

  As shown in FIG. 4, when the value of the input analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 executes processing with a circuit equivalent to a conventional ΔΣ digital modulator. In this case, the frequency of the output PDM signal exceeds 25 MHz. For this reason, the signal modulation circuit 10 modulates an analog signal into a PDM signal using a circuit that operates at a half frequency compared to the circuit indicated by the dotted line in FIG.

  Specifically, when the value of the input analog signal is included in the range of “256 to 767”, the signal modulation circuit 10, as shown by the solid line in FIG. 14 is used to calculate the difference between the input analog signals. Further, when the value of the input analog signal is included in the range of “256 to 767”, the signal modulation circuit 10 includes an adder 16, a second flip-flop 18, as shown by a dotted line in FIG. An integrated value of the calculated difference is calculated using a circuit including the switch 19.

  That is, the signal modulation circuit 10 includes a first modulation circuit that modulates an analog signal into a PDM signal and outputs the modulated PDM signal, as indicated by a solid line in FIG. Further, as shown by a solid line in FIG. 5, the signal modulation circuit 10 modulates a PDM signal having a frequency lower than that of the PDM signal output by the first modulation circuit, and outputs a modulated PDM signal. A modulation circuit is included.

  Then, the signal modulation circuit 10 determines whether or not the value held in Din 22 is within the range of “256 to 767”. Thereafter, when the signal modulation circuit 10 determines that the value held in Din 22 is within the range of “256 to 767”, the signal modulation circuit 10 modulates the analog signal into the PDM signal using the second modulation circuit. If the signal modulation circuit 10 determines that the value held in Din 22 is outside the range of “256 to 767”, the signal modulation circuit 10 modulates the analog signal into a PDM signal using the first modulation circuit.

  Next, the integration value calculated by the conventional ΔΣ digital modulator and the signal modulation circuit 10 when the value of the input analog signal is included in the range of “256 to 767” will be described using FIG. 6. FIG. 6 is a diagram for comparing the integral value calculated by the conventional ΔΣ digital modulator with the integral value calculated by the signal modulation circuit according to the first embodiment.

  In the example shown in FIG. 6, it is assumed that “256” is input to the conventional ΔΣ digital modulator and the signal modulation circuit 10 as an input value. Further, the quantization circuit included in the conventional ΔΣ digital modulator and the quantization circuit 23 included in the signal modulation circuit 10 output a pulse of the PDM signal when an integral value of “1024” or more is calculated. Shall.

As shown in FIG. 6, the integration circuit included in the conventional ΔΣ digital modulator has an integration value every 0.1 × 10 ⁻⁷ seconds when the input value “256” is input to the ΔΣ digital modulation signal. “256”, “512”, “768”, and “1024” are repeatedly calculated. On the other hand, when the clock signal is 1, the second differentiator 13 and the second flip-flop 18 output the same value as the value output immediately before, as indicated by F in FIG.

Therefore, the integration circuit 15 of the signal modulation circuit 10 outputs “1024”, which is the same as the value output immediately before, as indicated by G in FIG. Further, as shown by H in FIG. 6, the second differentiator 13 and the second flip-flop 18 output a new value when the clock signal is not received. Therefore, the integration circuit 15 of the signal modulation circuit 10 outputs a new integration value “256” as indicated by I in FIG. That is, the integration circuit 15 of the signal modulation circuit 10 repeatedly calculates integration values “256”, “512”, “768”, and “1024” every 0.2 × 10 ⁻⁷ seconds.

Next, the PDM signal output from the conventional ΔΣ digital modulator will be described with reference to FIG. FIG. 7 is a diagram for explaining a PDM signal output from a conventional ΔΣ digital modulator. As shown in FIG. 7, the conventional ΔΣ digital modulator repeatedly calculates integral values “256”, “512”, “768”, and “1024” every 0.1 × 10 ⁻⁷ seconds. Therefore, the conventional ΔΣ digital modulator outputs a pulse having a wavelength of 0.1 × 10 ⁻⁷ seconds with a period of 0.4 × 10 ⁻⁷ seconds.

Next, the PDM signal output from the signal modulation circuit 10 will be described with reference to FIG. FIG. 8 is a diagram for explaining the PDM signal output from the signal modulation circuit according to the first embodiment. As shown in FIG. 8, the signal modulation circuit 10 repeatedly calculates integral values “256”, “512”, “768”, and “1024” every 0.2 × 10 ⁻⁷ seconds. For this reason, the signal modulation circuit 10 outputs a pulse having a wavelength of 0.2 × 10 ⁻⁷ seconds at a cycle of 0.8 × 10 ⁻⁷ seconds.

  That is, the signal modulation circuit 10 outputs a PDM signal having a frequency lower than that of the PDM signal output from the conventional ΔΣ digital modulator and having the same duty ratio as the PDM signal output from the conventional ΔΣ digital modulator. To do. As a result, as indicated by the hatched portion in FIG. 7 and the hatched portion in FIG. 8, the value obtained by integrating the PDM signal output from the signal modulation circuit 10 is integrated with the PDM signal output from the conventional ΔΣ digital modulator. The same value can be maintained. As a result, the signal modulation circuit 10 can keep the amount of power supplied by the power element circuit at the same amount as before even when the PDM signal is output at half the conventional frequency.

  FIG. 9 is a diagram illustrating the frequency of the PDM signal output from the signal modulation circuit according to the first embodiment. As indicated by J in FIG. 9, the signal modulation circuit 10 suppresses the frequency of the output PDM signal to ½ when the value of the input analog signal is included in the range of “256 to 767”. . For this reason, the signal modulation circuit 10 can appropriately operate the power element circuit as a result of suppressing the frequency of the PDM signal to be equal to or lower than the frequency at which the FET operates appropriately.

  Further, when the value of the input analog signal is included in the range of “1-255” and “768-1023”, the signal modulation circuit 10 outputs the PDM signal having the same frequency as that of the conventional ΔΣ digital modulator. Output. That is, since the signal modulation circuit 10 outputs a PDM signal having the same frequency as that of a conventional ΔΣ digital modulator within a range where it is not necessary to lower the frequency of the PDM signal, the signal modulation circuit 10 maintains responsiveness to the input analog signal. Can do. As a result, the signal modulation circuit 10 can widen the range in which the frequency of the PDM signal falls within an appropriate range, as indicated by K in FIG.

  FIG. 10 is a diagram for comparing the frequency of the PDM signal output from the signal modulation circuit according to the first embodiment and the frequency of the PDM signal output from the conventional ΔΣ digital modulator. As shown by the dotted line in FIG. 10, the conventional ΔΣ digital modulator reduces the frequency of the PDM signal uniformly to one half when the sampling frequency is halved. As indicated by L, the range in which the power element circuit can perform an appropriate operation is narrowed.

  On the other hand, as indicated by the solid line in FIG. 10, the signal modulation circuit 10 can suppress the frequency of the PDM signal to half only when the value of the analog signal is included in the range of “256 to 767”. . As a result, the signal modulation circuit 10 can widen the range in which the power element circuit can perform an appropriate operation, as indicated by M in FIG.

  Next, the integrated value of the PDM signal output from the signal modulation circuit 10 will be described in detail with reference to FIG. FIG. 11 is a diagram for comparing the integrated value of the PDM signal output from the signal modulation circuit according to the first embodiment and the integrated value of the PDM signal output from the conventional ΔΣ digital modulator.

As shown in FIG. 11, when the input value is “256”, the conventional ΔΣ digital modulator has a wavelength of 0.1 × 10 ⁻⁷ seconds with a period of 0.4 × 10 ⁻⁷ seconds. Output a pulse. On the other hand, when the input value is “256”, the signal modulation circuit 10 outputs a pulse having a wavelength of 0.2 × 10 ⁻⁷ seconds with a period of 0.8 × 10 ⁻⁷ seconds. For this reason, when the time scale at which the input value changes is sufficiently larger than 0.8 × 10 ⁻⁷ seconds, the value obtained by integrating the pulse of the PDM signal output from the conventional ΔΣ digital modulator and the signal modulation circuit 10 Is the same value as the integrated value of the pulse of the PDM signal output from the.

As shown in FIG. 11, the conventional ΔΣ digital modulator has a wavelength of 0.1 × 10 ⁻⁷ seconds with a period of 0.2 × 10 ⁻⁷ seconds when the input value is “512”. Is output. On the other hand, when the input value is “512”, the signal modulation circuit 10 outputs a pulse having a wavelength of 0.4 × 10 ⁻⁷ seconds with a period of 0.4 × 10 ⁻⁷ seconds. For this reason, when the time scale at which the input value changes is sufficiently larger than 0.2 × 10 ⁻⁷ seconds, the value obtained by integrating the pulse of the PDM signal output from the conventional ΔΣ digital modulator and the signal modulation circuit 10 Is the same value as the integrated value of the pulse of the PDM signal output from the.

Further, as shown in FIG. 11, the conventional ΔΣ digital modulator has a wavelength of 0.3 × 10 ⁻⁷ seconds with a period of 0.4 × 10 ⁻⁷ seconds when the input value is “768”. Is output. On the other hand, when the input value is “768”, the signal modulation circuit 10 outputs a pulse having a wavelength of 0.6 × 10 ⁻⁷ seconds with a period of 0.8 × 10 ⁻⁷ seconds. For this reason, when the time scale at which the input value changes is sufficiently larger than 0.8 × 10 ⁻⁷ seconds, the value obtained by integrating the pulse of the PDM signal output from the conventional ΔΣ digital modulator and the signal modulation circuit 10 Is the same value as the integrated value of the pulse of the PDM signal output from the.

  As described above, the signal modulation circuit 10 has the same integration value as the pulse of the PDM signal output from the conventional ΔΣ digital modulator regardless of the value of the input value, and the conventional ΔΣ digital modulator outputs it. A PDM signal having a frequency lower than that of the PDM signal is output. Therefore, as shown in FIG. 12, the signal modulation circuit 10 can cause the power element circuit to supply appropriate power regardless of the value of the input analog signal. FIG. 12 is a diagram for explaining an integrated value of the output PDM signal.

  Next, a ΔΣ digital modulation circuit having the signal modulation circuit 10 will be described with reference to FIG. FIG. 13 is a diagram for explaining the ΔΣ digital modulation circuit having the signal modulation circuit according to the first embodiment. The conventional ΔΣ digital modulation circuit operates the difference circuit and the integration circuit regardless of the input value. On the other hand, the ΔΣ digital modulation circuit in which the range indicated by the dotted line in FIG. 13 is replaced with the signal modulation circuit 10 according to the first embodiment can transmit a low-frequency PDM signal while maintaining the duty ratio according to the input value. it can. Such a ΔΣ digital modulation circuit transmits a PDM signal at a frequency in a range in which the power element circuit in the subsequent stage appropriately operates, so that a range in which the power element circuit can perform an appropriate operation is widened.

[Processing flow of signal modulator]
Next, the flow of processing executed by the signal modulation circuit 10 will be described with reference to FIG. FIG. 14 is a flowchart for explaining the flow of processing executed by the signal modulation circuit. In the example illustrated in FIG. 14, the signal modulation circuit 10 starts processing when the power is input.

  First, the signal modulation circuit 10 is determined by the user so that Fcyc_max, which is the maximum value of the frequency of the PDM signal to be output, is set to “1/2” (step S101). Next, the signal modulation circuit 10 identifies a range in which the frequency of the output PDM signal is “½” (step S102).

  Next, the signal modulation circuit 10 determines whether or not an input value is held in Din 22 (step S103). If the signal modulation circuit 10 determines that the input value is held in Din 22 (Yes in step S103), is the input value included in the range in which the frequency of the PDM signal is “1/2”? It is determined whether or not (step S104).

  Next, when the signal modulation circuit 10 determines that the input value is included in the range where the frequency of the PDM signal is “½” (Yes in step S104), the counter initial value is set to “1”. Setting is performed (step S105). Next, the signal modulation circuit 10 performs countdown (step S106). Then, the signal modulation circuit 10 determines whether or not the value of the counter is “0” (step S107).

  Further, when the signal modulation circuit 10 determines that the value of the counter is “0” (Yes at Step S107), the signal modulation circuit 10 executes difference calculation and integration calculation using the circuit indicated by the solid line in FIG. (Step S108). Thereafter, the signal modulation circuit 10 outputs a pulse according to the calculation result (step S109).

  On the other hand, when the signal modulation circuit 10 determines that the value of the counter is not “0” (No in step S107), the signal modulation circuit 10 outputs a pulse according to the calculation result in the immediately preceding step (step S110).

  When the signal modulation circuit 10 determines that the input value is not included in the range where the frequency of the PDM signal is “½” (No in step S104), the circuit indicated by the solid line in FIG. Is used to execute the difference calculation and the integration calculation (step S108). Further, when the signal modulation circuit 10 outputs a pulse (steps S109 and S110), it again determines whether or not the input value is held in the Din 22 (step S103). If the signal modulation circuit 10 determines that the input value is not held in Din 22 (No in step S103), the signal modulation circuit 10 ends the process.

[Effect of Example 1]
As described above, the signal modulation circuit 10 according to the first embodiment includes the XOR 20 that determines whether or not the input value held in the Din 20 is included in the range of “256 to 767”. When the input value is included in the range of “1-255” and “767-1023”, the signal modulation circuit 10 operates the difference circuit 11 and the integration circuit 15 according to the synchronization signal, and sets the input value. Modulate to PDM signal. Further, when the input value held in Din20 is included in the range of “256 to 767”, the signal modulation circuit 10 operates the difference circuit 11 and the integration circuit 15 at a time interval longer than the synchronization signal. The input value is modulated into a PDM signal.

  For this reason, the signal modulation circuit 10 can suppress the frequency of the PDM signal to be output to a range in which the FET can appropriately operate while maintaining the response to the analog signal, and the power element circuit performs an appropriate operation. Increase the range of things you can do.

  In addition, the integration circuit 15 according to the first embodiment quantizes the calculated integration value at the same time interval as the synchronization signal when the input value is included in the range of “1 to 255” and “767 to 1023”. Output to the circuit 23. Further, when the input value is included in the range of “256 to 767”, the integration circuit 15 outputs the calculated integration value to the quantizer 23 at a time interval longer than the synchronization signal. Therefore, the signal modulation circuit 10 can cause the power element circuit to supply appropriate power as a result of lowering the frequency of the PDM signal while maintaining the duty ratio of the PDM signal output to the quantization circuit 23.

  The integration circuit 15 according to the first embodiment includes a first flip-flop 17 that operates at the same time interval as the synchronization signal and a second flip-flop 18 that operates at a time interval longer than the synchronization signal. Then, when the input value is included in the range of “1 to 255” and “767 to 1023”, the integration circuit 15 performs integration using the value held in the first flip-flop 17. Further, when the input value is included in the range of “256 to 767”, the integration circuit 15 performs integration using the value held in the second flip-flop 18. For this reason, the difference circuit 15 can calculate an appropriate integral value even when it operates at a time interval longer than the synchronization signal. As a result, the signal modulation circuit 10 can appropriately suppress the frequency of the output PDM signal without reducing the sampling frequency.

  The difference circuit 11 according to the first embodiment includes a first differentiator 12 that operates at the same time interval as the synchronization signal and a second differencer 13 that operates at a time interval longer than the synchronization signal. The difference circuit 11 inputs the difference value calculated by the first differentiator 12 to the integration circuit 15 when the input value is included in the ranges of “1 to 255” and “767 to 1023”. Further, the difference circuit 11 inputs the difference value calculated by the second differentiator 13 to the integration circuit 15 when the input value is included in the range of “256 to 767”. For this reason, the difference circuit 11 can calculate an appropriate difference value even when it operates at a time interval longer than the synchronization signal. As a result, the signal modulation circuit 10 can appropriately suppress the frequency of the output PDM signal without reducing the sampling frequency.

  The signal modulation circuit 10 according to the first embodiment includes a counter 21 and operates the second differentiator 13 and the second flip-flop 18 in accordance with a clock signal output from the counter 21. For this reason, the signal modulation circuit 10 can lower the frequency of the output PDM signal at an arbitrary ratio. For example, when the initial value “m = 1” is set in the counter 21, the signal modulation circuit 10 sets the frequency of the output PDM signal to “½” and sets the counter 21 to the initial value “m = 3”. Is set, the frequency of the PDM signal to be output can be set to “1/4”.

  Although the embodiments of the present invention have been described so far, the embodiments may be implemented in various different forms other than the embodiments described above. Therefore, another embodiment included in the present invention will be described below as a second embodiment.

(1) Parameters The signal modulation circuit 10 described above modulates an analog signal into a PDM signal with an input resolution of 10 bits and a sampling frequency of 100 MHz. However, the embodiment is not limited to this. For example, the sampling frequency may be 1000 Hz.

Further, the quantization circuit 23 described above transmits a feedback signal indicating “1024”. However, the embodiment is not limited to this. For example, when the input resolution is set to “N” bits, the quantization circuit transmits a feedback signal indicating “2 ^N ”.

  The quantization circuit 23 described above transmits a pulse of the PDM signal when an integral value of “1024” or more is output. However, the embodiment is not limited to this, and for example, “512” or more. When the integrated value of is output, a pulse of the PDM signal may be transmitted.

  Further, the signal modulation circuit 10 described above inputs “1” as the initial value m to the counter 21. However, the embodiment is not limited to this. For example, when the maximum value of the PDM signal to be output is suppressed to “1/4”, the signal modulation circuit 10 may input “3” as the initial value m.

  Here, the signal modulation circuit 10 cooperates with the counter 21 and the XOR circuit 20, determines the input value, and controls the maximum value of the PDM signal. Further, the determination circuit for determining the input value is not limited to the XOR circuit 20.

(2) Regarding the operation of the difference circuit and the integration circuit In the signal modulation circuit 10 described above, when the counter signal is 1, the second difference unit 13 and the second flip-flop 18 have the same value as the value output immediately before. It was output. However, the embodiment is not limited to this.

  As described above, when the range of the input value is included in the predetermined range, if the frequency of the PDM signal can be lowered, the range in which the power element circuit is appropriately operated can be widened.

DESCRIPTION OF SYMBOLS 10 Signal modulation circuit 11 Difference circuit 12 1st difference device 12
13 Second subtractor 13
14 switch 15 integration circuit 16 adder 16
17 First flip-flop 18 Second flip-flop 19 Switch 20 XOR circuit 21 Counter 22 Din
23 Quantization circuit 24 Delay circuit

Claims (7)

An integration circuit that integrates and outputs a differential signal corresponding to an input value that is continuously input at a predetermined time interval;
A quantizing circuit that outputs a quantized signal obtained by quantizing the output of the integrating circuit;
When a quantized signal is output by the quantizing circuit, after the predetermined time interval has elapsed since the quantized signal was output, a difference signal corresponding to the quantized signal and the input value is output. A difference circuit that calculates and inputs the calculated difference signal to the integration circuit;
A determination circuit that monitors the input value and determines whether or not the input value is included in a predetermined range;
With
The integration circuit integrates and outputs the difference signal after a time interval obtained by extending the predetermined time interval elapses when the determination circuit determines that the input value falls within a predetermined range. ,
When the difference circuit determines that the input value is included in a predetermined range by the determination circuit, the difference signal is output after the predetermined time interval has elapsed since the output of the quantized signal. And a difference signal corresponding to the input value, and the calculated difference signal is input to the integration circuit after a time interval obtained by extending the predetermined time interval has elapsed. .   When the determination circuit determines that the input value falls within a predetermined range, the integration circuit integrates the difference signal at a time interval obtained by extending the predetermined time interval, and The integrated signal is output after the extended time interval has elapsed, and if the determination circuit determines that the input value does not fall within a predetermined range, the difference signal is output at the predetermined time interval. 2. The signal modulation circuit according to claim 1, wherein the signal modulation circuit integrates and outputs a signal obtained by integrating the difference signal after the time interval elapses. The integration circuit includes:
An adder circuit that calculates a new integrated signal at the predetermined time interval using the difference signal input from the difference circuit;
When a new integration signal is calculated by the adder circuit, the calculated integration signal is temporarily held, and the held integration signal is output after the predetermined time interval has elapsed. A holding circuit;
When a new integration signal is calculated by the adder circuit, the calculated integration signal is temporarily held until the extended time interval elapses after the predetermined time interval elapses. A second holding circuit that outputs the held integration signal; and if the determination circuit determines that the input value is not within a predetermined range, adds the integration signal output by the first holding circuit. A transmission circuit that transmits the integrated signal output by the second holding circuit to the adder when the determination circuit determines that the input value is included in a predetermined range by the determination circuit;
With
The adder circuit
The signal modulation circuit according to claim 1, wherein a new integration signal is calculated by adding the integration signal acquired from the transmission circuit and the difference signal. The difference circuit is
When a quantized signal is output by the quantizing circuit, after the predetermined time interval has elapsed since the quantized signal was output, a difference signal corresponding to the quantized signal and the input value is output. A first difference circuit that calculates and outputs the calculated difference signal after the predetermined time interval has elapsed;
When a quantized signal is output by the quantizing circuit, a difference signal corresponding to the quantized signal and the input value is obtained after the predetermined time interval has elapsed since the quantized signal was output. A second difference circuit that calculates and outputs the calculated difference signal after a time interval obtained by extending the predetermined time interval;
When the determination circuit determines that the input value is not included in the predetermined range, the difference signal output by the first difference circuit is input to the integration circuit, and the input value is determined by the determination circuit. An input circuit that inputs the difference signal output from the second difference circuit to the integration circuit,
The signal modulation circuit according to claim 1, further comprising: The signal modulation circuit includes:
For the second holding circuit and the second difference circuit, further comprising an output circuit for outputting a signal at a time interval obtained by extending the predetermined time interval,
When the second holding circuit receives the signal output by the output circuit, the second holding circuit outputs the held integrated signal until the next output signal is received,
The second difference circuit, when receiving the signal output by the output circuit, outputs the calculated difference signal until the next output signal is received. 5. The signal modulation circuit according to 4. An integrator that integrates and outputs a differential signal according to an input value that is continuously input at a predetermined time interval;
A quantum unit that outputs a quantized signal obtained by quantizing the output of the integrating unit;
When a quantized signal is output by the quantum unit, a difference signal corresponding to the quantized signal and the input value is calculated after the predetermined time interval has elapsed since the quantized signal was output. A difference unit that inputs the calculated difference signal to the integration unit;
A determination unit that monitors the input value and determines whether or not the input value is included in a predetermined range;
With
When the determination unit determines that the input value is included within a predetermined range, the integration unit integrates and outputs the difference signal at a time interval obtained by extending the predetermined time interval,
The difference unit, when the determination unit determines that the input value is included in a predetermined range, the quantized signal after the predetermined time interval has passed since the quantization signal was output. And a difference signal corresponding to the input value, and the calculated difference signal is input to the integration unit after a time interval obtained by extending the predetermined time interval has elapsed. . A method performed by a signal modulation apparatus for modulating a continuously input input value into a digital signal,
An integration step of integrating and outputting a differential signal corresponding to an input value that is continuously input at a predetermined time interval;
A quantization step for outputting a quantized signal obtained by quantizing the output of the integration step;
When a quantized signal is output by the quantization step, a difference signal corresponding to the quantized signal and the input value is obtained after the predetermined time interval has elapsed since the quantized signal was output. A difference step of calculating and inputting the calculated difference signal to the integration step;
A determination step of monitoring the input value and determining whether the input value falls within a predetermined range;
With
In the integration step, when it is determined by the determination step that the input value is included in a predetermined range, the differential signal is integrated and output after a time interval extending the predetermined time interval has elapsed. And
In the difference step, when it is determined by the determination step that an input value is included in a predetermined range, the quantized signal is output after the predetermined time interval has elapsed since the quantized signal was output. And a difference signal corresponding to the input value, and the calculated difference signal is input to the integration step after a time interval obtained by extending the predetermined time interval has elapsed. .

Images