JP5505443B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device including a JFET or MOSFET having a trench structure and a method for manufacturing the same.

  Conventionally, Patent Documents 1 and 2 disclose SiC semiconductor devices each including a JFET having a trench structure. 7A and 7B are diagrams showing this conventional SiC semiconductor device. FIG. 7A is a plan pattern view, FIG. 7B is a cross-sectional view taken along line XX ′ of FIG. (B) is YY 'sectional drawing of Fig.7 (a).

As shown in this figure, an n ⁻ type drift layer J 2, a p ⁺ type first gate region J 3 and an n ⁺ type source region J 4 are formed in order on an n ⁺ type SiC substrate J 1 and then penetrated therethrough. A trench J5 is formed, and an n ⁻ type channel layer J6 and a p ⁺ type second gate region J7 are formed in the trench J5. Although not shown, by controlling the gate voltage applied to the gate electrode electrically connected to the second gate region J7, the source electrode and n ⁺ type electrically connected to the n ⁺ type source region J4 are controlled. An operation is performed in which a drain current flows between the drain electrode electrically connected to the SiC substrate J1.

JP 2005-328014 A JP 2003-69041 A

  In the conventional SiC semiconductor device, for example, as shown in FIG. 7A, the trenches J5 are formed in a strip shape, and the trenches J5 are arranged in parallel to be laid out in a stripe shape. However, it was confirmed that an excessive drain current is generated when the trenches J5 are arranged in a strip shape. FIG. 8 is a characteristic diagram when the drain current characteristic with respect to the gate voltage in the conventional SiC semiconductor device is examined. As shown in this figure, when the gate voltage approaches the vicinity of the threshold for operating the JFET, it can be confirmed that the drain current has been generated before the threshold is exceeded. Due to the drain current generated in the vicinity of the threshold value, there arises a problem that the JFET cannot have an ideal characteristic, that is, an ideal characteristic that the drain current starts flowing only when the gate voltage reaches the threshold value.

  It has been confirmed that such problems are not limited to JFETs, but occur similarly in MOSFETs having a storage channel layer.

  In view of the above points, the present invention provides a SiC semiconductor device having a structure capable of suppressing an excessive drain current generated when a gate voltage approaches a threshold value in the case where a JFET or MOSFET having a trench structure is provided, and a method for manufacturing the SiC semiconductor device. For the purpose.

When the present inventors diligently studied the above problem, it was found that the JFET structure formed at the tip portion of the trench J5 was affected. That is, when the trench J5 is formed in a strip shape, the long side of the trench J5 is basically used to form a JFET, but since the n ⁺ type source region J4 is formed by epitaxial growth, the substrate is formed. The n ⁺ type source region J4 is formed as a whole, and a JFET is also formed at the tip of the trench J5. For this reason, it is considered that the threshold value of the JFET structure formed at the tip of the trench J5 is different from the threshold value of the JFET structure formed at the long side of the trench J5, causing the above problem.

This was confirmed by changing the width of the trench J5. FIG. 9 is a plan view showing the state of each part at the tip of the trench J5 when the width of the trench J5 is changed. As shown in this figure, when the width of the trench J5 is set to 1.2 μm, 1.7 μm, and 2.1 μm, the thickness of the n ⁻ -type channel layer J6 grown at the tip of the trench J5 is 0. They were 8 μm, 0.6 μm, and 0.5 μm. Such a phenomenon occurs due to the dependency of migration on the width of the trench J5 when forming the n ⁻ -type channel layer J6. As the width of the trench J5 becomes narrower due to the capillary phenomenon, the migration to the tip becomes larger. To occur. For reference, the difference in growth amount between the portion formed at the long side portion of the trench J5 and the portion formed at the tip portion of the n ⁻ -type channel layer J6 was confirmed, and the result shown in FIG. 10 was obtained. As the width of J5 is increased, the difference between the two is reduced. However, as the width of the trench J5 is reduced, the difference between the two is increased.

  Further, when the characteristics of the drain current Id with respect to the gate voltage Vg were examined in each of the above cases, the result was as shown in FIG. 11 (W in the figure indicates the width of the trench J5).

Ideally, the drain current should flow when the gate voltage Vg reaches the threshold value, as shown by the broken line in FIG. 11. However, the gate voltage Vg is a conventional SiC semiconductor device structure. The drain current Id has a characteristic that is ideal. This deviation changes in accordance with the thickness of the n ⁻ -type channel layer J6 formed at the tip of the trench J5, and the deviation amount increases as the thickness increases. This is because the threshold value decreases as the thickness of the n ⁻ -type channel layer J6 increases, and the tip portion increases as the width of the trench J5 decreases and the n ⁻ -type channel layer J6 at the end of the trench J5 increases. The threshold value of the JFET structure configured as described above is affected and deviates from an ideal state. Therefore, if the JFET structure is not formed at the tip of the trench J5, it can be said that the above problem can be prevented.

Therefore, in order to achieve the above object, according to the first aspect of the present invention, in the SiC semiconductor device having the JFET, the second conductivity type deeper than the thickness of the source region (4) at both ends of the trench (6). By forming the region (20), at least the source region (4) and the channel layer (7) located at both ends of the trench (6) are filled with the second conductivity type region (20). The source region (4) is not formed at both ends of the trench (6).

  In the SiC semiconductor device including the JFET configured as described above, the channel layer (7) formed at both ends of the trench (6) is thicker than the portion located on the long side of the trench (6). Even if this is the case, it is possible to prevent the JFET structure from being formed at both ends of the trench (6). For this reason, as in the case of the conventional structure in which the JFET structure is formed at both ends of the trench (6), the JFET structure of the portion where the threshold value of the JFET structure at both ends is located on the long side of the trench (6). It is not affected by deviation from the threshold value. Therefore, it is possible to provide a SiC semiconductor device having a structure capable of suppressing an excessive drain current generated when the gate voltage approaches the threshold.

  The invention according to claim 2 is characterized in that the source region (4) is not formed at both ends of the trench (6) in the SiC semiconductor device provided with the MOSFET. Thus, even in an SiC semiconductor device including a MOSFET, the same effect as in claim 1 can be obtained by adopting the same structure as in claim 1.

  In this case, as described in claim 3, when the trench (6) has a stripe shape in which a plurality of trenches (6) are arranged in parallel, the second conductivity type region (20) has a plurality of trenches (6). It can be made to be a continuous region including the region of the tip.

  A fourth or fifth aspect of the present invention relates to a method of manufacturing an SiC semiconductor device according to any one of the first to third aspects. Each of the SiC semiconductor devices can be manufactured by the manufacturing method described in each of the claims.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is the figure which showed the SiC semiconductor device concerning 1st Embodiment of this invention, (a) is a plane pattern figure, (b) is AA 'sectional drawing of (a), (b) is ( a) BB 'sectional drawing of (a), (d) is CC' sectional drawing of (a). It is the figure which showed the result of having investigated the characteristic of the drain current (A) with respect to the gate voltage (V) of the conventional structure and the structure of 1st Embodiment. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1. It is the figure which showed the SiC semiconductor device concerning 2nd Embodiment of this invention, (a) is a plane pattern figure, (b) is DD 'sectional drawing of (a), (b) is ( It is EE 'sectional drawing of a). FIG. 5 is a cross sectional view showing a manufacturing step of the SiC semiconductor device shown in FIG. 4. It is the figure which showed the SiC semiconductor device concerning 3rd Embodiment of this invention, (a) is a plane pattern figure, (b) is FF 'sectional drawing of (a), (b) is ( It is GG 'sectional drawing of a). It is the figure which showed the conventional SiC semiconductor device, (a) is a plane pattern figure, (b) is XX 'sectional drawing of (a), (b) is YY' of (a). It is sectional drawing. It is a characteristic view when the drain current characteristic with respect to the gate voltage in the conventional SiC semiconductor device was investigated. It is the top view which showed the mode of each part of the front-end | tip part of the trench J5 when the width | variety of the trench J5 was changed. It is a figure which shows the result of having investigated the difference in the amount of growth of the part formed in the long side part of trench J5 among the n < ^- > type | mold channel layer J6, and the part formed in a front-end | tip part. It is a figure which shows the result of having investigated the characteristic of the drain current Id with respect to the gate voltage Vg.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. 1A and 1B are diagrams showing a SiC semiconductor device according to the present embodiment, in which FIG. 1A is a plane pattern diagram, FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. 1B is a cross-sectional view taken along the line BB ′ in FIG. 1A, and FIG. 1D is a cross-sectional view taken along the line CC ′ in FIG.

The SiC semiconductor device shown in FIGS. 1A to 1D is configured using an n ⁺ -type SiC substrate 1. The n ⁺ -type SiC substrate 1, for example, can be used off-substrate, n ⁺ -type SiC is independent of the layout and off direction of the cell of the JFET is formed on the substrate 1 off the cell layout of the JFET There is no need to match the direction.

First, the basic structure of JFET will be described. The basic structure of the JFET is the structure shown in FIG. Specifically, a trench 6 is formed in a semiconductor substrate 5 in which an n ⁻ type drift layer 2, a p ⁺ type first gate region 3, and an n ⁺ type source region 4 are sequentially formed on an n ⁺ type SiC substrate 1. An n ⁻ type channel layer 7 is formed from the inner wall of the trench 6 to the surface of the semiconductor substrate 5. A p ⁺ -type second gate region 8 is formed on the surface of the n ⁻ -type channel layer 7 so as to completely fill the inside of the trench 6. A gate electrode 9 is formed on the surface of the second gate region 8, and a source electrode 11 is formed thereon via an interlayer insulating film 10. Source electrode 11 is electrically connected to n ⁺ type source region 4 through a contact hole formed in interlayer insulating film 10. Further, n ⁺ on the back surface of the mold SiC substrate 1 and the drain electrode 12 are formed, it is electrically connected to the n ⁺ -type SiC substrate 1 to be a drain region. With this structure, the basic structure of JFET is configured.

Further, as shown in FIG. 1A, the opening shape of the trench 6 is a strip shape, and a plurality of trenches 6 having such an opening shape are arranged in parallel to be arranged in a stripe shape. Yes. Then, as shown in FIGS. 1C and 1D, a mesa structure in which the n ⁺ type source region 4 is removed from the outer edge portion of the n ⁺ type SiC substrate 1 including the periphery of the front end portion of the trench 6. In addition, a concave shape is formed by removing the n ⁻ -type channel layer 7 and the second gate region 8 at the tip of the trench 6. Therefore, the n ⁺ -type source region 4 is in a state where only the position adjacent to the long side of each trench 6 is left, and the JFET structure is configured only in that region.

In the SiC semiconductor device including the JFET configured as described above, even if the n ⁻ -type channel layer 7 formed at the tip of the trench 6 is thicker than the portion located on the long side of the trench 6. The JFET structure can be prevented from being formed at the tip of the trench 6. For this reason, as in the case of the conventional structure in which the JFET structure is formed at the tip of the trench 6, the threshold of the JFET structure at the tip is shifted from the threshold of the JFET structure at the portion located on the long side of the trench 6. Not affected. Therefore, it is possible to provide a SiC semiconductor device having a structure capable of suppressing an excessive drain current generated when the gate voltage approaches the threshold.

In particular, in the tip portion of the trench 6, a region that is thicker than a portion of the n ⁻ -type channel layer 7 formed on the long side portion of the trench 6 and a region that is longer than the thickness of the first gate region 3 from that region It is preferable that the concave shape is removed. By doing so, the distance between the channel portion having an increased film thickness and the n ⁺ -type source region 4 becomes equal to or longer than the channel length, and the drain current is completely cut even in the off state near the threshold voltage. Occurrence can be prevented.

FIG. 2 shows a conventional structure in which the n ⁺ -type source region 4 remains at the tip of the trench 6 and a concave shape in which the n ⁺ -type source region 4 is removed at the tip of the trench 6 as in this embodiment. It is the figure which showed the result of having investigated the characteristic of the drain current (A) with respect to the gate voltage (V) in the case of each structure. As shown in this figure, in the structure of this embodiment, the drain current does not flow when the gate voltage approaches the threshold value unlike the conventional structure, and the drain current is not reached until the threshold value is reached. Can flow. This experimental result also shows that the SiC semiconductor device has a structure that can suppress an excessive drain current that is generated when the gate voltage approaches the vicinity of the threshold value.

  Next, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device according to the present embodiment, in which the left side of the drawing corresponds to the cross section corresponding to FIG. 1B, and the right side of the drawing shows the cross section corresponding to FIG. The state during the process is shown.

First, in the step shown in FIG. 3A, the n ⁻ type drift layer 2, the p ⁺ type first gate region 3 and the n ⁺ type source region 4 are epitaxially grown on the surface of the n ⁺ type SiC substrate 1 in order. Thus, the semiconductor substrate 5 is configured.

Subsequently, in the step shown in FIG. 3B, a trench 6 is formed by disposing a mask (not shown) in which a region where the trench 6 is to be formed is opened, and then performing anisotropic etching such as RIE (Reactive Ion Etching). To do. Then, the n ⁻ type channel layer 7 is formed by epitaxial growth. At this time, n ^- the migration type channel layer 7, the bottom and the tip portion of the trench 6, n than the side wall surface of the long side of the trench 6 ^- thickness type channel layer 7 is formed thickly.

In the step shown in FIG. 3C, after the second gate region 8 made of a p ⁺ type layer is epitaxially grown on the surface of the n ⁻ type channel layer 7, the n ⁺ type is obtained by CMP (Chemical Mechanical Polishing) or the like. The second gate region 8 and the n ⁻ -type channel layer 7 are planarized until the source region 4 is exposed, so that they remain only inside the trench 6.

Thereafter, the mesa structure is formed by removing the n ⁺ type source region 4 at the outer edge of the substrate. At this time, the n ⁺ type source region 4 and the n ⁻ type channel layer 7 and the vicinity of the tip of the trench 6 are simultaneously formed. The second gate region 8 is partially removed to form a concave shape. Specifically, after placing a mask having an opening in the outer edge of the substrate, the n ⁺ -type source region 4 and the n ⁻ -type channel layer 7 and the second gate region 8 that are partially removed, an anisotropic process such as RIE is performed. The portion where the mask is opened is removed by performing etching. As a result, in addition to the n ⁺ type source region 4 at the outer edge of the substrate, the n ⁺ type source region 4, the n ⁻ type channel layer 7 and the second gate region 8 are partially removed and recessed at the tip of the trench 6. It becomes a shape. Then, the same manufacturing steps as the conventional ones such as the gate electrode 9 forming step, the interlayer insulating film 10 forming step, the contact hole forming step, the source electrode 11 forming step and the drain electrode 12 forming step are performed. The SiC semiconductor device shown in FIG.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the JFET structure is not formed at the tip of the trench 6 by a method different from that of the first embodiment, and the basic structure of the SiC semiconductor device is the same as that of the first embodiment. Therefore, only a different part from 1st Embodiment is demonstrated.

  4A and 4B are diagrams illustrating the SiC semiconductor device according to the present embodiment, in which FIG. 4A is a plane pattern diagram, FIG. 4B is a cross-sectional view taken along the line DD ′ of FIG. FIG. 4B is a cross-sectional view taken along the line EE ′ of FIG.

As shown in FIGS. 4A to 4C, in the present embodiment, the n ⁺ -type source region 4, the n ⁻ -type channel layer 7 and the second channel are formed in the vicinity of the tip of the trench 6 as in the first embodiment. Instead of partially removing the gate region 8, the p ⁺ -type region 20 is configured by ion-implanting a p-type impurity in the region near the tip. Specifically, as shown in FIG. 4A, the p ⁺ -type region 20 is laid out in a strip shape (rectangular shape) so as to include all the tip portions of the trenches 6, and the first gate region 3 Alternatively, it is shallower than the second gate region 8 and deeper than the n ⁺ -type source region 4. By this p ⁺ type region 20, all of the n ⁻ type channel layer 7 located between the n ⁺ type source region 4 and the second gate region 8 at least at the tip of the trench 6 is filled with the p ⁺ type region 20. As a result, the JFET structure is not formed at the tip of the trench 6.

Thus, even if the vicinity of the front end portion of the trench 6 is filled with the p ⁺ -type region 20, the JFET structure can be prevented from being formed at the front end portion of the trench 6. Therefore, the same effect as that of the first embodiment can be obtained. Can be obtained.

  FIG. 5 is a view showing a manufacturing process of the SiC semiconductor device according to the present embodiment. The manufacturing process of the cross section corresponding to FIG. 4B on the left side of the paper and the cross section corresponding to FIG. 4C on the right side of the paper. The inside is shown. However, in FIG. 5, only the parts different from the first embodiment are shown.

First, similarly to the first embodiment, the process shown in FIGS. 3A to 3C is performed to obtain the structure shown in FIG. Subsequently, although not shown, after a mask such as LTO is arranged, a region where the p ⁺ type region 20 is to be formed is opened. Then, a p-type impurity is ion-implanted using the mask and activated by heat treatment, thereby forming a p ⁺ -type region 20 as shown in FIG. Although not shown in the drawings, a process for removing the n ⁺ -type source region 4 at the outer edge of the substrate, a process for forming the gate electrode 9, a process for forming the interlayer insulating film 10, and a process for forming a contact hole in order to form a mesa structure The SiC semiconductor device shown in FIG. 4 is completed by performing manufacturing steps similar to those of the prior art, such as the source electrode 11 forming step and the drain electrode 12 forming step.

As described above, the manufacturing method of the SiC semiconductor device according to the present embodiment performs the step of forming the p ⁺ -type region 20, and the n ⁺ -type source region 4 and the n ⁻ -type channel layer 7 when forming the mesa structure. The second embodiment is different from the first embodiment in that the second gate region 8 is not partially removed, but is basically the same as the first embodiment.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the JFET structure is not formed at the tip of the trench 6 by a method different from that of the first embodiment, and the basic structure of the SiC semiconductor device is the same as that of the first embodiment. Therefore, only a different part from 1st Embodiment is demonstrated.

  6A and 6B are diagrams showing the SiC semiconductor device according to the present embodiment, in which FIG. 6A is a plane pattern diagram, FIG. 6B is a cross-sectional view taken along line FF ′ in FIG. FIG. 6B is a cross-sectional view taken along the line GG ′ of FIG.

As shown in FIGS. 6A to 6C, in this embodiment, the n ⁺ -type source region 4, the n ⁻ -type channel layer 7 and the second channel are formed in the vicinity of the tip of the trench 6 as in the first embodiment. Instead of partially removing the gate region 8, the n ⁺ type source region 4 is formed by selective ion implantation so that the n ⁺ type source region 4 is not formed in a region near the tip of the trench 6. To. Specifically, as shown in FIG. 6A, an n ⁺ type source region 4 is formed by ion implantation of an n type impurity in a portion adjacent to the long side of each trench 6. However, as shown in FIGS. 6A to 6C, the first gate region 3 is formed in the vicinity of the tip of the trench 6 up to the same height as the surface of the second gate region 8. Thus, the n ⁺ -type source region 4 is not formed.

Thus, even if the n ⁺ type source region 4 is formed by selective ion implantation so that the n ⁺ type source region 4 is not formed in a region near the tip of the trench 6, the tip of the trench 6 is formed. Therefore, the same effect as that of the first embodiment can be obtained.

The manufacturing method of the SiC semiconductor device having such a structure is different from the first embodiment in that the step of forming the n ⁺ -type source region 4 is performed by ion implantation, but is basically the same as the first embodiment. is there.

(Other embodiments)
In each of the above embodiments, the SiC semiconductor device provided with the JFET has been described. Instead of the second gate region 8, a gate insulating film is formed on the surface of the n ⁻ -type channel layer 7 and a gate is formed on the surface of the gate insulating film. A structure similar to that of each of the above embodiments can also be adopted for a SiC semiconductor device including a MOSFET in which electrodes are arranged. If the structure of each of the above embodiments is employed in a semiconductor including a MOSFET, the MOSFET structure can be prevented from being formed at the tip of the trench 6, so that the same effect as in each of the above embodiments can be obtained.

As for the difference between the MOSFET and JFET manufacturing methods, the step of forming a gate insulating film by thermal oxidation or the like after forming the n ⁻ -type channel layer 7, the step of forming a gate electrode on the surface of the gate insulating film, Using the region described as the first gate region 3 in the embodiment as a base region, the step of planarizing the gate electrode, the gate insulating film, and the n ⁻ -type channel layer 7 is performed until the base region is exposed. Although different from the embodiment, the other points are the same as those of the above embodiments.

In the first embodiment, a concave shape is formed in a wide range near the tip of the trench 6, and in the second embodiment, the p ⁺ -type region 20 is formed in a wide range near the tip of the trench 6. However, these are also merely showed only one example, as JFET structure at the distal end of at least the trench 6 is not configured, the n ⁺ -type source region 4 can be removed concave shape, or n ⁺ -type source region 4 to the p-type It is sufficient that the p ⁺ -type region 20 to be inverted is formed. However, at the front end portion of the trench 6, the n ⁻ type channel layer 7 is completely filled with the concave shape from which the region thicker than the long side portion of the trench 6 is removed, or the p ⁺ type region 20. Then, even if the mask displacement of the etching mask or the ion implantation mask of the p-type impurity occurs, it is possible to prevent the JFET structure or the MOSFET structure from being configured at the tip of the trench 6 more reliably.

In each of the above embodiments, an n-channel type JFET or MOSFET in which a channel region is set in the n ⁻ -type channel layer 7 has been described as an example. However, a p-channel type in which the conductivity type of each component is reversed. The present invention can also be applied to JFETs and MOSFETs.

Furthermore, the above first and second embodiments have been described the n ⁺ -type source region 4 which is epitaxially grown, the n ⁺ -type source region by ion-implanting the n-type impurity with respect to the first gate region 3 4 may be formed.

  In each of the above-described embodiments, the rectangular trench 6 having one direction as the longitudinal direction has been described as an example of a rectangle. A strip shape such as a sharp hexagonal shape (for example, a shape in which only two opposite sides of a regular hexagon are elongated) may be used.

1 n ⁺ type SiC substrate 2 n ⁻ type drift layer 3 First gate region (base layer)
4 n ⁺ type source region 5 Semiconductor substrate 6 Trench 7 n ⁻ type channel layer 8 Second gate region 9 Gate electrode 10 Interlayer insulating film 11 Source electrode 12 Drain electrode 20 p ⁺ type region

Claims (6)

A first conductivity type substrate (1) made of silicon carbide, a first conductivity type drift layer (2) formed by epitaxial growth on the first conductivity type substrate (1), and on the drift layer (2) A first conductivity type first gate region (3) formed by epitaxial growth; and a first conductivity type source region (4) formed by epitaxial growth or ion implantation on the first gate region (3). A semiconductor substrate (5);
A strip-shaped trench (6) penetrating the source region (4) and the first gate region (3) to the drift layer (2) and having one direction as a longitudinal direction;
A channel layer of a first conductivity type formed by epitaxial growth on the inner wall of the trench (6) and having a thickness greater than the long side portion of the trench (6) at both ends of the trench (6). 7) and
A JFET having a second conductivity type second gate region (8) formed on the channel layer (7);
The second conductivity type region (20) deeper than the thickness of the source region (4) is formed at both ends of the trench (6), and the source located at least at both ends of the trench (6) Since the region (4) and the channel layer (7) are filled with the second conductivity type region (20), the source region (4) is formed at both ends of the trench (6). The silicon carbide semiconductor device characterized by not having. A first conductivity type substrate (1) made of silicon carbide, a first conductivity type drift layer (2) formed by epitaxial growth on the first conductivity type substrate (1), and on the drift layer (2) A semiconductor substrate (5) having a second conductivity type base layer (3) formed by epitaxial growth and a first conductivity type source region (4) formed by epitaxial growth or ion implantation on the base layer (3). )When,
A strip-shaped trench (6) penetrating the source region (4) and the base layer (3) to the drift layer (2) and having one direction as a longitudinal direction;
A channel layer of a first conductivity type formed by epitaxial growth on the inner wall of the trench (6) and having a thickness greater than the long side portion of the trench (6) at both ends of the trench (6). 7) and
A gate insulating film formed on the channel layer (7);
A MOSFET having a gate electrode formed on the surface of the gate insulating film in the trench (6);
The second conductivity type region (20) deeper than the thickness of the source region (4) is formed at both ends of the trench (6), and the source located at least at both ends of the trench (6) Since the region (4) and the channel layer (7) are filled with the second conductivity type region (20), the source region (4) is formed at both ends of the trench (6). The silicon carbide semiconductor device characterized by not having.   The trench (6) has a stripe shape in which a plurality of the trenches (6) are arranged in parallel, and the second conductivity type region (20) is a continuous region including a region of the tip of the plurality of trenches (6). The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device. A first conductivity type substrate (1) made of silicon carbide, a first conductivity type drift layer (2) formed by epitaxial growth on the first conductivity type substrate (1), and on the drift layer (2) A first conductivity type first gate region (3) formed by epitaxial growth; and a first conductivity type source region (4) formed by epitaxial growth or ion implantation on the first gate region (3). Preparing a semiconductor substrate (5);
Forming a strip-shaped trench (6) having a longitudinal direction in one direction, penetrating the source region (4) and the first gate region (3) to reach the drift layer (2);
A first conductivity type channel layer (7) is formed on the inner wall of the trench (6) by epitaxial growth so that the film thickness is thicker at the both ends of the trench (6) than at the long side of the trench (6). And a process of
Forming a second gate region (8) of the second conductivity type formed on the channel layer (7);
Planarizing the channel layer (7) and the second gate region (8) until the source region (4) is exposed;
After the planarization, the source regions (4) located at both ends of the trench (6) at least deeper than the thickness of the source region (4) are filled at both ends of the trench (6). Forming a second conductivity type region (20), and a method for manufacturing a silicon carbide semiconductor device including a JFET. A first conductivity type substrate (1) made of silicon carbide, a first conductivity type drift layer (2) formed by epitaxial growth on the first conductivity type substrate (1), and on the drift layer (2) A semiconductor substrate (5) having a second conductivity type base layer (3) formed by epitaxial growth and a first conductivity type source region (4) formed by epitaxial growth or ion implantation on the base layer (3). )
Forming a strip-shaped trench (6) having a longitudinal direction in one direction, penetrating the source region (4) and the base layer (3) to the drift layer (2);
A first conductivity type channel layer (7) is formed on the inner wall of the trench (6) by epitaxial growth so that the film thickness is thicker at the both ends of the trench (6) than at the long side of the trench (6). And a process of
Forming a gate insulating film on the channel layer (7);
Forming a gate electrode on the surface of the gate insulating film in the trench (6);
Planarizing the gate electrode, the gate insulating film and the channel layer (7) until the source region (4) is exposed;
After the planarization, the source regions (4) located at both ends of the trench (6) at least deeper than the thickness of the source region (4) are filled at both ends of the trench (6). Forming a second conductivity type region (20), and a method of manufacturing a silicon carbide semiconductor device including a MOSFET. In the step of forming the trench (6), the trench (6) has a stripe shape in which a plurality of trenches (6) are arranged in parallel.
In the step of forming the second conductivity type region (20), the second conductivity type region (20) is formed in a continuous region including the region of the tip portion of the plurality of trenches (6). A method for manufacturing a silicon carbide semiconductor device according to claim 4 or 5.

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