JP5503048B2 - Semiconductor integrated circuit having power controllable region - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having a power controllable region. Specifically, the present invention relates to a semiconductor integrated circuit in which a test circuit is incorporated in a semiconductor integrated circuit having a region where power supply can be controlled on and off, and a design method thereof.

  In recent years, there has been a strong demand for low power consumption of electronic devices, and therefore, semiconductor integrated circuits having a power supply control function are being used. FIG. 14 is a layout diagram of a semiconductor integrated circuit having a power controllable region. The semiconductor integrated circuit 10 is wired with a power supply VDD as a PAD supply power supply and a ground power supply GND as a PAD supply GND. The semiconductor integrated circuit 10 has an always-on area 11 in which the power is always on, and a power controllable area 12 in which the power can be turned on / off by power control. A power supply VSD is wired as a power supply in the power controllable area 12, and the power controllable area 12 is operated by the power supply from the power supply VSD. Power supply control switches 13A and 13B are provided between the power supply VDD and the power supply VSD, and the power supply control switches 13A and 13B are ON / OFF controlled by a power supply control signal CTL input from the outside of the power supply controllable region 12.

  FIG. 15 is a circuit diagram of power supply control. A plurality of semiconductor switches 14 (here, pMOS transistors) are provided between the power supply VDD and the power supply VSD, and the control signal line 16 is wired so that the power supply control signal CTL is applied to the gate of each semiconductor switch 14. . Further, a buffer 15 for timing adjustment is inserted between the semiconductor switches 14.

  In such a configuration, the voltage of the power supply VSD is controlled by ON / OFF control of the power supply control switches 13A and 13B by the power supply control signal CTL. As a result, an appropriate voltage is supplied to the power supply VSD in accordance with the operation level of the logic circuit 18 in the power controllable area, and when the power controllable area 12 is stopped, power supply to the power supply VSD is performed. Stopped. Then, leakage current from the power supply VDD to the ground power supply GND can be prevented, and low power consumption can be realized.

  An LSI having a power control function or a power shutdown function is disclosed in Patent Document 1.

JP 2006-170663 A

  Since the conventional power controllable area is a small area, the number of semiconductor switches constituting the power control switch can be very small (for example, one or two). On the other hand, in recent years, the power controllable area has become larger and the operation has become complicated, so that the configuration of the power control switch requires many semiconductor switches. However, with the increase in the number of semiconductor switches constituting the power control switch, the following problems have arisen.

For example, as shown in FIG. 16, the control signal line 16 is disconnected halfway, and the potential of the signal line at the disconnected position becomes indefinite. This indefinite potential may cause a defect that the semiconductor switch 14 is fixed in a state in which it is always OFF. In this case, only the switch on the left side in FIG. 16 operates normally, and the voltage necessary for the power supply VSD is not supplied. Then, an IR drop occurs during the operation of the power controllable area 12, and the potential of the power supply VSD is lowered.
In this case, the presence of switches that are always OFF increases the amount of voltage drop (IR drop) between the power supply lines VDD and VSD as compared to when each switch operates normally. Therefore, the value of the voltage supplied to the logic circuit 18 may not be a sufficient value, causing a problem that the logic circuit 18 malfunctions or the logic circuit 18 does not operate at a specified operating frequency.

  Alternatively, as shown in FIG. 17, the control signal line 16 may be disconnected in the middle, and the potential at the disconnection portion may become unstable, which may cause a defect in which the semiconductor switch 14 is fixed in a constantly ON state. obtain. In this case, even when the logic circuit 18 in the power controllable area 12 stops operating, the power control switches 13A and 13B are turned off by a predetermined number or all to suppress the leakage current. Therefore, the original purpose of introducing the power control 13A, 13B switch cannot be achieved.

  Further, if the number of semiconductor switches 14 constituting the power control switches 13A and 13B increases, the number of switches that are always ON due to disconnection or the number of switches that are always OFF due to disconnection increases. The amount of leakage current is further increased.

  Here, conventionally, even if a failure has occurred in the control signal line that controls the power control switches 13A and 13B, it is very difficult to identify the cause. For example, in the case of FIG. 16, if an IR drop causes a malfunction of the power controllable region 12 or a reduction in operating frequency, an error is detected. However, it is specifically determined whether the control signal line 16 is broken, whether the logic of the power control signal CTL is wrong, or whether the transistor in the power controllable region 12 is defective. It is difficult to do. In the case of FIG. 17, it is detected that there is a leakage current. However, a leakage current is always generated in the ON region 11, or a leakage current is generated in the power controllable region 12 due to disconnection of the control signal line 16. It is difficult to specify whether or not there is. Therefore, the conventional technique has a problem to be solved that it has not been possible to specify that the malfunction of the circuit, the increase in the leakage current, or the like has occurred due to the disconnection of the control signal line 16.

  According to one embodiment, a semiconductor integrated circuit includes a first switch connected between a first power supply line and a second power supply line and connected to a predetermined circuit, and a first power supply line. And a second switch connected to a predetermined circuit, a first control signal line connected to the first switch, and a second switch. A second control signal line, a logic gate to which control signals from the first control signal line and the second control signal line are respectively input, and a logic gate connected to the output of the logic gate. And a terminal. The first control signal line extends in a direction intersecting with the first power supply line.

  According to such a configuration, the value of the power control signal can be observed from the outside. As a result, it is possible to identify whether a malfunction of the logic circuit or an increase in leakage current occurs due to disconnection of the control signal line with respect to the switch, or whether these problems occur due to other factors.

1 is a layout diagram of a semiconductor integrated circuit having a power controllable region according to a first embodiment. The figure which shows the modification 1 of 1st Embodiment. The figure which shows the modification 2 of 1st Embodiment. The figure which shows the modification 3 of 1st Embodiment. The figure which shows 2nd Embodiment. The figure which shows FF for observation. The figure which shows a mode that the test of a power supply control switch is performed in 3rd Embodiment. The figure which shows a mode that the logic test of circuits other than a power supply control switch is performed in 3rd Embodiment. The figure which shows the procedure of the conventional design method. The figure which shows a power supply hierarchy. The figure which shows the procedure of the conventional design method. The figure which shows the design procedure for inserting the scan test of a power supply control switch in 4th Embodiment. The figure which shows a mode that the addition of the output node and the FF for switch observation were inserted in 4th Embodiment. In background art, the layout diagram of the semiconductor integrated circuit which has a power supply controllable area. The figure which shows the structure of a power supply control switch. The figure which shows an example of the defect of a power supply control switch. The figure which shows an example of the defect of a power supply control switch.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be illustrated and described with reference to reference numerals attached to respective elements in the drawings.
(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a layout diagram of a semiconductor integrated circuit having a power controllable region according to the first embodiment.
In FIG. 1, the semiconductor integrated circuit 100 has a constantly ON region 200 and a power controllable region 300. Power control switches 310A and 310B are provided between the power supply VDD and the power supply VSD, and the power control switches 310A and 310B are ON / OFF controlled by a power control signal CTL input from the outside of the power controllable area 300. The

  The power control switches 310A and 310B are composed of a plurality of lines. As described with reference to FIG. 15, each power supply control switch group includes a switch cell 17 including a pair of a semiconductor transistor 14 that switches between a power supply VDD and a power supply VSD and a timing adjustment buffer 15. The power supply control signal line 320 is branched for each of the power supply control switch groups 310 </ b> A and 310 </ b> B, and the branch lines 320 </ b> A and 320 </ b> B are wired in the power supply controllable region 300. Then, the switch cells 17 are arranged for each of the branched power control signal lines 320A and 320B, and constitute the power control switch series 310A and 310B, respectively.

Here, in the first embodiment, output nodes 330A and 330B and output terminals 340A and 340B for taking out the signal of the control signal line 320 to the outside are provided.
The output nodes 330A and 330B and the output terminals 340A and 340B are provided for each of the branched control signal lines 320A and 320B, that is, for each series of the power control switches 310A and 310B.
The output nodes 330 </ b> A and 330 </ b> B enable the output of the last stage of the power control switch to be output to the outside of the power controllable area 300 for each power control switch series. The output terminals 340A and 340B are connected to lines drawn from the output nodes 330A and 330B, respectively. The output terminals 340A and 340B output the output of the last stage of the power control switch to the outside of the chip for each power control switch series.

  In such a configuration, the operation of the power control switches 310A and 310B can be confirmed. Specifically, the presence or absence of disconnection of the control signal line is determined as described below.

  Here, for example, when the control signal lines 320A and 320B are disconnected in the middle, as can be understood from the description of FIGS. The value is fixed at either high level or low level depending on the disconnection situation. Then, the state of the switch between the determined location and the output terminal 340A or 340B is either always ON or always OFF, and responds to any change in the logical value of the control signal CTL that controls the connection state of each switch. Disappear. In this embodiment, this phenomenon is used. That is, for example, when a test device is connected to the output terminal 340A and the logical value of the output terminal 340A is observed, the output is output from the output terminal 340A in response to a change in the logical value of the signal CTL input to the control signal line 320A. When the logic value to be changed is changed, the control signal line 340A is not disconnected. On the other hand, when the logic value of the signal CTL input to the control signal line 320A is changed and the logic value of the signal output from the output terminal 340A is fixed without changing, the control signal line 320A is The disconnection has occurred in any part of the signal line. The above is a description of determining whether or not the control signal line 320A is disconnected using the output terminal 340A, but the same applies to determining whether or not the control signal line 320B is disconnected using the output terminal 340B. In the prior art, as described above, it is separated from which of a plurality of generation factors the malfunction of the logic circuit 18 due to the IR drop and the increase of the leakage current in a predetermined region on the chip are caused. I couldn't. However, according to the present embodiment, it is possible to determine whether or not the control signal line for controlling each switch is disconnected. Therefore, in this embodiment, the malfunction of the logic circuit 18 based on the IR drop and the increase in the leakage current in the predetermined region are due to the disconnection of the control signal to the switch that controls the supply of voltage to the power controllable region 300. Or whether it is due to other factors.

  Further, when performing an operation test, there is a concept of providing an external output terminal for each semiconductor switch cell 17, but there is a problem that the number of test points increases because there are many semiconductor switches constituting the power control switch. Not right. In this regard, in this embodiment, the output nodes 330A and 330B and the output terminals 340A and 340B may be provided for each of the power supply control switch groups 310A and 310B, so that the number of observation points is very small.

(Modification)
As a first modification, as shown in FIG. 2, signals that have passed through the power supply control switch series 310A to 310E are input to AND, OR, and XOR logic gates 211, 212, and 213, and their respective output signals. May be output to the output terminals 340C to 340E. Note that the XOR in FIG. 2 is a multi-input XOR, but actually, a 2-input XOR is configured in multiple stages. In other words, the AND gate can inspect the case where all the values indicated by the control signal line are “1”, and the OR gate can inspect the case where all the values indicated by the control signal line are “0”. For example, when the CTL is at a high level, the signal line is disconnected unless the output of the AND gate becomes a high level. If the output of the OR gate does not become low level when CTL is at low level, it can be determined that the signal line is disconnected. Also, in the case of a two-input XOR having a multi-stage configuration, the signal line is not disconnected if a low level signal is output from the XOR regardless of whether the CTL is at a low level or a high level. If a high level signal is output from XOR in the high state, it can be determined that the signal line is disconnected.

  Further, as a second modification, as shown in FIG. 3, signals that have passed through the power supply control switch series 310 </ b> A to 310 </ b> E are respectively input to flip-flops (FF) 221 to 225, and their outputs are passed through a multiplexer 230. You may make it selectively output to the output terminal 340F. In this case, the output of each control signal line propagating through the CTL is temporarily held in each FF 221 to 225. Then, by switching the value of the signal select for the MUX 230, the value held by each FF is output to the terminal 340F. Note that the FF 221 to FF 225 may not be provided, and the output of the MUX 230 may be switched based on the value of select, and each control signal line output propagating through the CTL may be output to the outside. According to such a configuration, the number of observation points can be reduced even when there are many power control switches. Further, as a third modification, as shown in FIG. 4, the number of output nodes and output terminals may be reduced by configuring the power control switch in a series of daisy chains.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
The second embodiment is a configuration for performing a circuit test including a power switch by a scan test. FIG. 5 shows a second embodiment. In the second embodiment, in order to execute a scan path test, the predetermined flip-flop is configured as a scan flip-flop (hereinafter referred to as an observation FF).

  As shown in FIG. 6, the observation FF has a configuration in which a multiplexer 410 is added to an input of a normal flip-flop 400. The multiplexer 410 switches the input signal to the data input pin of the flip-flop 400 between normal data input (DIN) and scan-in (SIN). The multiplexer 410 switches between the normal operation and the test mode in response to the ShiftEnable signal, captures the scan-in (SIN) in the test mode, and supplies it to the data terminal of the flip-flop. The flip-flops 400 are connected to each other so that the scan-out (SIN) of the next-stage flip-flop 400 becomes the scan-out of the previous-stage flip-flop 400. Thereby, a scan chain of a scan path test is configured.

  In FIG. 5, the multiplexer 410 of the observation FF is omitted for easy understanding, and D and SIN are shown as data terminals. Further, the ShiftEnable signal is input to the multiplexer of each flip-flop, but the wiring of the ShiftEnable signal is omitted in FIG. Also, normal data input lines during normal operation of each observation FF are omitted, and scan chain wiring is mainly shown. In FIG. 5, only one (symbol 19) is illustrated as a logic circuit necessary for normal operation, and the others are omitted.

In FIG. 5, first, a scan chain for testing each of the signal lines that control the connection state of the power control switches 310A and 310B will be described.
The scan chain for testing each of the signal lines that control the connection state of the power control switches 310A and 310B is the line from SIN1 to SO1. The scan chain SIN1 further includes, for example, a data terminal of FF (flip-flop) provided on the SO1 side from the FF503, and a data terminal of FF provided on the SO3 side from the FF507 provided in SIN3 which is another scan chain. It is also used for testing the operation of the logic circuit connected between the two. This test is a scan path test known as a known technique. That is, SIN1 is provided for testing signal lines for controlling the connection state of the power supply control switches 310A and 310B in addition to testing the operation of the logic circuit provided in the semiconductor integrated circuit 100.

  On the other hand, SIN2 and SIN3, which are scan chains different from SIN1, are also provided in the semiconductor integrated circuit 100 of FIG. SIN2 and SIN3 are scan chains for testing a logic circuit provided in the always-on area 200 and a logic circuit provided in the power controllable area 300. In FIG. 5, SIN 3 is used for testing the logic circuit 19 provided in the always-on area 200, but actually, it is also used for testing the logic circuit provided in the power shut-off area 300. In particular, FF508, FF509, FF510, and FF511 are FFs used for testing a logic circuit in the power controllable area 300. Similarly to SIN3, SIN2 is a scan chain used for testing a logic circuit provided in the always-on area 200 and the power-off possible area 300.

  In FIG. 5, an observation FF 501 to which a power supply control signal CTL is input during normal operation is provided, and scan path test test data SIN 1 is input to the scan-in terminal of the observation FF 501 from a scan-in terminal outside the chip. . The data output of the observation FF 501 is input to the power supply control switches 310A and 310B via the OR circuit 241.

  Here, in the present embodiment, the test of the control signal line that propagates the control signal CTL that controls the connection state of whether the power control switch 310A or 310B is on or off is performed as follows.

First, the control signal ShiftEnable is activated. For example, ShiftEnable is set to high level.
In this case, as described above, each FF included in SIN1, SIN2, and SIN3 takes in the input signal on the SIN side in each FF in response to ShiftEnable having become high level. Since Shift Enable is at a high level, the logical value of the signal output from the OR circuit 241 is also fixed at a high level. Here, the OR circuit 241 is connected to a control signal line for propagating CTL (see FIG. 5). That is, since the OR circuit 241 is fixed at a high level, the on / off state of each switch that controls the supply of power to the power controllable region 300 is also fixed.
Here, in the present embodiment, it is assumed that each switch is fixed to the ON state when ShiftEnable is at a high level. For example, each MOS transistor in FIG. 15 may be an n-type MOS transistor.
In this state, since the voltage is supplied to the power controllable area 300, the scan chains of SIN2 and SIN3 can be operated together with the scan chain of SIN1. That is, as a specific example, since the voltages are supplied to the FFs 508 to 511 of the SIN2 and SIN3, the entire SIN2 and SIN3 can be used in the scan path test together with the SIN1.

  In this situation, a test pattern is supplied to each of the scan chains SIN1, SIN2, and SIN3. That is, each of SIN1, SIN2, and SIN3 forms a shift register in response to the activation of ShiftEnable, and serially inputs a bit string that forms a test pattern for each of SIN1, SIN2, and SIN3. Specifically, each FF forming SIN1, SIN2, and SIN3 shifts a test pattern input serially in response to an edge of the input clock signal to a subsequent FF. By this operation, a test pattern is set in each FF of SIN1 to SIN3. Note that the bit of the test pattern set in the FF 501 in SIN 1 is “1” indicating a high level here. Then, at this time, the FF 501 outputs a high level signal from the terminal Q side. In addition, each of the other FFs of SIN1, SIN2, and SIN3 outputs a signal indicating the logic value of the set test pattern from each output terminal Q. Then, for example, since the FF 506 of the SIN 3 outputs a bit indicated by the test pattern set from the terminal Q, the logic circuit 19 performs an operation in response to the signal output from the FF 506, and the operation result is output to the FF 503 of the SIN 1. Output toward data terminal D. Specifically, at this time, the signal output from the logic circuit 19 has reached the input on the DIN side of the multiplexer 410 in FIG. The same applies to each FF provided in SIN1 to SIN3 and used for testing other logic circuits.

  Next, the activated ShiftEnable is deactivated. For example, the logical value of ShiftEnable is set to a low level. Then, the logical value of the signal output from the OR circuit 241 indicates the logical value of the signal output from the FF 501 of SIN1. As described above, since the bit of the test pattern set in the FF 501 is at a high level, the output of the OR circuit 241 is maintained at a high level without being affected by the deactivation of ShiftEnable. The signal output from the OR circuit 241 reaches the terminal D of FF502A and FF502B which are observation FFs. Specifically, the output signal of the OR circuit 241 reaches the input on the DIN side of the multiplexer shown in FIG. After the output signal of the OR circuit 241 reaches the FFs 502A and FF502B, an edge (for example, a rising edge) of the clock signal is supplied to each FF of SIN1 to SIN3. Then, each FF of SIN1 to SIN3 holds the logical value of the signal that has reached the terminal D (specifically, DIN in FIG. 6) and outputs it from the terminal Q. In particular, FF 502A and FF 502B hold the signal output from OR circuit 241 and output it from terminal Q. The FF 501 holds the control signal CTL and outputs it from the terminal Q. Here, in this example, it is assumed that CTL is at a high level and the FF 501 holds a logic value at a high level and outputs it from the terminal Q. Then, the output of the OR circuit 241 continues to be high level. The CTL may be input from the outside of the semiconductor integrated circuit 100 or may be output from an internal logic circuit.

  Thereafter, ShiftEnable is activated again, and the FFs of SIN1 to SIN3 are connected in series so that a shift register is formed. Then, a clock is supplied to each FF, and data captured by each FF is output from SO1, SO2, and SO3. Data output from SO1 to SON3 is taken into a test apparatus (not shown) and verified.

  Here, the control signal line connecting the OR circuit 241 and the FFs 502A and FF502B, that is, the signal line propagating through the CTL for controlling on / off of each switch (see FIG. 15) provided in the power controllable region 300 is disconnected. If not, the logical value of the signal output from the OR circuit 241 is correctly held in the FF 502A and FF 502B. However, for example, if the signal line on the FF 502A side is disconnected, as described above, a fixed logic value is input to the terminal D of the FF 502A regardless of the logic value of the signal output from the OR circuit 241. Similarly, if the signal line on the FF 502B side is disconnected, a fixed logical value is input to the terminal D of the FF 502B. Therefore, in order to determine whether or not the signal line is disconnected, it is necessary to perform a scan path test again.

  In the above description, the test pattern set in the FF 501 is the bit “1” indicating the high level, and the logical value of the CTL captured in the FF 501 is also the high level. In this case, since the output of the OR circuit 241 continues to be at a high level even after the Shift Enable is deactivated, one switch and the OR circuit that are closest to the OR circuit 241 among the switches in the power shutoff possible region 300 Except for the special case where the control signal line between 241 is disconnected and all the switches are always OFF, in principle, power is continuously supplied to the power shut-off possible region 300. Then, since the FF 508 to FF 511 continue to be driven, a scan path test using the FF 508 to FF 511 can be performed. Specifically, the logical values captured by the FFs 508 to 511 can be directly taken from the SO2 and SO3 into the test apparatus and used for verification. Therefore, the AND gates 242 and 243 receive the same high level signal as the output of the OR circuit 241, and the values captured by the FF 508 and FF 509 and the values captured by the FF 510 and FF 511 are used as they are. 243.

  As described above, in order to determine whether or not the control signal line is disconnected, it is necessary to perform a scan path test again. Normally, in order to perform a test of a logic circuit, a test pattern is set in each FF of the scan chain a plurality of times and a scan path test is performed. Therefore, a signal that propagates the CTL in parallel with the scan path test of the logic circuit. Also do line testing.

  Similar to the above description, first, ShiftEnable is activated. For example, ShiftEnable is set to high level. In FIG. 5, each FF forms a shift register, and scan chains SIN1 to SIN3 are formed. In this state, a test pattern is supplied to each SIN1 to SIN3. Here, in the supply of the test pattern this time, the bit of the test pattern set in the FF 501 is set to the bit “0” indicating the low level. Then, the FF 501 outputs a signal indicating a low level from the terminal Q.

  Similarly to the above description, ShiftEnable is deactivated so that the output of the OR circuit 241 indicates the output signal from the FF 501. At this time, the signal output from the OR circuit 241 indicates a low-level logic value. Then, after the signal output from the OR circuit 241 reaches FF502A and FF502B, the edge of the clock signal is supplied to each FF of SIN1 to SIN3. In response to this clock edge, each FF holds the value of the signal reaching the respective terminal D and outputs it from the respective terminal Q in the same manner as described above. In particular, the observation FF 502A and the observation FF 502B hold the value of the signal output from the OR circuit 241 (unless the control signal line propagating through the CTL is disconnected). The FF 501 holds the logical value of the CTL signal. At this time, the logical value of the CTL signal held in the FF 501 is set to a low level.

  By activating ShiftEnable again, each FF provided in each of SIN1 to SIN3 becomes a shift register, and the held value is output to SO1 to SO3 in response to the clock signal. These output values are taken into the test apparatus and verified.

  Here, the test pattern set in the FF 501 is “0” indicating a low level. If no disconnection occurs in the control signal line propagating through the CTL, the values captured by the FF 502A and the FF 502B are also “0”. However, if the signal line connecting the FF 502A and the OR circuit 241 is disconnected, the value of the signal captured by the FF 502A is the time of the scan path test when “1” indicating a high level is previously set in the FF 501. Will show the same value. Similarly, if the signal line connecting the FF 502B and the OR circuit 241 is disconnected, the value of the signal captured by the FF 502B is a scan path test when “1” indicating a high level is set in the FF 501. The same value as in the case of.

  That is, it is possible to determine whether or not a disconnection has occurred in the control signal that propagates the CTL signal by performing the above-described two scan path tests. In the second scan path test described above, power is not supplied to the FF 508 to FF 511 midway. This is because bit “0” indicating a low level is set in the FF 501 as a test pattern. Therefore, the values captured by the FF 508 to FF 511 in the second scan path test should not be used for verification. Since the supply of power to the FFs 508 to 511 is stopped in response to the deactivation of ShiftEnable after setting the test pattern to the FF508 to FF511, the FF508 to FF511 responds to the subsequent activation of ShiftEnable. This is because the value of the signal output from the terminal Q is an indefinite value. For this reason, the value of the CTL signal captured by the FF 501 is at a low level, and signals output from the AND gate 242 and the AND gate 243 are fixed at a low level. That is, the AND gates 242 and 243 serve as a mask circuit that prevents the data output from the FFs 508 to 511 in the power controllable area 300 from being output to SO2 to SO3.

In the present embodiment, an FF for testing a control signal line that propagates CTL is provided in a scan chain for testing a logic circuit provided in the semiconductor integrated circuit 100. Accordingly, as described above, a test for disconnection of the control signal propagating through the CTL can be performed in parallel with the scan path test of the logic circuit to be tested, so that the efficiency of the test can be improved.
In the first embodiment, the signal value of the control signal line propagating through the CTL needs to be directly output to an external terminal. Use of external terminals for testing leads to an increase in the number of pins, which is not always preferable. However, in the second embodiment, the test result of the control signal line can be output to the outside using the scan chain instead of the external terminal. Thereby, the presence or absence of disconnection of the control signal line can be specified without increasing the number of pins. As a result, it is possible to specify whether a factor such as a malfunction of the circuit or an increase in leakage current is due to disconnection of the control signal line or other factors without increasing the number of pins.

  Note that the observation FFs 501, 502 A, 502 B, and 503 constituting the scan chain for testing the signal line that propagates the CTL need to operate with the power supply VDD unrelated to the operation of the power control switches 310 A and 310 B. For this reason, FIG. 5 illustrates the case where the observation FF is arranged outside the power controllable region 300. However, if the observation FF is wired to operate with the power supply VDD, the observation FF is arranged in the power controllable region 300. You may do it.

  Also, when supplying a test pattern for performing a scan path test, the ShiftEnable signal is activated, and the ShiftEnable signal is input to the power control switches 310A and 310B via the OR circuit 241. Then, the output of the OR circuit 241 is fixed at a high level regardless of the state of the bit string indicated by the test pattern, so that the power supply control switches 310A and 310B can be turned on without fluttering.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
The third embodiment is a configuration for performing separately the test of the state of the signal line that propagates the signal CTL that controls the on / off state of the power control switch and the test of other logic circuits.
Compared to the second embodiment, the third embodiment makes it easier to create a test pattern to be input to the scan chain, reduces the test time, and further automatically generates the test pattern by a tool. There are three advantages: The reason why these advantages are obtained will be described later.

  Hereinafter, how the test is performed in the third embodiment will be described in order with reference to FIGS. 7 and 8. First, a test is performed to determine whether a signal line that propagates the control signal CTL is broken. Referring to FIG. 7, first, ShiftEnable1 is activated. For example, ShiftEnable1 is set to high level. In this embodiment, ShiftEnable1 is input to FF501, FF502A, and FF502B. Also, ShiftEnable2 is inactivated and SW_TEST is activated and is at a high level.

  As ShiftEnable1 becomes high level, the output of the OR circuit 244 becomes high level, and the FF501, FF502A, and FF502B form a shift register and become the scan chain SIN1 as described in the second embodiment. Note that the selector 231 outputs a signal input to SIN1 to the FF 501 when SW_TEST is at a high level. Further, since the output of the OR circuit 245 is also at a high level, the output of the OR circuit 241 is at a high level, and the power controllable area 300 is fixed in a state where power is supplied.

Next, a test pattern is input to SIN1.
The test pattern at this time is created considering only the test pattern input to the FF 501 in order to test the signal line that propagates the control signal CTL. It is not necessary to set a test pattern for the FFs 502A and 502B. After the test pattern is set to FF501, ShiftEnable1 is deactivated, for example, at a low level, as in the second embodiment. Note that the test pattern set in the FF 501 is “1” indicating a high level here. In this embodiment, the test of the logic circuit provided in the power controllable area 300 is not performed in the scan path test using SIN1. The test of the logic circuit is performed at the time of a scan path test using another scan chain SIN2 described later. Therefore, even if the test pattern set in the FF 501 is “1” or “0”, it does not affect the subsequent test as in the second embodiment, but “1” is set in the FF 501 here. Shall be.

After that, ShiftEnable1 is deactivated, and each FF included in SIN1 holds the data reaching the data terminal D and outputs it from the terminal Q as described in detail in the second embodiment. At this time, the FFs 502A and 502B hold the logical value of the signal output from the OR circuit 241 and output it from the terminal Q (if the signal line is not disconnected), as in the second embodiment.
Since the test pattern set in the FF 501 is “1”, the output of the OR circuit 241 remains at the high level when the ShiftEnable1 is deactivated. However, the output of the OR circuit 241 when each FF included in SIN1 holds the data that subsequently reaches the terminal D changes depending on whether the logical value of the CTL signal is high level or low level. However, as described above, in the scan path test using this SIN1, the logic circuit in the power controllable area 300 is not tested, so it will not be discussed here.

  Subsequently, ShiftEnable1 is activated again so that each FF included in SIN1 forms a shift register. A clock is supplied to each FF of SIN1, and the value of the signal held by each FF is output from the terminal SO1. The value output from SO1 is taken into the test apparatus and verified.

  Here, the value of the signal output to SO1 by the FF 502A and FF 502B is the data output by the OR circuit 241 unless the signal line that propagates the control signal CTL is disconnected, but the signal line is disconnected. For example, it is only a fixed logical value caused by disconnection. Therefore, as in the second embodiment, it is necessary to perform the scan path test again.

  In the next scan path test, the test pattern set in the FF 501 may be set to “0” indicating a low level. As a result, the process proceeds in the same manner as described above, and the test result is acquired from SO1. As a result, if the signal value output from the FF 502A to SO1 changes between the first time and the second time, the control signal line connecting the OR circuit 241 and the FF 502A is not disconnected. On the other hand, if the signal value output from FF 502A to SO1 does not change in the first and second times and the logic value is fixed, the control signal line connecting OR circuit 241 and FF 502A is disconnected. The same determination can be made for the signal line connecting the FF 502B and the OR circuit 241.

  From the above, it can be determined whether or not the signal line propagating through the control signal line CTL is disconnected. Therefore, subsequently, the logic circuit provided on the semiconductor integrated circuit is tested. Therefore, in this embodiment, a scan chain SIN2 provided separately from SIN1 is used. In FIG. 7 and FIG. 8, SIN2 is stretched only in the region 200 to which power is always supplied, but is actually stretched also in the power controllable region 300, and in the power controllable region 300 It is also used for testing a logic circuit provided in the circuit.

  Referring to FIG. 8, first, ShiftEnable2 is activated. For example, a high level is set. Then, SW_TEST is deactivated, for example, fixed to a low level. Here, ShiftEnable1 remains inactivated. In response to the activation of ShiftEnable2, FF501 and FF512 to 515 form a shift register, and a scan chain SIN2 is formed. Note that the selector 231 outputs data output from the terminal Q of the FF 513 to the FF 501 in accordance with the deactivation of SW_TEST. Here, in the case of using this SIN2, since the output of the OR circuit 245 becomes high level due to the inactivation of SW_TEST, the output of the OR circuit 241 also becomes high level. That is, the power controllable area 300 is fixed to an ON state in which a voltage is supplied.

  Here, although not shown in FIG. 8, SIN 2 is also extended in the power controllable area 300. In other words, the logic circuit provided in the power controllable area 300 is also tested in parallel using SIN2. This is because the power supply controllable region 300 is fixed in an ON state when SW_TEST is inactivated, so that the voltage supply to each FF constituting the scan chain provided in the power supply controllable region 300 is performed. This is because it is not blocked. That is, in this case, there is no case where the test result output by the FF included in the SIN2 in the power controllable area 300 has an indefinite value as in the second embodiment. Reliable verification can be performed even when the logic circuit in the area and the power controllable area 300 is tested together.

  The subsequent steps are the same as described above. That is, since ShiftEnable2 is activated, a test pattern is set for each FF of SIN2. Then, ShiftEnable2 is deactivated, and data in which each FF of SIN2 reaches the terminal D is captured. Thereafter, ShiftEnable2 is activated again, and the test result of the logic circuit is output from SO2. Then, the output result is verified.

  In the third embodiment, the scan path test for determining the disconnection of the signal line that propagates the control signal CTL and the scan path test for testing the logic circuit are performed separately. As a result, the test pattern can be created separately for the pattern for testing the signal line and the pattern for testing the logic circuit. In the second embodiment, since the disconnection of the signal line and the test of the logic circuit are performed at the same time, it is necessary to generate a complicated test pattern, but the third embodiment is advantageous in this respect.

  In the third embodiment, a test pattern can be created with an automatic generation tool. A tool for creating a test pattern cannot create a test pattern in consideration of the fact that power supply to the power controllable area 300 is stopped. In other words, all the tools generate test patterns on the assumption that the power supply is always on. In the second embodiment, the supply of power to the power controllable region 300 may be stopped halfway depending on the value of the test pattern set in the FF 501 and the value of CTL that determines the value captured in the FF 501 in FIG. there were. In particular, when the CTL is an external input in the second embodiment, it is only necessary to fix it at a high level, which is not a big problem. However, when the signal CTL is output from a predetermined logic circuit as shown in FIGS. Therefore, it is necessary to verify the CTL that is the output of the logic circuit with various test patterns, and there are many cases where the CTL becomes a low level. Then, in the second embodiment as shown in FIG. 5, in the test of the logic circuit that is performed after the test of the signal line that propagates the CTL, the power controllable region 300 is turned off when each FF performs the capture. Occur frequently (note that ShiftEnable is inactive). When trying to create a test pattern for a scan path test in such a situation, the automatic generation tool cannot be used. Therefore, in the second embodiment, the test pattern must be manually created. In that respect, in the third embodiment, when the logic circuit is tested, the power controllable area 300 is always supplied with power. That is, in this case, the test pattern can be created by the automatic generation tool. Therefore, the third embodiment exhibits an excellent effect of greatly shortening the development period compared to the second embodiment.

  Furthermore, the third embodiment exhibits an effect that the test time is shortened as compared with the second embodiment. In the second embodiment, as described above, when the CTL is the output of the logic circuit, the supply of power to the power controllable region 300 is stopped and frequently restarted after the scan path test. was there. When the power supply is stopped during the scan path test and then the power supply is started, each FF of the scan chain reaches the terminal D until the value of the voltage supplied by the power supply stabilizes. The constraint is that you have to wait for the value to be captured. On the other hand, in the third embodiment, the signal line disconnection test and the logic circuit test are performed separately. In the test of the logic circuit, since the power supply is not stopped, the above restriction does not occur. Accordingly, the time required for the scan path test for the logic circuit is shortened.

  Although the third embodiment has been described above, for example, after performing a scan path test of a logic circuit, a scan path test for inspecting whether or not a signal line is disconnected may be performed.

(Fourth embodiment)
Next, a method for designing a semiconductor integrated circuit including the power control switch test circuit described in the second and third embodiments will be described.
First, a conventional design method and its problems will be described.
9 and 11 are diagrams showing a procedure of a conventional design method.
FIG. 9 is a flowchart showing a procedure of a design method when a scan test of the power control switch is not inserted in a semiconductor integrated circuit including the power control switch.
With reference to FIG. 9, a design procedure when a scan test of the power control switch is not inserted in a semiconductor integrated circuit including the power control switch will be described.

First, as layout processing (ST100), circuit connection information is generated (ST101), and a power supply hierarchy is determined (ST102).
Here, in the determination of the power supply hierarchy (ST102), for example, as shown in FIG. 10, the circuit block that is always in the ON region and the circuit block in the power controllable region are separated.

  Subsequently, a scan path is inserted as a DFT process (Design For Testability). Here, since the test of the power control switch is not performed, the scan chain is configured by replacing the flip-flop in the circuit with the scan FF as usual.

  Then, as a layout process (ST300), a floor plan is generated (ST301), and a power control switch is inserted (ST302). Finally, placement and wiring are performed (ST500).

  Thus, in a semiconductor integrated circuit including a power control switch, when a scan test of the power control switch is not inserted, a normal DFT process is performed only once, and a smooth design is performed. However, since a scan test of the power control switch is not inserted, it is difficult to identify the cause if the product is defective.

Next, FIG. 11 is a diagram showing a design procedure when a scan test of the power control switch is inserted in a semiconductor integrated circuit including the power control switch.
In this case, the layout process (ST100), scan insertion (ST200), and layout process (ST300) are the same as the steps described in FIG.
Here, in order to insert the scan path of the power control switch, after the power control switch is inserted (ST302), the DFT processing (ST400) is performed again. That is, a switch observation FF is inserted (ST401), and a scan path including the switch observation FF is inserted (ST402). Finally, placement and wiring are performed as layout processing (ST500).

According to this procedure, the power supply control switch can be scanned and inserted.
However, since the DFT process is performed twice, the number of data exchanges between the DFT process and the layout process increases, and the labor and time required for circuit design become very large.
The layout process is performed while correcting the floor plan several times so that the final placement / wiring is optimized. Then, every time the floor plan is corrected, the DFT processing (ST400) for the power control switch must be repeated. Therefore, a dramatic increase in the number of steps is required to perform scan insertion for the power control switch.

In contrast, a fourth embodiment as a circuit design method of the present invention will be described.
FIG. 12 is a diagram showing a design procedure when a scan test of the power control switch is inserted in a semiconductor integrated circuit including the power control switch.
In FIG. 12, after determining the power supply hierarchy as the layout process (ST100), before performing the scan insertion (ST200) by the DFT process, an output node is added to the power controllable area (ST111), and further for switch observation An FF is inserted to connect to the output node. That is, as shown in FIG. 13, output nodes 330A and 330B are added to the power controllable area 300, and switch observation FFs 502A and 502B are inserted to connect to the output nodes 330A and 330B. Then, scan insertion (ST200) is performed as normal DFT processing.

  As layout processing (ST300), after performing a floor plan (ST301) and power supply control switch insertion (ST302), the final stage of the power supply control switch is connected to the output node (ST310). Then, it becomes a circuit which can test the power supply control switch. Finally, placement and wiring are performed (ST500).

  By adopting such a procedure, the DFT process (ST200) can be performed only once. Since the output node and the switch observation FF are inserted before the DFT processing (ST200), the DFT processing (ST200) can be performed almost the same as the normal scan insertion, and the circuit design can be facilitated. .

  In the design method according to the fourth embodiment, it is needless to say that a computer having a CPU and a memory can execute a layout program for a semiconductor integrated circuit, and the above processes can be executed automatically.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit, 11 ... Always ON area | region, 12 ... Power supply controllable area | region, 13A, 13B ... Power supply control switch, 14 ... Semiconductor switch, 15 ... Buffer, 16 ... Control signal line, 17 ... Switch cell, 18, 19 ... logic circuit, 100 ... semiconductor integrated circuit, 200 ... always ON region, 211, 212, 213 ... logic gate, 230, 231 ... multiplexer, 241 ... OR circuit, 242, 243 ... logic gate, 244, 245 ... OR circuit, 300 ... Power controllable area, 310A, 310B ... Power control switch, 320 ... Power control signal line, 330A, 330B ... Output node, 340A-340F ... Output terminal, 350 ... Scan-out terminal, 400 ... Flip-flop, 410 ... Multiplexer , 501 to 515 ... FF for observation.

Claims (23)

A first power line;
A second power line;
A first switch connected between the first power supply line and the second power supply line and connected to a predetermined circuit;
A second switch connected between the first power supply line and the second power supply line and connected to a predetermined circuit;
A first control signal line connected to the first switch;
A second control signal line connected to the second switch;
Logic gates to which control signals from the first control signal line and the second control signal line are respectively input;
A terminal connected to the logic gate and outputting the output of the logic gate to the outside;
The semiconductor integrated circuit, wherein the first control signal line extends in a direction intersecting with the first power supply line. The semiconductor integrated circuit according to claim 1, wherein the first control signal line extends in a direction intersecting with the second power supply line. The semiconductor integrated circuit according to claim 1, wherein the first power supply line and the second power supply line extend substantially in parallel. A ground line,
The semiconductor integrated circuit according to claim 1, wherein the second power supply line extends between the first power supply line and the ground line in a plan view. The semiconductor integrated circuit according to claim 4, wherein the ground line extends substantially parallel to the first and second power supply lines. The semiconductor integrated circuit according to claim 1, wherein the second control signal line extends in a direction intersecting with the first power supply line. The semiconductor integrated circuit according to claim 6, wherein the second control signal line extends in a direction intersecting with the second power supply line. The semiconductor integrated circuit according to claim 1, wherein the first control signal line and the second control signal line extend substantially in parallel. A third power supply line and another ground line, and the power supply line does not extend between the third power supply line and the other ground line in plan view. The semiconductor integrated circuit according to claim 1. A plurality of the first switches are provided,
The semiconductor integrated circuit according to claim 1, wherein a plurality of the second switches are provided. The semiconductor integrated circuit according to claim 1, wherein the logic gate is an AND gate, an OR gate, or an EX-OR gate. A first power line;
A second power line;
A switch connected between the first power supply line and the second power supply line and connected to a predetermined circuit;
A control signal line connected to the switch;
A scan chain to which the control signal line is connected;
An OR operation unit connected to the control signal line;
And a terminal for outputting the output of the scan chain to the outside. The semiconductor integrated circuit according to claim 12, wherein the control signal line extends in a direction intersecting with the first power supply line. The semiconductor integrated circuit according to claim 13, wherein the control signal line extends in a direction intersecting with the second power supply line. The semiconductor integrated circuit according to claim 12, wherein the first power supply line and the second power supply line extend substantially in parallel. A ground line,
The semiconductor integrated circuit according to claim 12, wherein the second power supply line extends between the first power supply line and the ground line. The semiconductor integrated circuit according to claim 16, wherein the ground line extends substantially parallel to the first and second power supply lines. Connected between the first power supply line and the second power supply line, connected to a predetermined circuit, and a switch different from the switch;
The semiconductor integrated circuit according to claim 12, further comprising a control signal line connected to the another switch and different from the control signal line. The semiconductor integrated circuit according to claim 18, wherein the another control signal line is connected to the scan chain and the OR operation unit. The semiconductor integrated circuit according to claim 18, wherein the control signal line and the another control signal line extend substantially in parallel. The semiconductor integrated circuit according to claim 12, wherein a scan chain different from the scan chain is provided in a direction crossing the control signal line. An AND operation unit,
The semiconductor integrated circuit according to claim 21, wherein an input of the logical sum operation unit and an input of the logical product operation unit are connected. The semiconductor integrated circuit according to claim 12, wherein a plurality of the switches are provided.

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