JP5499744B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a JFET (junction field effect transistor) and a method for manufacturing the same, and is preferably applied to a wide band gap semiconductor, particularly a SiC semiconductor device using silicon carbide (hereinafter referred to as SiC).

Conventionally, Patent Document 1 proposes a JFET composed of SiC suitable for high frequency and high breakdown voltage. FIG. 15 is a cross-sectional view of this JFET. As shown in this figure, a p ⁻ -type buffer layer J2, an n ⁻ -type channel layer J3 and an n ⁺ -type layer J4 are sequentially stacked on a substrate J1 made of SiC, and then the surface of the n ⁺ -type layer J4. To the n ⁻ -type channel layer J3 is formed by etching. Then, the p ⁺ type gate region J7 is formed in the recess J5 via the p ⁻ type layer J6, and the source electrode J9 and the drain electrode J10 are interposed via the metal layer J8 so as to be separated from the p ⁺ type gate region J7. As a result, the JFET disclosed in Patent Document 1 is configured.

US Pat. No. 7,560,325

In the normally-on JFET shown in Patent Document 1, as the concentration varies by p ⁺ -type gate region J7 is contacted directly n ⁺ -type layer J4 is not a PN junction becomes steep, p ⁺ -type gate region J7 Is surrounded by a p ⁻ type layer J6. This increases the capacitance between the p ⁺ -type gate region J7 and the n ⁺ -type layer J4, that is, between the gate and the source and between the gate and the drain. Further, the n ⁻ type channel layer J3 must be designed to be pinched off by a depletion layer extending from the lightly doped p ⁻ type layer J6, and a high voltage is applied to the p ⁺ type gate region J7 when the JFET is turned off. There is also a problem that must be done.

  In view of the above points, the present invention includes a JFET that can reduce the capacitance between the gate and the source and between the gate and the drain, and can suppress the gate applied voltage required to turn on the JFET from becoming a high voltage. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

  In order to achieve the above object, according to the first aspect of the present invention, the source region (3a) and the source region (3a) are located at a portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b). A gate region (4) of the second conductivity type that is disposed apart from the drain region (3b) and that is wider at a portion that is separated from the channel layer (2) than a portion that is in contact with the channel layer (2). It is characterized by being a JFET.

  As described above, the widened portion of the gate region (4) is separated from the surface of the channel layer (2). For this reason, the capacitance between the gate and the source and between the gate and the drain can be reduced.

  Further, since the gate region (4) is formed directly on the surface of the channel layer (2), the gate region (4) is further provided between the source region (3a) or drain region (3b) and the gate region (4). A lower concentration impurity layer is not required. Therefore, the width of the depletion layer extending into the channel layer (2) can be controlled by the high concentration gate region (4) in direct contact with the channel layer (2). Therefore, it can suppress that a gate applied voltage becomes a high voltage.

The semiconductor device having such a structure, preferably when applied to the case where wide-bandgap semiconductor is used, in particular, it is preferable when applied to the case of using SiC as a wide-bandgap semiconductor.

For example, when a SiC substrate (1) is used as the substrate, the gate region (4) is composed of SiC having the same crystal structure as the SiC substrate (1) as described in claims 1 and 2 , or a portion in contact with the channel layer (2) as described in claim 3 is constituted by SiC having the same crystal structure as SiC substrate (1), at least a portion of the part which is wider is the SiC substrate (1) It is composed of SiC having a different crystal structure.

As described in claim 1, when the main surface as a SiC substrate (1) off-substrate is used having an off-angle of 1 ° or less with respect to Si plane or C plane, Gate region (4) Can be made of SiC having the same crystal structure as the SiC substrate (1). In this case, a (0001) facet may be formed on the surface of the widened portion of the gate region (4).

Further, as described in claim 2, the main surface as a SiC substrate (1) in each case the on board a surface used, Gate region (4) of the same crystal structure as SiC substrate (1) It can be made of SiC. In this case, the gate region (4) has a flat surface with a surface.

On the other hand, as described in claim 4, when the main surface as a SiC substrate (1) off-substrate is used having an off angle of greater than 1 ° from Si plane or C plane, a gate region (4) (0001) facets are formed on the surface of the portion made of SiC having the same crystal structure as the SiC substrate (1), and the portion made of SiC having a different crystal structure from the SiC substrate (1) is , 3C-SiC formed on the surface of the (0001) facet.

Further, as described in claim 5, when an on-substrate whose main surface is an a-plane is used as the SiC substrate (1), a vertical direction from a portion in contact with the channel layer (2) in the gate region (4) Then, the crystal structure of the SiC substrate (1) is taken over, and the widened portion of the gate region (4) can be 3C-SiC.

The invention described in claims 6 to 10 is an invention relating to a method of manufacturing a semiconductor device described in claims 1 to 5 .

Specifically, in the invention described in claim 6 , a step of disposing a carbon mask (11) in which a region where a gate region (4) is to be formed is opened on the surface of the channel layer (2), and a carbon mask (11 ) As a mask on the channel layer (2), the step of epitaxially growing the gate region (4) so as to grow laterally up to the carbon mask (11), the carbon mask (11) is removed, and the gate region (4 And a step of separating the laterally grown portion from the surface of the channel layer (2).

  Thus, the gate region (4) can be formed by selective epitaxial growth by using the carbon mask (11). Then, by removing the carbon mask (11), the laterally grown portion of the gate region (4) can be separated from the surface of the channel layer (2).

Further, as described in claim 6 , by using a SiC substrate (1) whose main surface is an off substrate having an off angle of 1 ° or less with respect to the Si surface or the C surface, the gate region (4 ), A gate region (4) in which a (0001) facet is formed on the surface of a portion wider than a portion in contact with the channel layer (2) by lateral growth can be formed. Thereby, the semiconductor device according to claim 1 can be manufactured.

Further, as described in claim 7 , by using a SiC substrate (1) made of an off substrate having a main surface having an off angle exceeding 1 ° with respect to the Si surface or the C surface, the gate region (4 ) Is formed on the surface of the portion wider than the portion in contact with the channel layer (2), and 3C-SiC is formed on the surface of the (0001) facet by lateral growth. A grown gate region (4) can be formed. Thereby, the semiconductor device according to claim 4 can be manufactured.

Furthermore, as described in claim 8 , in the step of forming the gate region (4) by using the SiC substrate (1) whose main surface is an on-substrate whose main surface does not have an a-plane off angle, A gate region (4) in which the portion that is wider than the portion in contact with the channel layer (2) by the direction growth becomes 3C-SiC can be formed. Thereby, the semiconductor device according to claim 5 can be manufactured.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 1st Embodiment of this invention. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device provided with JFET shown in FIG. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device including the JFET following FIG. 2. FIG. 4 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device including the JFET following FIG. 3. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 2nd Embodiment of this invention. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 3rd Embodiment of this invention. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 4th Embodiment of this invention. It is sectional drawing which showed a mode that 3C-SiC was grown on the surface of a (0001) facet. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 5th Embodiment of this invention. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 6th Embodiment of this invention. FIG. 11 is a cross-sectional view of the SiC semiconductor device shown in FIG. 10 when a p ⁻ -type buffer layer 8 is formed. FIG. 11 is a cross-sectional view of the SiC semiconductor device shown in FIG. 10 when the p ⁺ -type gate region 4 has a different crystal structure. It is sectional drawing which showed a mode that 3C-SiC was grown in the horizontal direction of 4H-SiC. It is sectional drawing for 1 cell of the SiC semiconductor device provided with JFET concerning 7th Embodiment of this invention. It is sectional drawing of the SiC semiconductor device provided with the conventional JFET.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of one cell of a SiC semiconductor device including a JFET according to the present embodiment. Hereinafter, the structure of the JFET provided in the SiC semiconductor device will be described with reference to FIG.

The SiC semiconductor device shown in FIG. 1 is formed using a semi-insulating SiC substrate 1. Semi-insulating means a non-doped semiconductor material or the like that is composed of a semiconductor material and has a resistivity (or conductivity) close to that of the insulating material. For example, in this embodiment, the semi-insulating SiC substrate 1 is made of 4H—SiC whose main surface has an off angle of 1 ° or less with respect to the (0001) Si plane or the (000-1) C plane. A substrate having a resistivity of 1 × 10 ¹⁰ to 1 × 10 ¹¹ Ω · cm and a thickness of 50 to 400 μm (for example, 350 μm) is used.

On the surface of SiC substrate 1, n ⁻ type channel layer 2 is formed. The n ⁻ type channel layer 2 is a place where a channel region is formed. For example, the n type impurity concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ (for example, 1 × 10 ¹⁷ cm ⁻³ ), and the thickness is 0. .1 to 1.0 μm (for example, 0.2 μm).

An n ⁺ type layer 3 is formed on the surface layer portion of the n ⁻ type channel layer 2. The n ⁺ -type layer 3 is separated on the left and right sides of the page for each cell, and the left side of the page constitutes the n ⁺ -type source region 3a and the right side of the page constitutes the n ⁺ -type drain region 3b. These n ⁺ -type source region 3a and n ⁺ -type drain region 3b have an n-type impurity concentration of 5 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ⁻³ ) and a thickness of 0.1 It is 1.0 μm (for example, 0.2 μm).

the n ^- where positioned between the n ⁺ -type source region 3a and the n ⁺ -type drain region 3b of the type channel layer 2 of the surface, n ^- shallow recess 2a is formed than type channel layer 2. Since a portion deeper than the recess 2a in the n ⁻ -type channel layer 2 functions as a channel region, the channel depth is set by the depth D _G of the recess 2a. For example, the depth D _G of the recess 2a is a 0.1 [mu] m.

A p ⁺ -type gate region 4 is formed on the surface of the n ⁻ -type channel layer 2 in the recess 2 a. The p ⁺ type gate region 4 is made wider than the portion formed in the recess 2a at a predetermined distance, for example, 0.5 to 1.0 μm away from the surface of the n ⁻ type channel layer 2. Basically, it is T-shaped. SiC is not disposed between the wide portion of the T ⁺ -shaped p ⁺ -type gate region 4 and the surface of the n ⁻ -type channel layer 2. The p ⁺ -type gate region 4 has a p-type impurity concentration of 5 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ (for example, 1 × 10 ¹⁹ cm ⁻³ ) and a thickness of 0.1 to 1.0 μm (for example, 0. 4 μm). The surface of p ⁺ -type gate region 4 is preferably basically a flat surface. However, when the main surface of SiC substrate 1 has the above plane orientation, one end of the surface of p ⁺ -type gate region 4 is formed. Facets may be formed.

The formation position and dimensions of the p ⁺ -type gate region 4 are set based on the following matters. Specifically, the length of the portion of the p ⁺ -type gate region 4 that is in contact with the n ⁻ -type channel layer 2, that is, the channel length L _ch defines the cutoff frequency of the JFET. Can be high. For this reason, in this embodiment, it is 0.1-0.5 micrometer (for example, 0.4 micrometer). The length L _SG between the gate and the source is related to the current value of the JFET, and it is necessary to shorten the length L _SG in order to allow a larger current to flow. For this reason, in this embodiment, it is 0.1-0.5 micrometer, for example. Furthermore, the gate-drain length L _GD is related to the breakdown voltage of the JFET, and a larger one can increase the breakdown voltage. For this reason, in this embodiment, it is 0.5-1.0 micrometer, for example.

A gate electrode 5 is formed on the surface of the p ⁺ -type gate region 4. The gate electrode 5 is configured by a laminated structure of a plurality of metal layers. For example, the first layer 5 a is configured by a Ni-based metal layer such as NiSi ₂ that is brought into ohmic contact with the p ⁺ -type gate region 4. The second layer 5b composed of a Ti-based metal layer, and further, although not shown, are configured by sequentially forming an Au layer in consideration of bondability with an Al wiring or a wire for electrical connection with the outside. Is done. The first layer 5a is 0.1 to 0.5 μm (for example, 0.2 μm), the second layer 5b is 0.1 to 0.5 μm (for example, 0.1 μm), and the Al wiring or Au layer is 1.0 ˜5.0 μm (for example, 3.0 μm).

A source electrode 6 is formed on the n ⁺ type source region 3a, and a drain electrode 7 is formed on the n ⁺ type drain region 3b. The source electrode 6 and the drain electrode 7 are also made of the same material as the gate electrode 5, for example, like the Ni-based metal layers 6 a and 7 a and the Ti-based metal layers 6 b and 7 b.

  Such a structure constitutes a JFET. Although not shown, the electrodes are electrically separated by an interlayer insulating film, a protective film, etc. composed of a silicon oxide film, a silicon nitride film, etc., so that the SiC semiconductor device of this embodiment is configured. Yes.

When the gate voltage is not applied to the gate electrode 5, the JFET provided in the SiC semiconductor device configured as described above has a depletion layer extending from the p ⁺ type gate region 4 to the n ⁻ type channel layer 2 side ( The n ⁻ type channel layer 2 is pinched off by a depletion layer extending from the SiC substrate 1 to the n ⁻ type channel layer 2 side. When a gate voltage is applied to the gate electrode 5 from this state, the depletion layer extending from the p ⁺ type gate region 4 is reduced. Thereby, a channel region is formed in the n ⁻ -type channel layer 2, and a current flows between the source electrode 6 and the drain electrode 7 through the channel region. As described above, the JFET of this embodiment can function as a normally-off element.

In such a JFET, the surface of the p ⁺ -type gate region 4 is made wide so that the gate electrode 5 can be easily arranged, but the portion in contact with the n ⁻ -type channel layer 2 is made narrow. For this reason, the following effects can be acquired.

(1) The widened portion of the p ⁺ -type gate region 4 is separated from the surface of the n ⁻ -type channel layer 2. For this reason, the capacitance between the gate and the source and between the gate and the drain can be reduced.

Further, the p ⁺ -type gate region 4 directly n ^- because it forms on the surface of the mold channel layer 2, than further p ⁺ -type gate region 4 between the n ⁺ -type layer 3 and the p ⁺ -type gate region 4 A low concentration p ^- type layer is not required. Thus, n ^- by type channel layer 2 high-concentration p ⁺ -type gate region 4 which is in direct contact with the, n ^- can be controlled depletion layer width extending type channel layer 2. Therefore, compared to the case where a p ⁻ type layer is further provided between the n ⁺ type layer 3 and the p ⁺ type gate region 4, it is possible to suppress the gate applied voltage from becoming a high voltage. In addition, a JFET capable of high-speed switching can be obtained, and a SiC semiconductor device suitable for higher frequencies can be obtained.

(2) As described above, the channel length L _ch defines the cutoff frequency of the JFET. The shorter the channel length L _ch , the higher the cutoff frequency. The length L _SG between the gate and the source is related to the current value of the JFET, and it is necessary to shorten the length L _SG in order to allow a larger current to flow. Furthermore, the gate-drain length L _GD is related to the breakdown voltage of the JFET, and a larger one can increase the breakdown voltage. Therefore, it is advantageous to make the portion of the p ⁺ -type gate region 4 in contact with the n ⁻ -type channel layer 2 as narrow as possible in order to realize a high cut-off frequency, a large current, and a high breakdown voltage.

However, if the p ⁺ type gate region 4 is simply narrowed, it becomes difficult to dispose the gate electrode 5 on the surface of the p ⁺ type gate region 4. Therefore, by making the surface of the p ⁺ -type gate region 4 wide and narrowing the portion in contact with the n ⁻ -type channel layer 2, the arrangement of the gate electrode 5 can be facilitated, and a high cut-off frequency, large It becomes possible to realize current and high breakdown voltage.

(3) n ^- a recess 2a of the depth D _G relative to the mold channel layer 2, are arranged p ⁺ -type gate region 4 within the recess 2a. For this reason, the depletion layer spreads not only from the bottom surface of the recess 2a but also from the side surface, and the depletion layer can be expanded more widely than in the case where the recess 2a is not formed. Therefore, when the JFET is turned off, the n ⁻ -type channel layer 2 can be pinched off in a wider range, and the breakdown voltage can be further improved.

  (4) By configuring the SiC substrate 1 with a semi-insulating material, it is possible to absorb radio waves generated during the operation of the JFET, so that a SiC semiconductor device suitable for higher frequencies can be obtained.

  Next, a method for manufacturing an SiC semiconductor device including a JFET having such a configuration will be described. 2 to 4 are cross-sectional views showing manufacturing steps of the SiC semiconductor device including the JFET shown in FIG. With reference to these drawings, a method of manufacturing a semiconductor device including the JFET shown in FIG. 2 will be described.

First, as shown in FIG. 2 (a), the semi-insulating SiC substrate 1 is composed of an off substrate whose main surface has an off angle of 1 ° or less with respect to the (0001) Si surface or the (000-1) C surface. Prepare. 2B, on the main surface of the SiC substrate 1, for example, the n-type impurity concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ (for example, 1 × 10 ¹⁷ cm ⁻³ ). The n ⁻ type channel layer 2 having a thickness of 0.1 to 1.0 μm (for example, 0.2 μm) is epitaxially grown.

In the step shown in FIG. 2C, after a mask made of LTO or the like (not shown) is disposed on the surface of the n ⁻ type channel layer 2, the mask is patterned to form the n ⁺ type source region 3a and the n ⁺ type drain. A region where the region 3b is to be formed is opened. Then, an n-type impurity is ion-implanted, the n-type impurity concentration is 5 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ⁻³ ), and the thickness is 0.1 to 1.0 μm (for example, 0). N ⁺ -type source region 3a and n ⁺ -type drain region 3b to be 4 μm). Thereafter, the mask is removed.

In the step shown in FIG. 2D, a resist 10 is formed on the surfaces of the n ⁻ type channel layer 2, the n ⁺ type source region 3a, and the n ⁺ type drain region 3b. As the resist 10, an organic solvent in which the remaining material is carbonized when the organic substance is evaporated can be used. For example, a positive organic solvent such as a resist for i-line photolithography, a resist for deep-UV lithography. A resist for ArF lithography or a resist for electron beam lithography can be used. In the step shown in FIG. 3A, the carbon mask 11 is formed by carbonizing the resist 10 by, for example, heat treatment at 750 degrees in an argon (Ar) atmosphere.

In the step shown in FIG. 3B, an etching mask 12 composed of a silicon oxide film or the like is disposed on the surface of the carbon mask 11. In the step shown in FIG. 3C, a patterning resist 13 is formed on the surface of the etching mask 12. Then, the resist 13 is patterned by photolithography, and the resist 13 is opened in a region where the recess 2a is to be formed. Thereafter, in the step shown in FIG. 3D, after patterning the etching mask 12 with BHF or the like using the resist 13, the resist 13 is removed and then the carbon mask is used with O ₂ plasma or the like using the etching mask 12 as a mask. 11 is patterned.

In the step shown in FIG. 4A, the recess 2a is formed by partially etching the surface of the n ⁻ -type channel layer 2 with CF ₄ plasma or the like using the etching mask 12 and the carbon mask 11 as a mask.

In the step shown in FIG. 4B, the p-type impurity concentration is 5 × 10 ^{18 to} 5 × in the recess 2 a by selective epitaxial growth by removing the etching mask 12 and then covering the SiC surface with the carbon mask 11. A p ⁺ -type gate region 4 having a thickness of 10 ¹⁹ cm ⁻³ (for example, 1 × 10 ¹⁹ cm ⁻³ ) and a thickness of 0.1 to 1.0 μm (for example, 0.4 μm) is formed. At this time, the p ⁺ -type gate region 4 is formed in the recess 2a, but is also formed on the surface side of the carbon mask 11 by continuously performing epitaxial growth.

Incidentally, p ⁺ -type gate region 4, since it is formed by epitaxial growth with respect to the SiC substrate 1 composed of a off-substrate having an off angle with respect to (0001) Si plane or (000-1) C plane, p ⁺ A facet of (0001) plane is partially formed on the surface of the mold gate region 4, and a part of the surface may not be a flat surface. The surface of the p ⁺ -type gate region 4 is basically preferably a flat surface in order to make it easier to dispose the gate electrode 5 thereon, but the main surface of the SiC substrate 1 has the above plane orientation. In some cases, facets may be formed at one end of the surface of the p ⁺ -type gate region 4. In this case, compared to the case where the entire surface of the p ⁺ -type gate region 4 is a flat surface, there is a possibility that the gate electrode 5 may be slightly disposed, but the surface of the p ⁺ -type gate region 4 is widened. Therefore, the gate electrode 5 can be formed without any particular problem.

In the step shown in FIG. 4C, the carbon mask 11 is removed. Thus, also becomes the carbon mask 11 is removed in the lower portion which is wider among the p ⁺ -type gate region 4, p ⁺ -type gate region 4 is a T-shape. Thereafter, in the step shown in FIG. 4D, a metal mask or a silicon oxide film is not shown so as to cover a region other than the regions where the gate electrode 5, the source electrode 6 and the drain electrode 7 are to be formed. After disposing the mask, the Ni-based metal layer constituting the first layers 5a, 6a and 7a and the Ti-based metal constituting the second layers 5b, 6b and 7b of the gate electrode 5, the source electrode 6 and the drain electrode 7 Deposit layers. Then, by removing the mask, the first layers 5a, 6a, 7a and the second layers 5a, 6b, 7b are left only in regions where the gate electrode 5, the source electrode 6, and the drain electrode 7 are to be formed by lift-off. Further, by performing heat treatment as necessary, the first layers 5a, 6a and 7a of the gate electrode 5, the source electrode 6 and the drain electrode 7 can be silicided and NiSi ₂ or the like can be used to reduce the resistance. Thereafter, by forming an interlayer insulating film, a protective film, etc. (not shown), the SiC semiconductor device including the JFET shown in FIG. 1 can be manufactured.

(Second Embodiment)
A second embodiment of the present invention will be described. The SiC semiconductor device according to the present embodiment is obtained by forming a p ⁻ -type buffer layer with respect to the first embodiment, and is otherwise the same as the first embodiment. Therefore, only the portions different from the first embodiment are described. explain.

FIG. 5 is a cross-sectional view of the SiC semiconductor device including the JFET according to the present embodiment. As shown in this figure, in this embodiment, a p ⁻ type buffer layer 8 having a lower impurity concentration than the p ⁺ type gate region 4 is formed on the surface of the SiC substrate 1. An n-type channel layer 2 is formed on the surface of the p ⁻ -type buffer layer 8. The p ⁻ type buffer layer 8 is provided in order to obtain a higher breakdown voltage, and the p type impurity concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ (for example, 1 × 10 ¹⁶ cm ⁻³ ), The thickness is 0.2 to 2.0 μm (for example, 0.4 μm). The p ⁻ type buffer layer 8 is provided with a p ⁺ type contact region 8a having a high impurity concentration. A recess 9 is formed in the lower portion of the source electrode 6 so as to penetrate the n ⁺ type source region 3a and expose the p ⁺ type contact region 8a, and the source electrode 6 is buried in the recess 9 so that p ^The p ⁻ -type buffer layer 8 is connected to the source electrode 6 through the ⁺ -type contact region 8a and is fixed to the ground potential.

Even if it is set as such a structure, the effect similar to 1st Embodiment can be acquired fundamentally. In addition, since the p ⁻ -type buffer layer 8 is formed with respect to the first embodiment, it is possible to obtain an effect that the breakdown voltage is higher than that of the first embodiment. Furthermore, since the p ⁻ -type buffer layer 8 is provided, the p ⁻ -type buffer layer 8 can also absorb radio waves generated when the JFET is operated, and a SiC semiconductor device suitable for higher frequencies can be obtained. Further, when the p ⁻ -type buffer layer 8 is provided, the SiC substrate 1 can be n-type or p-type, so that the SiC substrate 1 can be prepared more easily.

In addition, the SiC semiconductor device having such a structure can be basically manufactured by the same manufacturing method as the SiC semiconductor device of the first embodiment. However, unlike the first embodiment, the structure is provided with the p ⁻ -type buffer layer 8. Therefore, the step of forming the p ⁻ -type buffer layer 8 on the surface of the SiC substrate 1 and the p ⁺ -type contact region 8 a Are formed by ion implantation, and an etching process for forming the recess 9 in the n ⁻ -type channel layer 2 is performed before the resist 10 is formed.

(Third embodiment)
A third embodiment of the present invention will be described. The SiC semiconductor device of this embodiment is obtained by forming the p ⁺ -type gate region 4 without forming the recess 2a as compared with the first embodiment, and is otherwise the same as the first embodiment. Only parts different from the first embodiment will be described.

FIG. 6 is a cross-sectional view of the SiC semiconductor device including the JFET according to the present embodiment. As shown in this figure, in this embodiment, the p ⁺ type gate region 4 is formed directly on the outermost surface of the n ⁻ type channel layer 2. Even with such a structure, the same effect as in the first embodiment can be obtained. However, since the recess 2a is not formed, a portion extending from the side surface of the recess 2a in the depletion layer extending from the p ⁺ -type gate region 4 is eliminated as compared with the first embodiment. For this reason, the spread of the depletion layer is somewhat narrower than that of the first embodiment in which the concave portion 2a is formed, and it can be said that the structure of the first embodiment is more advantageous in consideration of the improvement of breakdown voltage.

  Such a SiC semiconductor device can also be basically manufactured by the same manufacturing method as the SiC semiconductor device of the first embodiment. However, unlike the first embodiment, it is not necessary to form the recess 2a, so that it is not necessary to arrange the etching mask 12 on the carbon mask 11, and the recess 2a using the etching mask 12 is not required. It is not necessary to perform an etching process for formation.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The SiC semiconductor device according to the present embodiment is obtained by changing the off-angle of the SiC substrate 1 with respect to the first embodiment, and is otherwise the same as the first embodiment. Only explained.

FIG. 7 is a cross-sectional view of the SiC semiconductor device including the JFET according to the present embodiment. In the present embodiment, the off-angle of the SiC substrate 1 is larger than 1 °, for example, 4 ° or 8 °. Then, by constructing a JFET using such a SiC substrate 1, the p ⁺ -type gate region 4 is composed of 4H—SiC and 3C—SiC, as shown in FIG.

When the off-angle of the SiC substrate 1 is increased, 3C—SiC can be grown on the surface of the (0001) facet depending on the epitaxial growth conditions when the p ⁺ -type gate region 4 is formed. FIG. 8 is an enlarged cross-sectional view showing this state. As shown in this figure, an n ⁻ type channel layer 2 in which the crystallinity of the SiC substrate 1 is inherited is formed on the surface of the SiC substrate 1 made of 4H—SiC off-substrate, and the n ⁻ type channel layer 2 A p ⁺ -type gate region 4 is formed on the surface. At this time, due to the anisotropy of the lateral growth and the influence of step flow growth, the p ⁺ -type gate region 4 is formed not by a circular pattern but by a hexagonal pattern biased in the off direction, and a (0001) facet is formed. Since the off angle is large, 3C-SiC can be formed on the (0001) facet.

Even with such a structure, the same effect as in the first embodiment can be obtained. Further, by forming 3C—SiC on the (0001) facet as in this embodiment, the entire surface of the p ⁺ -type gate region 4 can be made closer to a flat surface. For this reason, the gate electrode 5 formed on the surface of the p ⁺ -type gate region 4 can be more easily formed. Such a SiC semiconductor device can also be manufactured by the same manufacturing method as that of the SiC semiconductor device of the first embodiment, except that the SiC substrate 1 having an off angle of 1 ° or more is used.

If the PN junction is composed of 4H—SiC and 3C—SiC having different crystal structures, it may cause leakage current. However, even if the crystal structure changes in the same p ⁺ -type gate region 4, It's hard to be a cause and it doesn't matter much. Conversely, in the case of 3C—SiC, the impurity doping level during epitaxial growth can be increased compared to 4H—SiC or the like, so that the internal resistance of the p ⁺ -type gate region 4 can be reduced.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment has a structure in which elements operating in the D mode and the E mode are combined by the JFET structure shown in the first embodiment and the third embodiment. Since it is the same as that of 3rd Embodiment, only a different part from 1st, 3rd Embodiment is demonstrated.

  FIG. 9 is a cross-sectional view of a SiC semiconductor device including a JFET according to the present embodiment. As shown in this figure, in the SiC semiconductor device of the present embodiment, different JFET structures are formed in the same substrate, one of which (right side of the drawing) is the JFET structure of the first embodiment, and the other (left side of the drawing). Is the JFET structure of the third embodiment.

  In the SiC semiconductor device configured as described above, the JFET on the left side of the paper operates as a D-mode (normally on type) element, and the JFET on the right side of the paper operates as an E-mode (normally off type) element.

Specifically, in the JFET operating as the D mode, even when no gate voltage is applied to the gate electrode 5, the depletion layer (and the n ⁻ type channel layer 2 side) extends from the p ⁺ type gate region 4 to the n ⁻ type channel layer 2 side. The n ⁻ type channel layer 2 is not completely pinched off by the depletion layer extending from the SiC substrate 1 to the n ⁻ type channel layer 2 side, and a channel region is formed. Therefore, current flows between the source electrode 6 and the drain electrode 7 through the channel region when no gate voltage is applied to the gate electrode 5. When a negative gate voltage is applied to the gate electrode 5, the depletion layer is increased in elongation. As a result, the channel region in the n ⁻ -type channel layer 2 is eliminated, and no current flows between the source electrode 6 and the drain electrode 7. Thus, the D-mode JFET functions as a normally-on element.

On the other hand, in the JFET operating as the E mode, when no gate voltage is applied to the gate electrode 5, a depletion layer (and n from the SiC substrate 1 to the n ⁻ type channel layer 2 side) extends from the p ⁺ type gate region 4 to the n ⁻ type channel layer 2 side. ^The n ⁻ type channel layer 2 is completely pinched off by the depletion layer extending to the ⁻ type channel layer 2 side. When a positive gate voltage is applied to the gate electrode 5 from this state, the depletion layer extending from the p ⁺ type gate region 4 is reduced. Thereby, a channel region is formed in the n ⁻ -type channel layer 2, and a current flows between the source electrode 6 and the drain electrode 7 through the channel region. As described above, the E-mode JFET functions as a normally-off type element.

  In this manner, a SiC semiconductor device in which the D mode and the E mode are formed on the same substrate can be obtained. Since the SiC semiconductor device having such a structure does not combine an n-channel MOSFET and a p-channel MOSFET as in a CMOS, the channel mobility of the D-mode and E-mode elements is equal. For this reason, since the channel mobility is different as in CMOS, it is not necessary to adjust the area, and the elements of the D mode and the E mode can be made the same area.

  The SiC semiconductor device having such a structure is basically manufactured by the same manufacturing method as in the first embodiment. However, since the recess 2a is not formed for the D-mode JFET, after the carbon mask 11 is patterned, a mask that covers the D-mode JFET is disposed, and then an etching process for forming the recess 2a is performed. It will be.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is obtained by changing the SiC substrate 1 to an on-substrate having no off-angle instead of an off-substrate with respect to the first embodiment, and is otherwise the same as the first embodiment. Only the parts different from the first embodiment will be described.

FIG. 10 is a cross-sectional view of the SiC semiconductor device including the JFET according to the present embodiment. In the present embodiment, an on-substrate having no off-angle, such as an a-plane substrate, is used as the SiC substrate 1. As a result, as shown in FIG. 10, the surface of the p ⁺ -type gate region 4 is also a flat surface with no facet formed on the a-plane.

Thus, an on-substrate can be used as the SiC substrate 1 instead of an off-substrate. In this way, the surface of the p ⁺ type gate region 4 can be a flat surface on which no facet is formed. Such a SiC semiconductor device can also be manufactured by the same manufacturing method as that of the SiC semiconductor device of the first embodiment except that an a-plane on-substrate is used as the SiC substrate 1.

Note that the p ⁻ -type buffer layer 8 can be formed even when an on-substrate is used as in this embodiment. FIG. 11 is a cross-sectional view of the SiC semiconductor device when the p ⁻ -type buffer layer 8 is formed. As shown in this figure, on the surface of the SiC substrate 1, than the p ⁺ -type gate region 4 p at a low impurity concentration ^- it forms a type buffer layer 8, the p ^- surface of the type buffer layer 8 An n-type channel layer 2 is formed on the substrate. Further, p ^- type buffer layer 8 is provided with a p ⁺ -type contact region 8a which is a high impurity concentration, p ⁺ -type through recess 9 passed through the n ⁺ -type source region 3a at the lower portion of the source electrode 6 The contact region 8a is connected to the source electrode 6 and fixed to the ground potential. Thus, also in the structure of this embodiment, as in the second embodiment, by forming the p ⁻ -type buffer layer 8, the breakdown voltage can be further increased, and the radio waves generated when the JFET is operated can be absorbed. Thus, it is possible to obtain a SiC semiconductor device suitable for higher frequencies.

Further, when an a-plane on-substrate is used as SiC substrate 1, p ⁺ -type gate region 4 may have a different crystal structure. FIG. 12 is a cross-sectional view of an SiC semiconductor device including a JFET in the case where the p ⁺ -type gate region 4 has a different crystal structure. As shown in this figure, a portion of the p ⁺ type gate region 4 formed immediately above the recess 2a is composed of 4C—SiC, and a portion of the p ⁺ type gate region 4 that is wide (flange portion). Is made of 3C-SiC.

When the SiC substrate 1 is an a-plane on-substrate, 3C—SiC can be grown in the lateral direction of 4H—SiC depending on the epitaxial growth conditions when the p ⁺ -type gate region 4 is formed. FIG. 13 is an enlarged cross-sectional view showing this state. As shown in this figure, the underlying crystal structure is inherited in the vertical direction from the portion in contact with the n ⁻ -type channel layer 2 and the crystal structure becomes 4H—SiC. Regarding the lateral growth for 4H—SiC, 3C—SiC is grown along the <0001> direction due to the anisotropy of lateral growth. In this way, the p ⁺ -type gate region 4 can be configured with a different crystal structure. As described above, in the case of 3C—SiC, since the impurity doping level during epitaxial growth can be increased compared to 4H—SiC or the like, the internal resistance of the p ⁺ -type gate region 4 can be reduced. It becomes.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is obtained by forming the p ⁺ -type gate region 4 without forming the recess 2a as in the third embodiment with respect to the sixth embodiment. Therefore, only the differences from the sixth embodiment will be described.

FIG. 14 is a cross-sectional view of an SiC semiconductor device including a JFET according to the present embodiment. As shown in this figure, in this embodiment, the p ⁺ type gate region 4 is formed directly on the outermost surface of the n ⁻ type channel layer 2. In this way, even when an on-substrate is used as the SiC substrate 1, the p ⁺ -type gate region 4 may be formed without forming the recess 2a. Even with such a structure, the same effect as in the sixth embodiment can be obtained.

(Other embodiments)
The second, in the sixth embodiment, p ^- has been described structure -type buffer layer 8 is not limited to, third to fifth, also the seventh embodiment, p ^- -type buffer layer 8 It can be set as the structure to form. Also in this case, the p ⁻ -type buffer layer 8 can be grounded by making the p ⁻ -type buffer layer 8 electrically connected to the source electrode 6 through the p ⁺ -type contact region 8 a and the recess 9. .

In each of the above embodiments, the n channel type JFET having the n ⁻ type channel layer 2 as a channel has been described as an example. However, the p channel in which the n type and the p type shown in the above embodiments are inverted The present invention may be applied to a type of JFET.

Moreover, although each said embodiment demonstrated the case where the SiC substrate 1 was comprised by 4H-SiC, you may comprise by the thing of other crystal structures, such as 6H-SiC. Further, the case where the p ⁺ -type gate region 4 takes over the crystal structure of the underlying SiC substrate 1 (n ⁻ -type channel layer 2) and has the same crystal structure has been described, but the epitaxial growth is performed so as to have different crystal structures. Conditions can also be set. For example, the p ⁺ type gate region 4 made of 3C—SiC can be formed on the SiC substrate 1 (n ⁻ type channel layer 2) made of 6H—SiC. In this case, since the doping level of impurities in the p ⁺ type gate region 4 can be increased, the resistance of the p ⁺ type gate region 4 can be reduced.

Further, the gate electrode 5, the source electrode 6 and the drain electrode 7 have a three-layer structure, and a Ni-based metal layer, a Ti-based metal layer, and a metal layer made of Al or Au are taken as an example. However, these are merely examples, for example, Ni / Ti / Mo / Au, Ti / Mo / Ni / Au, Ni / Mo / Ti, Ti / Mo / Ni, Ti / Mo, Ni in order from the lower layer. A laminated structure of / Mo may be used, or a single layer structure of only Ti or Ni may be used. Although the case where the first layers 5a, 6a, and 7a are silicided to form metal silicide has been described, the resistance may be reduced by forming the first layers 5a, 6a, and 7a into metal carbide to form metal silicide. In either case, since the portion in contact with the p ⁺ type gate region 4 becomes metal silicide or metal carbide, the contact portion between the first layer 5a and the p ⁺ type gate region 4 is silicided or carbided in a self-aligned manner. can do.

  In the above embodiment, the SiC semiconductor device is described as an example of the semiconductor device. However, the present invention can be applied to a semiconductor device using Si, and other wide band gap semiconductor devices such as GaN and diamond. The present invention can also be applied to a semiconductor device using AlN or the like.

  In addition, when indicating the orientation of a crystal, a bar (-) should be added to a desired number, but there is a limitation in expression based on a personal computer application. A bar shall be placed in front of the number.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 n ^- type channel layer 2a Recess 3 n ⁺ type layer 3a n ⁺ type source region 3b n ⁺ type drain region 4 p ⁺ type gate region 5 Gate electrode 6 Source electrode 7 Drain electrode 8 p ^- type buffer layer 8a p ⁺ type contact region 9 recess 10 resist 11 carbon mask 12 mask for etching 13 resist

Claims (10)

A substrate (1) composed of a semiconductor material having a main surface;
A first conductivity type channel layer (2) formed of a first conductivity type semiconductor by epitaxial growth on the main surface of the substrate (1);
A source region of a first conductivity type formed in a surface layer portion of the channel layer (2) in the channel layer (2), having a higher impurity concentration than the channel layer (2), and spaced apart from each other. 3a) and the drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). A second conductivity type gate region (4) in which a portion separated from the channel layer (2) is wider than a portion in contact with the channel layer (2);
A gate electrode (5) formed on the gate region (4) and electrically connected to the gate region (4);
A source electrode (6) electrically connected to the source region (3a);
A JFET having a drain electrode (7) electrically connected to the drain region (3b) ;
As the semiconductor material, silicon carbide which is a wide band gap semiconductor is used, and as the substrate, a silicon carbide substrate (1) is used,
The gate region (4) is made of silicon carbide having the same crystal structure as the silicon carbide substrate (1),
Further, an off substrate having a main surface having an off angle of 1 ° or less with respect to the Si surface or C surface is used as the silicon carbide substrate (1),
A semiconductor device characterized in that a (0001) facet is formed on the surface of the widened portion of the gate region (4) . A substrate (1) composed of a semiconductor material having a main surface;
A first conductivity type channel layer (2) formed of a first conductivity type semiconductor by epitaxial growth on the main surface of the substrate (1);
A source region of a first conductivity type formed in a surface layer portion of the channel layer (2) in the channel layer (2), having a higher impurity concentration than the channel layer (2), and spaced apart from each other. 3a) and the drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). A second conductivity type gate region (4) in which a portion separated from the channel layer (2) is wider than a portion in contact with the channel layer (2);
A gate electrode (5) formed on the gate region (4) and electrically connected to the gate region (4);
A source electrode (6) electrically connected to the source region (3a);
A JFET having a drain electrode (7) electrically connected to the drain region (3b) ;
As the semiconductor material, silicon carbide which is a wide band gap semiconductor is used, and as the substrate, a silicon carbide substrate (1) is used,
The gate region (4) is made of silicon carbide having the same crystal structure as the silicon carbide substrate (1),
Furthermore, an on-substrate whose main surface is a-plane is used as the silicon carbide substrate (1),
The semiconductor device according to claim 1 , wherein the gate region (4) has a flat surface with an a surface . A substrate (1) composed of a semiconductor material having a main surface;
A first conductivity type channel layer (2) formed of a first conductivity type semiconductor by epitaxial growth on the main surface of the substrate (1);
A source region of a first conductivity type formed in a surface layer portion of the channel layer (2) in the channel layer (2), having a higher impurity concentration than the channel layer (2), and spaced apart from each other. 3a) and the drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). A second conductivity type gate region (4) in which a portion separated from the channel layer (2) is wider than a portion in contact with the channel layer (2);
A gate electrode (5) formed on the gate region (4) and electrically connected to the gate region (4);
A source electrode (6) electrically connected to the source region (3a);
A JFET having a drain electrode (7) electrically connected to the drain region (3b) ;
As the semiconductor material, silicon carbide which is a wide band gap semiconductor is used, and as the substrate, a silicon carbide substrate (1) is used,
In the gate region (4), a portion in contact with the channel layer (2) is made of silicon carbide having the same crystal structure as the silicon carbide substrate (1), and at least one of the wide portions. The semiconductor device is characterized in that the portion is made of silicon carbide having a crystal structure different from that of the silicon carbide substrate (1) . As the silicon carbide substrate (1), an off-substrate having a main surface having an off-angle exceeding 1 ° with respect to the Si or C-plane is used.
A (0001) facet is formed on the surface of the portion of the gate region (4) that is made of silicon carbide having the same crystal structure as the silicon carbide substrate (1), and is a crystal different from the silicon carbide substrate (1). 4. The semiconductor device according to claim 3 , wherein a portion of the structure made of silicon carbide is 3C—SiC formed on a surface of the (0001) facet. An on-substrate whose main surface is a-plane is used as the silicon carbide substrate (1),
The crystal structure of the silicon carbide substrate (1) is inherited in the vertical direction from the portion of the gate region (4) that is in contact with the channel layer (2), and the width of the gate region (4) is increased. The semiconductor device according to claim 3 , wherein the portion is 3C—SiC. Providing a substrate (1) made of a semiconductor material having a main surface, and forming a first conductivity type channel layer (2) on the main surface by epitaxial growth of a first conductivity type semiconductor;
A source region (first conductivity type) having a higher impurity concentration than the channel layer (2) in the surface layer portion of the channel layer (2) in the channel layer (2) and being spaced apart from each other. 3a) and forming a drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). Forming a second conductivity type gate region (4) in which a portion spaced from the channel layer (2) is wider than a portion in contact with the channel layer (2);
On the gate region (4), a gate electrode (5) electrically connected to the gate region (4), a source electrode (6) electrically connected to the source region (3a), And forming a drain electrode (7) electrically connected to the drain region (3b), and a method of manufacturing a semiconductor device including a JFET,
Disposing a carbon mask (11) in which a region where the gate region (4) is to be formed is opened on the surface of the channel layer (2);
Epitaxially growing the gate region (4) on the channel layer (2) using the carbon mask (11) as a mask so as to laterally grow on the carbon mask (11);
The carbon removing the mask (11), seen including and a step of separating the lateral grown portion from a surface of said channel layer (2) of the gate region (4),
A silicon carbide substrate (1) made of an off-substrate having a main surface having an off angle of 1 ° or less with respect to the Si surface or the C-plane as the substrate,
In the step of forming the gate region (4), the gate region (4) in which a (0001) facet is formed on a surface of a portion wider than a portion in contact with the channel layer (2) by the lateral growth. Forming a semiconductor device. Providing a substrate (1) made of a semiconductor material having a main surface, and forming a first conductivity type channel layer (2) on the main surface by epitaxial growth of a first conductivity type semiconductor;
A source region (first conductivity type) having a higher impurity concentration than the channel layer (2) in the surface layer portion of the channel layer (2) in the channel layer (2) and being spaced apart from each other. 3a) and forming a drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). Forming a second conductivity type gate region (4) in which a portion spaced from the channel layer (2) is wider than a portion in contact with the channel layer (2);
On the gate region (4), a gate electrode (5) electrically connected to the gate region (4), a source electrode (6) electrically connected to the source region (3a), And forming a drain electrode (7) electrically connected to the drain region (3b), and a method of manufacturing a semiconductor device including a JFET,
Disposing a carbon mask (11) in which a region where the gate region (4) is to be formed is opened on the surface of the channel layer (2);
Epitaxially growing the gate region (4) on the channel layer (2) using the carbon mask (11) as a mask so as to laterally grow on the carbon mask (11);
The carbon removing the mask (11), seen including and a step of separating the lateral grown portion from a surface of said channel layer (2) of the gate region (4),
A silicon carbide substrate (1) comprising an off-substrate having a main surface having an off-angle exceeding 1 ° with respect to the Si or C-plane as the substrate,
In the step of forming the gate region (4), a (0001) facet is formed on the surface of a portion wider than a portion in contact with the channel layer (2), and the (0001) is formed by the lateral growth. A method of manufacturing a semiconductor device, comprising forming the gate region (4) in which 3C-SiC is grown on a surface of a facet . Providing a substrate (1) made of a semiconductor material having a main surface, and forming a first conductivity type channel layer (2) on the main surface by epitaxial growth of a first conductivity type semiconductor;
A source region (first conductivity type) having a higher impurity concentration than the channel layer (2) in the surface layer portion of the channel layer (2) in the channel layer (2) and being spaced apart from each other. 3a) and forming a drain region (3b);
A portion of the surface of the channel layer (2) located between the source region (3a) and the drain region (3b) is disposed apart from the source region (3a) and the drain region (3b). Forming a second conductivity type gate region (4) in which a portion spaced from the channel layer (2) is wider than a portion in contact with the channel layer (2);
On the gate region (4), a gate electrode (5) electrically connected to the gate region (4), a source electrode (6) electrically connected to the source region (3a), And forming a drain electrode (7) electrically connected to the drain region (3b), and a method of manufacturing a semiconductor device including a JFET,
Disposing a carbon mask (11) in which a region where the gate region (4) is to be formed is opened on the surface of the channel layer (2);
Epitaxially growing the gate region (4) on the channel layer (2) using the carbon mask (11) as a mask so as to laterally grow on the carbon mask (11);
The carbon removing the mask (11), seen including and a step of separating the lateral grown portion from a surface of said channel layer (2) of the gate region (4),
A silicon carbide substrate (1) comprising an on-substrate whose main surface does not have an a-plane off angle as the substrate,
In the step of forming the gate region (4), the gate region (4) in which a portion that is wider than a portion in contact with the channel layer (2) by the lateral growth becomes 3C-SiC is formed. A method of manufacturing a semiconductor device. Forming a recess (2a) in a region where the gate region (4) is to be formed in the surface of the channel layer (2),
9. The gate region (4) is formed in the recess (2 a) formed in the channel layer (2) in the step of epitaxially growing the gate region (4) . A method of manufacturing a semiconductor device according to one of the above. Disposing a Les resist (10) on a surface of said channel layer (2),
Carbonizing the resist (10) to form the carbon mask (11);
After disposing an etching mask (12) on the surface of the carbon mask (11), patterning the etching mask (12) to open a region where the gate region (4) is to be formed;
Using the etching mask (12), opening the formation region of the gate region (4) in the carbon mask (11);
Using the etching mask (12) and the carbon mask (11) as a mask, the surface of the channel layer (2) is etched in a region where the gate region (4) opened in the mask is to be formed. A step of forming the recess (2a),
Forming the gate region (4) in the recess (2a) formed in the channel layer (2) using the carbon mask (11) after removing the etching mask (12); The method for manufacturing a semiconductor device according to claim 9 , further comprising:

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