JP5487290B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP5487290B2 JP5487290B2 JP2012278898A JP2012278898A JP5487290B2 JP 5487290 B2 JP5487290 B2 JP 5487290B2 JP 2012278898 A JP2012278898 A JP 2012278898A JP 2012278898 A JP2012278898 A JP 2012278898A JP 5487290 B2 JP5487290 B2 JP 5487290B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
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Description
本発明は、電源装置に係り、特に、電子機器等に用いられる半導体装置及び電源装置に適用して有効な技術に関する。 The present invention relates to a power supply device, and more particularly, to a technique effective when applied to a semiconductor device and a power supply device used in electronic equipment and the like.
従来より、電子機器等に用いられる電源装置として、図２に示すような電源装置が知られている。図２に示す電源装置では、直流入力電源６０から入力コンデンサ６１を含んで構成された入力部５１に入力された直流電力を駆動部７０から出力される制御信号に基づいてスイッチング部５２でスイッチングし、転流ダイオード６３や出力フィルタ５５を含んで構成された出力部５３から負荷６６に対して電力が供給される。また、負荷６６へ出力される電圧や電流は検出部６７で検出され、この検出値と設定部６８で設定された負荷６６の制御目標値とが比較演算部６９で比較され、駆動部７０から比較結果に基づいた制御信号がスイッチング部５２に出力される。このようにして、負荷に供給される電力が制御目標値と一致するように制御される。 2. Description of the Related Art Conventionally, a power supply device as shown in FIG. 2 is known as a power supply device used for electronic devices and the like. In the power supply device shown in FIG. 2, the switching unit 52 switches the DC power input from the DC input power source 60 to the input unit 51 including the input capacitor 61 based on the control signal output from the driving unit 70. Electric power is supplied to the load 66 from the output unit 53 including the commutation diode 63 and the output filter 55. The voltage or current output to the load 66 is detected by the detection unit 67, and the detected value and the control target value of the load 66 set by the setting unit 68 are compared by the comparison calculation unit 69. A control signal based on the comparison result is output to the switching unit 52. In this way, the power supplied to the load is controlled so as to coincide with the control target value.
このような電源装置の具体的な回路構成を図３に示す。スイッチング部５２は、能動素子（例えばトランジスタやＭＯＳＦＥＴ等）６２で構成されている。出力部５３は、転流ダイオード６３と、チョークコイル６４及びコンデンサ６５で構成された出力フィルタとで構成されている。制御部５４は、比較演算部６９、設定部６８、駆動部７０で構成されている。さらに、制御部５４は図示しない発振回路を備えており、駆動部７０からパルス信号を能動素子６２に出力する。これにより、能動素子６２に印加される直流入力電源６０からの直流電圧Ｖｉｎがスイッチングされる。 A specific circuit configuration of such a power supply apparatus is shown in FIG. The switching unit 52 includes an active element 62 (for example, a transistor or a MOSFET). The output unit 53 includes a commutation diode 63 and an output filter composed of a choke coil 64 and a capacitor 65. The control unit 54 includes a comparison calculation unit 69, a setting unit 68, and a drive unit 70. Further, the control unit 54 includes an oscillation circuit (not shown), and outputs a pulse signal from the driving unit 70 to the active element 62. As a result, the DC voltage Vin from the DC input power supply 60 applied to the active element 62 is switched.
図３に示す電源装置では、能動素子６２がオンの場合には、直流電力はチョークコイル６４及びコンデンサ６５にチャージされると共に負荷６６へ供給される。能動素子６２がオフの場合は、チョークコイル６４及びコンデンサ６５にチャージされていたエネルギーが転流ダイオード６３を介して負荷６６に供給される。 In the power supply device shown in FIG. 3, when the active element 62 is on, DC power is charged to the choke coil 64 and the capacitor 65 and supplied to the load 66. When the active element 62 is off, the energy charged in the choke coil 64 and the capacitor 65 is supplied to the load 66 through the commutation diode 63.
このとき、制御部５４では、比較演算部６９において検出部６７で検出した出力電圧Ｖｏをモニタし、これと設定部６８で設定された制御目標値と比較し、駆動部７０から比較結果に基づいた制御信号をスイッチング部５２に出力する。これにより、能動素子６２がオンオフ制御され、負荷に供給される電力が制御目標値と一致するように制御される。このときの出力電圧Ｖｏは、以下の（１）式で示される。 At this time, the control unit 54 monitors the output voltage Vo detected by the detection unit 67 in the comparison calculation unit 69, compares this with the control target value set by the setting unit 68, and based on the comparison result from the drive unit 70. The control signal is output to the switching unit 52. Thereby, the active element 62 is controlled to be turned on / off, and the power supplied to the load is controlled to coincide with the control target value. The output voltage Vo at this time is expressed by the following equation (1).
Ｖｏ＝Ｖｉｎ×（Ｔｏｎ／Ｔ）・・・（１）
ただし、Ｖｉｎは入力直流電圧、Ｔは駆動部７０から出力されるパルス信号の周期、Ｔｏｎは周期Ｔのうち能動素子６２が導通の時間を示す。すなわち、Ｔｏｎ／Ｔはデューティ比を示す。
Vo = Vin × (Ton / T) (1)
Here, Vin is an input DC voltage, T is a period of a pulse signal output from the drive unit 70, and Ton is a period of time during which the active element 62 is conductive in the period T. That is, Ton / T represents the duty ratio.
ところで、出力部５３における転流側には、図３に示すように受動素子であるダイオードを使用するのが通常であるが、転流ダイオード６３は、図４に示すような電流−電圧特性を有しており、電流がある所定値以上になると、順方向電圧が飽和状態になる。この飽和電圧は、高速ダイオードにおいては０．９Ｖ〜１．３Ｖ、ショットキーダイオードでは０．４５Ｖ〜０．５５Ｖ程度となっている。このように、転流ダイオード６３の順方向電圧が飽和することにより電力損失が生じ、電源変換効率を悪化させるという問題があった。さらに、電力損失が大きく素子のジャンクション温度が上昇するため、出力電流を大きくする程、転流ダイオード６３を多くして（２個や３個等）並列接続し、１素子当たりの電力損失を分散させ、ジャンクション温度を抑制する必要があるという問題があった。 Incidentally, a diode which is a passive element is usually used on the commutation side of the output unit 53 as shown in FIG. 3, but the commutation diode 63 has a current-voltage characteristic as shown in FIG. If the current exceeds a predetermined value, the forward voltage becomes saturated. This saturation voltage is about 0.9V to 1.3V for high-speed diodes and about 0.45V to 0.55V for Schottky diodes. Thus, there is a problem that power loss occurs due to saturation of the forward voltage of the commutation diode 63 and power conversion efficiency is deteriorated. Furthermore, since the power loss is large and the junction temperature of the element rises, the larger the output current is, the more commutation diodes 63 (two or three, etc.) are connected in parallel to distribute the power loss per element. There is a problem that it is necessary to suppress the junction temperature.
この問題を解決するため、図５に示すように、転流側に転流用ＭＯＳＦＥＴ３（ダイオード３Ａ）を使用した同期整流方式の電源装置が知られている。図５において、１は直流入力電源、２は整流用ＭＯＳＦＥＴ（ダイオード２Ａ）、４はチョークコイル、５は出力コンデンサ、６は負荷となるＬＳＩを示す抵抗、７は入力コンデンサ、９は制御回路である。これは図６に示すように、ダイオードの電流−電圧特性が非線形性であるのに対し、ＭＯＳＦＥＴの電流−電圧特性がゲート電圧によっては線形性になり、電圧降下がダイオードの場合と比較して小さいことを利用したものである。 In order to solve this problem, as shown in FIG. 5, a synchronous rectification type power supply device using a commutation MOSFET 3 (diode 3A) on the commutation side is known. In FIG. 5, 1 is a DC input power source, 2 is a rectifying MOSFET (diode 2A), 4 is a choke coil, 5 is an output capacitor, 6 is a resistor indicating an LSI serving as a load, 7 is an input capacitor, and 9 is a control circuit. is there. As shown in FIG. 6, the current-voltage characteristic of the diode is non-linear, whereas the current-voltage characteristic of the MOSFET is linear depending on the gate voltage, and the voltage drop is smaller than that of the diode. It uses small things.
このような電源装置では、図７に示すような回路の形状に起因する寄生成分が存在する。例えば、主回路の寄生抵抗１０、主回路の寄生インダクタンス１１、ＭＯＳＦＥＴゲート駆動回路の寄生抵抗１２、ＭＯＳＦＥＴゲート駆動回路の寄生インダクタンス１３がこれに該当する。図８は、主回路の寄生インダクタンス１１と電源損失の関係を示したもので、インダクタンスが大きくなるにしたがい、損失が増加することが分かる。主回路の寄生抵抗１０、ＭＯＳＦＥＴゲート駆動回路の寄生抵抗１２、ＭＯＳＦＥＴゲート駆動回路の寄生インダクタンス１３についても同様に、数値が大きくなるに従い、損失が増加するという傾向を示す。 In such a power supply device, there exists a parasitic component due to the shape of the circuit as shown in FIG. For example, the parasitic resistance 10 of the main circuit, the parasitic inductance 11 of the main circuit, the parasitic resistance 12 of the MOSFET gate driving circuit, and the parasitic inductance 13 of the MOSFET gate driving circuit correspond to this. FIG. 8 shows the relationship between the parasitic inductance 11 of the main circuit and the power loss, and it can be seen that the loss increases as the inductance increases. Similarly, the parasitic resistance 10 of the main circuit, the parasitic resistance 12 of the MOSFET gate driving circuit, and the parasitic inductance 13 of the MOSFET gate driving circuit show a tendency that the loss increases as the numerical value increases.
主回路の寄生インダクタンス１１を低減する手段として、複数の半導体チップを一つのパッケージに実装する手法があり、マルチチップモジュール（ＭＣＭ：Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）、またはＳｉＰ（Ｓｙｅｔｅｍ ｉｎ Ｐａｃｋａｇｅ）と呼ばれている。最近、図９に示す駆動部１５と整流用ＭＯＳＦＥＴ２、転流用ＭＯＳＦＥＴ３を機能ブロック１６として集積化したモジュールが製品化されており、これらの内容は、特開２００４−３４２７３５号公報（特許文献１）に詳細に記述されている。 As a means for reducing the parasitic inductance 11 of the main circuit, there is a method of mounting a plurality of semiconductor chips in one package, which is called a multi-chip module (MCM) or SiP (System in Package). . Recently, a module in which the drive unit 15, the rectifying MOSFET 2, and the commutation MOSFET 3 shown in FIG. 9 are integrated as a function block 16 has been commercialized, and these contents are disclosed in Japanese Patent Application Laid-Open No. 2004-342735 (Patent Document 1). Is described in detail.
図１０は、上記特許文献１に示された図で、ＱＦＮパッケージ（Ｑｕａｄ ＦｌａｔＮｏ−Ｌｅａｄ）に整流用ＭＯＳＦＥＴ２０、転流用ＭＯＳＦＥＴ２１、駆動用ＩＣ２２を集積し、チップ間の接続とチップとリードフレーム２４の接続はワイヤボンディング２３を用いている。図１１は、図１０の断面図（ａ−ａ’線）を示す。 FIG. 10 is a diagram shown in the above-mentioned Patent Document 1. In the QFN package (Quad Flat No-Lead), a rectifying MOSFET 20, a commutation MOSFET 21, and a driving IC 22 are integrated. For the connection, wire bonding 23 is used. FIG. 11 is a cross-sectional view (a-a ′ line) of FIG. 10.
しかしながら、この半導体装置は主回路の電流経路にワイヤボンディングを用いているため、インダクタンスが大きいという問題がある。 However, since this semiconductor device uses wire bonding in the current path of the main circuit, there is a problem that inductance is large.
そこで、本発明は、上記問題を解決すべくなされたものであり、インダクタンスを低減できる半導体装置を提供することを目的とするものである。 Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device capable of reducing inductance.
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
本発明は、上記目的を達成するために、整流用ＭＯＳＦＥＴと転流用ＭＯＳＦＥＴ、及びこれらを駆動する駆動用ＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）を一つのパッケージに実装した半導体装置において、整流用ＭＯＳＦＥＴ、金属板、転流用ＭＯＳＦＥＴを積層し、主回路の電流はパッケージの裏面から表面に向かって流れ、上記金属板はパッケージ内の配線を経由して出力端子に繋がり、駆動用ＩＣと整流用ＭＯＳＦＥＴ、及び転流用ＭＯＳＦＥＴを繋ぐ配線にワイヤボンディングを用い、全ての端子が同一面に配置されていることを特徴とする。 To achieve the above object, the present invention provides a rectifying MOSFET, a commutation MOSFET, and a driving IC (Integrated Circuit) for driving them in a single package. Laminating commutation MOSFETs, the current of the main circuit flows from the back side to the front side of the package, the metal plate is connected to the output terminal via the wiring in the package, the driving IC, the rectification MOSFET, and the commutation Wire bonding is used for wiring connecting MOSFETs, and all terminals are arranged on the same plane.
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
本発明によれば、半導体装置の主回路インダクタンスを低減し、電源損失及び電圧スパイクを低減できるという効果を有する。 According to the present invention, it is possible to reduce the main circuit inductance of the semiconductor device and reduce the power loss and voltage spike.
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
また、図面において、半導体装置を示す平面図は、実際には上面が封止材で覆われているが、分かりやすくするために、封止材を取り除いて内蔵している部品が露出した状態を示している。さらに、半導体装置を示す断面図は、主要な部品を切断するように線を決め、この線で切断した断面を示している。 In the drawings, the top view of the semiconductor device is actually covered with a sealing material, but for the sake of clarity, the embedded component is exposed after the sealing material is removed. Show. Further, the cross-sectional view showing the semiconductor device shows a cross section obtained by deciding a line so as to cut main components and cutting the main part.
本発明の実施の形態における半導体装置は、前述した図５に示すような同期整流方式の電源装置に用いられる。すなわち、この電源装置は、整流用ＭＯＳＦＥＴの一方の主端子が直流入力電源の正電位側に接続され、整流用ＭＯＳＦＥＴの他方の主端子がチョークコイルと転流用ＭＯＳＦＥＴの一方の主端子に接続され、転流用ＭＯＳＦＥＴの他方の主端子が直流入力電源の負電位側に接続され、出力コンデンサの一方の端子がチョークコイルの他方の端子に接続され、出力コンデンサの他方の端子が転流用ＭＯＳＦＥＴの他方の主端子に接続され、負荷となる半導体装置に電力を供給する端子の一方がチョークコイルの他方の端子に接続され、負荷となる半導体装置に電力を供給する端子の他方が転流用ＭＯＳＦＥＴの他方の主端子に接続され、制御回路により整流用ＭＯＳＦＥＴ及び転流用ＭＯＳＦＥＴのゲートを駆動するような構成となっている。 The semiconductor device according to the embodiment of the present invention is used in a synchronous rectification type power supply device as shown in FIG. That is, in this power supply device, one main terminal of the rectifying MOSFET is connected to the positive potential side of the DC input power supply, and the other main terminal of the rectifying MOSFET is connected to one main terminal of the choke coil and the commutation MOSFET. The other main terminal of the commutation MOSFET is connected to the negative potential side of the DC input power supply, one terminal of the output capacitor is connected to the other terminal of the choke coil, and the other terminal of the output capacitor is the other terminal of the commutation MOSFET. Is connected to the other terminal of the choke coil, and the other terminal of the choke coil is connected to the other terminal of the commutation MOSFET. Connected to the main terminals of the rectifier, and the control circuit drives the gates of the rectification MOSFET and the commutation MOSFET.
以下において、本発明の実施の形態を、各実施例に分けて説明する。 In the following, embodiments of the present invention will be described separately for each example.
（第１の実施例）
図１２、図１を用いて、本発明の第１の実施例における半導体装置について説明する。図１２に示すように、本実施例の半導体装置は、整流用ＭＯＳＦＥＴ２０と転流用ＭＯＳＦＥＴ２１、及びこれらを駆動する駆動用ＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔｓ）２２を備え、整流用ＭＯＳＦＥＴ２０、金属板（導電体）２５、転流用ＭＯＳＦＥＴ２１を積層し、ワイヤボンディング２３により駆動用ＩＣ２２と整流用ＭＯＳＦＥＴ２０、及び転流用ＭＯＳＦＥＴ２１を接続し、整流用ＭＯＳＦＥＴ２０と出力端子ＬＸに繋がるリードフレームを金属板２５とワイヤボンディングを介して接続し、転流用ＭＯＳＦＥＴ２１とグランド端子Ｇｎｄに繋がるリードフレームをワイヤボンディングで接続する。主回路の端子と駆動用ＩＣの端子は同一面上に配置される。その理由は、本発明に係る半導体装置は電気回路基板に実装されるので、端子を３次元的に取り出すことが困難であるためである。図１は、図１２の断面図（ａ−ａ’線）を示す。
(First embodiment)
A semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 12, the semiconductor device of this embodiment includes a rectifying MOSFET 20, a commutation MOSFET 21, and a driving IC (Integrated Circuits) 22 for driving them, and includes a rectifying MOSFET 20, a metal plate (conductor) 25. The commutation MOSFET 21 is stacked, the driving IC 22 is connected to the rectification MOSFET 20 and the commutation MOSFET 21 by wire bonding 23, and the lead frame connected to the rectification MOSFET 20 and the output terminal LX is connected to the metal plate 25 through wire bonding. The lead frame connected to the commutation MOSFET 21 and the ground terminal Gnd is connected by wire bonding. The terminals of the main circuit and the driving IC are arranged on the same plane. This is because the semiconductor device according to the present invention is mounted on an electric circuit board, and thus it is difficult to take out terminals three-dimensionally. FIG. 1 shows a cross-sectional view (aa ′ line) of FIG.
次に、この半導体装置の電流経路について説明する。電流は、主回路電流とゲート電流の２種類があり、また主回路電流は２つの期間に分けることができる。つまり、「電力を供給する期間」と「転流期間」で、「電力を供給する期間」は、整流用ＭＯＳＦＥＴ２０がオン、転流用ＭＯＳＦＥＴ２１がオフで、電流は図１２の電源端子Ｖｉｎに繋がるリードフレーム２４から、整流用ＭＯＳＦＥＴ２０を裏面から表面に向かって流れ、金属板２５を通り、図９のチョークコイル４と出力コンデンサ５からなる出力フィルタを介して負荷に流れ込む。一方、「転流期間」の電流は、グランド端子Ｇｎｄから金属板２５を通って、転流用ＭＯＳＦＥＴ２１を表面から裏面に向かって流れ、リードフレーム２４を経由してチョークコイル４に流れ込む。図１２では、整流用ＭＯＳＦＥＴ２０、転流用ＭＯＳＦＥＴ２１ともに表面側がソース、裏面側がドレインの所謂「縦型デバイス」を想定している。 Next, the current path of this semiconductor device will be described. There are two types of current, main circuit current and gate current, and the main circuit current can be divided into two periods. That is, in the “period for supplying power” and the “commutation period”, the “period for supplying power” is such that the rectification MOSFET 20 is on, the commutation MOSFET 21 is off, and the current leads to the power supply terminal Vin in FIG. From the frame 24, the rectifying MOSFET 20 flows from the back surface to the front surface, passes through the metal plate 25, and flows into the load through the output filter including the choke coil 4 and the output capacitor 5 of FIG. On the other hand, the current in the “commutation period” flows from the ground terminal Gnd through the metal plate 25, flows through the commutation MOSFET 21 from the front surface to the back surface, and flows into the choke coil 4 through the lead frame 24. In FIG. 12, it is assumed that both the rectifying MOSFET 20 and the commutation MOSFET 21 are so-called “vertical devices” in which the front side is the source and the back side is the drain.
図１３は、本発明と従来例の電源損失を比較したものである。従来例の主回路インダクタンスが２．３ｎＨであるのに対して、本発明では０．５ｎＨに低減でき、電源損失は約５．５Ｗから５．１Ｗへ改善する。 FIG. 13 compares the power loss between the present invention and the conventional example. While the main circuit inductance of the conventional example is 2.3 nH, in the present invention, it can be reduced to 0.5 nH, and the power loss is improved from about 5.5 W to 5.1 W.
（第２の実施例）
次に、金属板２５の応力を緩和した実施例について述べる。本発明の半導体装置の製造工程には、リフローと呼ばれる高温のプロセスが含まれる。リフローの際には、半導体と金属の熱膨張係数が異なるため、半導体チップにクラックが発生するなどの問題がある。図１４の実施例では、金属板２５に複数の溝４６を設けることでリフロー時の応力を緩和することができる。
(Second embodiment)
Next, an embodiment in which the stress of the metal plate 25 is relaxed will be described. The manufacturing process of the semiconductor device of the present invention includes a high-temperature process called reflow. During reflow, the semiconductor and metal have different coefficients of thermal expansion, which causes problems such as the generation of cracks in the semiconductor chip. In the embodiment of FIG. 14, the stress during reflow can be relieved by providing a plurality of grooves 46 in the metal plate 25.
（第３の実施例）
次に、第１の実施例と比べてインダクタンスを更に低減できる、他の実施例について述べる。図１２では、金属板２５からリードフレーム２４、及び転流用ＭＯＳＦＥＴ２１からグランド端子の接続にワイヤボンディングを用いているが、ワイヤボンディングのインダクタンスは金属板に比べて大きいという問題がある。
(Third embodiment)
Next, another embodiment that can further reduce the inductance as compared with the first embodiment will be described. In FIG. 12, wire bonding is used to connect the lead plate 24 from the metal plate 25 and the ground terminal from the commutation MOSFET 21, but there is a problem that the inductance of the wire bonding is larger than that of the metal plate.
図１５は、金属板２５からリードフレーム２４、及び転流用ＭＯＳＦＥＴ２１とグランド端子の接続に金属板２５と金属板２８を用いた実施例で、第１の実施例と比べて主回路のインダクタンスを大幅に低減することができる。図１６は、図１５の断面図（ａ−ａ’線）を示す。 FIG. 15 shows an embodiment in which the metal plate 25 and the metal plate 28 are used to connect the lead frame 24, the commutation MOSFET 21 and the ground terminal from the metal plate 25, and the inductance of the main circuit is greatly increased as compared with the first embodiment. Can be reduced. FIG. 16 is a sectional view (a-a ′ line) of FIG. 15.
本実施例では、金属板２５からリードフレーム２４、及び転流用ＭＯＳＦＥＴ２１からグランド端子の接続を金属板としたが、どちらか一方を金属板とし、他方をワイヤボンディングとした場合も、第１の実施例と比べて特性を向上できることは言うまでもない。 In this embodiment, the metal plate 25 is connected to the lead frame 24, and the commutation MOSFET 21 is connected to the ground terminal by a metal plate. It goes without saying that the characteristics can be improved compared to the example.
（第４の実施例）
次に、図１７と図１８を用いて、他の実施例について述べる。本実施例が図１５の実施例と異なる点は、駆動用ＩＣ２２が、絶縁物４７を介して転流用ＭＯＳＦＥＴ２１と金属板２８の上に積層されていることである。駆動用ＩＣ２２を積層することで、駆動用ＩＣ２２から、整流用ＭＯＳＦＥＴ２０と転流用ＭＯＳＦＥＴ２１までの距離が短くなるので、駆動回路のインダクタンスが小さくなる。また、実装面積が小さくなるという効果もある。図１８は、図１７の断面図（ａ−ａ’線）を示す。
(Fourth embodiment)
Next, another embodiment will be described with reference to FIGS. 17 and 18. The present embodiment is different from the embodiment of FIG. 15 in that the driving IC 22 is laminated on the commutation MOSFET 21 and the metal plate 28 with an insulator 47 interposed therebetween. By laminating the driving IC 22, the distance from the driving IC 22 to the rectifying MOSFET 20 and the commutation MOSFET 21 is shortened, so that the inductance of the driving circuit is reduced. In addition, there is an effect that the mounting area is reduced. 18 shows a cross-sectional view (aa ′ line) of FIG.
（第５の実施例）
次に、図１９を用いて、他の実施例について述べる。本実施例が第１の実施例と異なる点は、金属板を用いないことである。金属板の代わりに半導体前工程の配線パターンを用いることで、配線の広がり抵抗は増加するが、製造工程を簡略化できるという効果がある。
(Fifth embodiment)
Next, another embodiment will be described with reference to FIG. This embodiment is different from the first embodiment in that no metal plate is used. By using the wiring pattern of the semiconductor pre-process instead of the metal plate, the spreading resistance of the wiring increases, but the manufacturing process can be simplified.
（第６の実施例）
次に、図２０を用いて、他の実施例について述べる。本実施例が第１の実施例と異なる点は、駆動用ＩＣ２２を含まないことである。本実施例では、駆動用ＩＣを外付けする必要があるが、半導体装置のユーザが任意の駆動用ＩＣを選択できるというメリットがある。
(Sixth embodiment)
Next, another embodiment will be described with reference to FIG. This embodiment is different from the first embodiment in that the driving IC 22 is not included. In this embodiment, it is necessary to attach a driving IC externally, but there is an advantage that a user of the semiconductor device can select an arbitrary driving IC.
（第７の実施例）
次に、図２１を用いて、他の実施例について述べる。図２１が第１の実施例と異なる点は、入力コンデンサ２９を半導体装置の中に取り込んだことである。入力コンデンサ２９を内蔵することで、入力コンデンサ２９の正極から整流用ＭＯＳＦＥＴ２０、転流用ＭＯＳＦＥＴ２１を通って入力コンデンサ２９の負極に戻る主回路ループの距離が短くなり、インダクタンスを低減することができる。
(Seventh embodiment)
Next, another embodiment will be described with reference to FIG. FIG. 21 differs from the first embodiment in that the input capacitor 29 is taken into the semiconductor device. By incorporating the input capacitor 29, the distance of the main circuit loop that returns from the positive electrode of the input capacitor 29 to the negative electrode of the input capacitor 29 through the rectifying MOSFET 20 and the commutation MOSFET 21 is shortened, and the inductance can be reduced.
図２２は、インダクタンスの低減効果を更に高めた例である。入力コンデンサ２９を電源端子のリードフレーム２４とグランド端子の金属板２８の間に配置する。このように、入力コンデンサ２９を立体的に配置することで、上記した主回路ループのインダクタンスを最小にすることができる。 FIG. 22 shows an example in which the inductance reduction effect is further enhanced. An input capacitor 29 is disposed between the lead frame 24 serving as a power supply terminal and the metal plate 28 serving as a ground terminal. Thus, by arranging the input capacitor 29 in three dimensions, the inductance of the main circuit loop described above can be minimized.
（第８の実施例）
近年、半導体プロセスの微細化に伴い、電源の負荷となるＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔｓ）の動作電圧は下がる傾向にあり、電源の入力電圧が変わらない条件では、電源のデューティーは年々下がることになる。この場合、整流用ＭＯＳＦＥＴ２０の導通期間は短くなるので、整流用ＭＯＳＦＥＴ２０は導通損失に比べて、スイッチング損失が支配的になる。スイッチング損失を低減するためには帰還容量を下げることが有効で、整流用ＭＯＳＦＥＴ２０のチップサイズは転流用ＭＯＳＦＥＴ２１と比べて小さくなる。小さい面積の整流用ＭＯＳＦＥＴ２０の上に、大きい転流用ＭＯＳＦＥＴ２１を積層する場合、ワイヤボンディングの際に、機械的な強度が問題となる。
(Eighth embodiment)
In recent years, with the miniaturization of semiconductor processes, the operating voltage of LSI (Large Scale Integrated Circuits), which is the load of the power supply, tends to decrease. . In this case, since the conduction period of the rectification MOSFET 20 is shortened, the rectification MOSFET 20 has a dominant switching loss compared to the conduction loss. In order to reduce the switching loss, it is effective to lower the feedback capacitance, and the chip size of the rectifying MOSFET 20 is smaller than that of the commutation MOSFET 21. When the large commutation MOSFET 21 is stacked on the rectification MOSFET 20 having a small area, mechanical strength becomes a problem during wire bonding.
次に、この問題を対策した実施例を述べる。図２３は、駆動用ＩＣ２２と転流用ＭＯＳＦＥＴ２１の接続に用いるワイヤボンディング２３の位置が整流用ＭＯＳＦＥＴ２０と金属板２５が積層された位置にあることが特徴である。この構造をとることにより、ボンディング時の衝撃により転流用ＭＯＳＦＥＴ２１が傾くのを防ぐことができる。 Next, an embodiment that counters this problem will be described. FIG. 23 is characterized in that the position of the wire bonding 23 used to connect the driving IC 22 and the commutation MOSFET 21 is the position where the rectifying MOSFET 20 and the metal plate 25 are laminated. By adopting this structure, it is possible to prevent the commutation MOSFET 21 from being inclined by an impact during bonding.
図２４が、図２３と異なる点は、整流用ＭＯＳＦＥＴ２０と同じ厚さのダミーチップ３１を挿入したことである。この構造をとることで、整流用ＭＯＳＦＥＴ２０のボンディング時の衝撃に対する耐性が向上する。 24 differs from FIG. 23 in that a dummy chip 31 having the same thickness as that of the rectifying MOSFET 20 is inserted. By adopting this structure, the resistance against the impact during bonding of the rectifying MOSFET 20 is improved.
（第９の実施例）
以上、述べたように、半導体チップを積層することで、実装面積が小さくなり、機器が小型化できるというメリットがある。反面、熱抵抗が増加するという問題がある。以下、この問題を解決する実施例を２つ述べる。
(Ninth embodiment)
As described above, by stacking semiconductor chips, there is an advantage that the mounting area is reduced and the device can be downsized. On the other hand, there is a problem that the thermal resistance increases. Hereinafter, two embodiments for solving this problem will be described.
一つめの実施例を図１を用いて説明する。第１の実施例では、封止材２７の例として樹脂を挙げたが、一般に樹脂は熱抵抗が大きいという問題がある。最近、熱伝導導が低い樹脂が報告されており、図１の封止材２７に高熱伝導度樹脂を用いることでパッケージの熱抵抗を大幅に低減することができる。高熱伝導樹脂については、日立評論７月号（２００５）「ナノテクノロジーによる新素材（高熱伝導樹脂・低誘電損失樹脂・ナノ粒子）」に詳述されている。 A first embodiment will be described with reference to FIG. In the first embodiment, resin is used as an example of the sealing material 27. However, there is a problem that the resin generally has a large thermal resistance. Recently, a resin having low thermal conductivity has been reported, and the thermal resistance of the package can be greatly reduced by using a high thermal conductivity resin for the sealing material 27 of FIG. The high thermal conductive resin is described in detail in the Hitachi review July issue (2005) “New materials by nanotechnology (high thermal conductive resin, low dielectric loss resin, nanoparticle)”.
２つめの実施例を図３０を用いて説明する。図３０が図１と異なる点は、転流用ＭＯＳＦＥＴ２１の上に金属板２８を配置し、この金属板２８を露出させたことである。本実施例を用いることで、整流用ＭＯＳＦＥＴ２０及び転流用ＭＯＳＦＥＴ２１の発熱が、金属板２８を介して空気中に放出されるので、熱伝導度が大幅に低減できる。 A second embodiment will be described with reference to FIG. 30 differs from FIG. 1 in that a metal plate 28 is disposed on the commutation MOSFET 21 and the metal plate 28 is exposed. By using this embodiment, the heat generated by the rectifying MOSFET 20 and the commutation MOSFET 21 is released into the air through the metal plate 28, so that the thermal conductivity can be greatly reduced.
（第１０の実施例）
次に、負荷となるＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅｄ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔｓ）を含めた実施例について述べる。図２５は、本発明の半導体装置と、その負荷となるＬＳＩ３４を電気回路基板３２に搭載し、これらに共通のヒートシンク３３を取り付けたものである。ヒートシンクを共通化することで、本発明の半導体装置のためのヒートシンクが不要となり、部品数が削減できる。また、ＬＳＩの発熱は本発明の半導体装置と比べると大きいので、ＬＳＩ用のヒートシンクを大型化する必要はない。
(Tenth embodiment)
Next, an embodiment including an LSI (Large Scaled Integrated Circuits) serving as a load will be described. FIG. 25 shows a semiconductor device of the present invention and an LSI 34 serving as a load mounted on an electric circuit board 32 and a common heat sink 33 attached thereto. By using a common heat sink, a heat sink for the semiconductor device of the present invention becomes unnecessary, and the number of components can be reduced. Further, since the heat generation of the LSI is larger than that of the semiconductor device of the present invention, it is not necessary to increase the size of the LSI heat sink.
（第１１の実施例）
次に、本発明の半導体装置と、出力フィルタとなるインダクタンス及びコンデンサを含めた実施例について述べる。図５の電気回路において、整流用ＭＯＳＦＥＴ２と転流用ＭＯＳＦＥＴ３は交互にオンとなり、出力の電流及び電圧は矩形波となるので、出力コンデンサ５とチョークコイル４は電圧と電流を平滑化する役割を果たす。
(Eleventh embodiment)
Next, an embodiment including the semiconductor device of the present invention and an inductance and a capacitor serving as an output filter will be described. In the electric circuit of FIG. 5, the rectifying MOSFET 2 and the commutation MOSFET 3 are alternately turned on, and the output current and voltage are rectangular waves. Therefore, the output capacitor 5 and the choke coil 4 serve to smooth the voltage and current. .
図２６は、本発明の半導体装置、チョークコイル、コンデンサと負荷となるＬＳＩのソケットを含めた実施例を示す。ソケット４０はＬＳＩを取り付けるソケットで、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）やＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）である、ソケットの中心付近に、周波数特性が良いコンデンサ４１が置かれ、その周囲に周波数特性が上記コンデンサ４１より劣るコンデンサ４２が置かれ、その周囲にチョークコイル４３が置かれ、その周囲に本発明の半導体装置４４が置かれる。このように、電源を構成する部品を密に配置することで、出力フィルタと負荷であるＬＳＩの距離が短くなり、整流用ＭＯＳＦＥＴがスイッチングする際のＬＳＩの電圧変化を小さくすることができる。 FIG. 26 shows an embodiment including the semiconductor device, choke coil, capacitor and LSI socket serving as a load of the present invention. The socket 40 is a socket to which an LSI is attached. A capacitor 41 having a good frequency characteristic is placed near the center of the socket, which is a BGA (Ball Grid Array) or LGA (Land Grid Array), and the capacitor 41 has a frequency characteristic around it. An inferior capacitor 42 is placed, a choke coil 43 is placed around it, and a semiconductor device 44 of the present invention is placed around it. Thus, by arranging the components constituting the power supply densely, the distance between the output filter and the load LSI can be shortened, and the change in the LSI voltage when the rectifying MOSFET is switched can be reduced.
ここで、コンデンサの周波数特性を説明する。図２７は、コンデンサの周波数特性を示した図で、横軸が周波数、縦軸がインピーダンスを表す。コンデンサの周波数がＶ字型となる理由は、低周波数領域ではコンデンサの寄生インダクタンスが無視できるのでインピーダンスが純粋なコンデンサ特性を示すのに対し、高周波では寄生インダクタンスが支配的になるので、インピーダンスがインダクタンス特性を示すからである。周波数特性が良いコンデンサは、高い周波数までインピーダンスが低下する。本実施例では、２つの異なる周波数特性を持つコンデンサを例に説明したが、周波数特性が異なるコンデンサを３種以上用いても、同様の効果が得られる。 Here, the frequency characteristics of the capacitor will be described. FIG. 27 is a diagram showing the frequency characteristics of the capacitor, where the horizontal axis represents frequency and the vertical axis represents impedance. The reason why the frequency of the capacitor is V-shaped is that the parasitic inductance of the capacitor is negligible in the low frequency region, so that the impedance shows a pure capacitor characteristic, whereas the parasitic inductance is dominant at high frequencies, so the impedance is inductance. This is because the characteristics are shown. A capacitor having a good frequency characteristic has an impedance that decreases to a high frequency. In the present embodiment, the capacitor having two different frequency characteristics has been described as an example, but the same effect can be obtained even when three or more types of capacitors having different frequency characteristics are used.
（第１２の実施例）
次に、本発明の半導体装置を応用した実施例について述べる。図２８は、本発明の半導体装置７１を４個並列に用いた実施例で、半導体装置７１の前段に、制御信号を出力する制御回路７５があり、それぞれの半導体装置７１に位相の異なる信号を出力する。図２８において、７２はチョークコイル、７３は出力コンデンサ、７４は負荷となるＬＳＩを示す抵抗である。本実施例では、半導体装置７１の並列数が４個なので、制御回路７５が出力する信号の位相は９０度ずつ異なる。このように位相をずらすことで、電源の実効的なスイッチング周波数を、それぞれの周波数の４倍にすることができ、出力電流のリップルを低減することができる。
(Twelfth embodiment)
Next, examples in which the semiconductor device of the present invention is applied will be described. FIG. 28 shows an embodiment in which four semiconductor devices 71 of the present invention are used in parallel. A control circuit 75 that outputs a control signal is provided in the preceding stage of the semiconductor device 71, and signals having different phases are sent to the respective semiconductor devices 71. Output. In FIG. 28, 72 is a choke coil, 73 is an output capacitor, and 74 is a resistor indicating an LSI serving as a load. In this embodiment, since the parallel number of the semiconductor devices 71 is four, the phase of the signal output from the control circuit 75 differs by 90 degrees. By shifting the phase in this way, the effective switching frequency of the power supply can be made four times the respective frequency, and the ripple of the output current can be reduced.
（第１３の実施例）
次に、本発明の他の実施例について述べる。他の実施例を示す図２９が、図９と異なる点は、制御部１４をパッケージに取り込んだことで、点線で示した範囲の機能ブロック４５を一つのパッケージに実装したことで、制御部１４から整流用ＭＯＳＦＥＴ２と転流用ＭＯＳＦＥＴ３までの距離が短くなるので、制御部１４からの信号の遅延が短くなり、負荷となるＬＳＩの電流が急変した場合の応答性が向上する。
(Thirteenth embodiment)
Next, another embodiment of the present invention will be described. FIG. 29 showing another embodiment is different from FIG. 9 in that the control unit 14 is incorporated in the package, and the functional block 45 in the range indicated by the dotted line is mounted in one package. Since the distance from the rectifier MOSFET 2 to the commutation MOSFET 3 is shortened, the delay of the signal from the control unit 14 is shortened, and the responsiveness when the current of the LSI serving as a load changes suddenly is improved.
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
本発明は、電源装置に係り、特に、電子機器等に用いられる半導体装置及び電源装置に適用して有効である。 The present invention relates to a power supply device, and is particularly effective when applied to a semiconductor device and a power supply device used in electronic equipment and the like.
１…直流入力電源、２…整流用ＭＯＳＦＥＴ、３…転流用ＭＯＳＦＥＴ、４…チョークコイル、５…出力コンデンサ、６…負荷となるＬＳＩを示す抵抗、７…入力コンデンサ、９…制御回路、１０…主回路の寄生抵抗、１１…主回路の寄生インダクタンス、１２…駆動回路の寄生抵抗、１３…駆動回路の寄生インダクタンス、１４…制御部、１５…駆動部、１６…機能ブロック、２０…整流用ＭＯＳＦＥＴ、２１…転流用ＭＯＳＦＥＴ、２２…駆動用ＩＣ、２３…ワイヤボンディング、２４…リードフレーム、２５…金属板、２７…封止材、２８…金属板、２９…入力コンデンサ、３１…ダミーチップ、３２…電気回路基板、３３…ヒートシンク、３４…負荷となるＬＳＩ、４０…ソケット、４１，４２…コンデンサ、４３…チョークコイル、４４…本発明の半導体装置、４５…機能ブロック、４６…溝、４７…絶縁物、５１…入力部、５２…スイッチング部、５３…出力部、５４…制御部、５５…出力フィルタ、６０…直流入力電源、６１…入力コンデンサ、６２…能動素子、６３…転流ダイオード、６４…チョークコイル、６５…コンデンサ、６６…負荷、６７…検出部、６８…設定部、６９…比較演算部、７０…駆動部、７１…本発明の半導体装置、７２…チョークコイル、７３…出力コンデンサ、７４…負荷となるＬＳＩを示す抵抗、７５…制御回路。 DESCRIPTION OF SYMBOLS 1 ... DC input power source, 2 ... Rectification MOSFET, 3 ... Commutation MOSFET, 4 ... Choke coil, 5 ... Output capacitor, 6 ... Resistance indicating LSI as load, 7 ... Input capacitor, 9 ... Control circuit, 10 ... Parasitic resistance of main circuit, 11 ... Parasitic inductance of main circuit, 12 ... Parasitic resistance of driving circuit, 13 ... Parasitic inductance of driving circuit, 14 ... Control unit, 15 ... Driving unit, 16 ... Functional block, 20 ... MOSFET for rectification , 21 ... Commutation MOSFET, 22 ... Driving IC, 23 ... Wire bonding, 24 ... Lead frame, 25 ... Metal plate, 27 ... Sealing material, 28 ... Metal plate, 29 ... Input capacitor, 31 ... Dummy chip, 32 ... Electric circuit board, 33 ... Heat sink, 34 ... LSI as load, 40 ... Socket, 41, 42 ... Capacitor, 43 ... Choke coil 44 ... Semiconductor device of the present invention 45 ... Functional block 46 ... Groove 47 Insulator 51 ... Input unit 52 ... Switching unit 53 ... Output unit 54 ... Control unit 55 ... Output filter 60 ... DC Input power supply 61 ... Input capacitor 62 ... Active element 63 ... Commutation diode 64 ... Choke coil 65 ... Capacitor 66 ... Load 67 ... Detection unit 68 ... Setting unit 69 ... Comparison calculation unit 70 ... Drive unit 71 ... Semiconductor device of the present invention 72 ... Choke coil 73 ... Output capacitor 74 ... Resistor showing LSI as load 75 ... Control circuit
Claims (9)
整流用縦型ＭＯＳＦＥＴを備え、前記整流用縦型ＭＯＳＦＥＴのソース電極と電気的に接続されたソース電極パッドが配置された第１主面と、前記第１主面とは反対側であって、前記整流用縦型ＭＯＳＦＥＴのドレイン電極が形成された第２主面と、を有する第１半導体チップと、
転流用縦型ＭＯＳＦＥＴを備え、前記転流用縦型ＭＯＳＦＥＴのソース電極と電気的に接続されたソース電極パッドが配置された第３主面と、前記第３主面とは反対側であって、前記転流用縦型ＭＯＳＦＥＴのドレイン電極が形成された第４主面と、を有する第２半導体チップと、
前記第１および第２半導体チップに電気的に接続され、第１表面と前記第１表面とは反対側の第２表面と、を有する第１金属板と、
上面と、前記上面とは反対側の下面と、を有する第１リード端子と、
前記第１リード端子とは電気的に分離された出力リード端子と、
前記第１および第２半導体チップ、前記第１金属板、前記第１および出力リード端子のそれぞれの一部を封止する封止体と、を備え、
前記第１および第２半導体チップは、前記第１半導体チップの前記第１主面が前記第１金属板の前記第１表面と対向するように、かつ前記第２半導体チップの前記第４主面が前記第１金属板の前記第２表面と対向するように前記第１金属板を介して積層されていることにより、前記第１半導体チップの前記ソース電極パッドと前記第２半導体チップの前記ドレイン電極とは電気的に直列で接続され、
前記第１および第２半導体チップ、および前記第１金属板は、前記第１リード端子の前記上面上に積層され、
前記第１金属板は、前記出力リード端子と電気的に接続され、
前記第１半導体チップのチップサイズは、前記第２半導体チップのチップサイズよりも小さい、半導体装置。 A semiconductor device for a DC-DC converter,
A first main surface including a rectifying vertical MOSFET, wherein a source electrode pad electrically connected to a source electrode of the rectifying vertical MOSFET is disposed on the opposite side of the first main surface; A first semiconductor chip having a second main surface on which a drain electrode of the vertical MOSFET for rectification is formed;
A third main surface provided with a commutation vertical MOSFET and provided with a source electrode pad electrically connected to a source electrode of the commutation vertical MOSFET; and the opposite side of the third main surface; A second semiconductor chip having a fourth main surface on which a drain electrode of the vertical MOSFET for commutation is formed;
A first metal plate electrically connected to the first and second semiconductor chips and having a first surface and a second surface opposite to the first surface;
A first lead terminal having an upper surface and a lower surface opposite to the upper surface;
An output lead terminal electrically isolated from the first lead terminal;
A sealing body that seals a part of each of the first and second semiconductor chips, the first metal plate, and the first and output lead terminals;
The first and second semiconductor chips are configured such that the first main surface of the first semiconductor chip faces the first surface of the first metal plate, and the fourth main surface of the second semiconductor chip. Are stacked via the first metal plate so as to face the second surface of the first metal plate, so that the source electrode pad of the first semiconductor chip and the drain of the second semiconductor chip The electrodes are electrically connected in series,
The first and second semiconductor chips and the first metal plate are stacked on the upper surface of the first lead terminal,
The first metal plate is electrically connected to the output lead terminal ;
The semiconductor device, wherein a chip size of the first semiconductor chip is smaller than a chip size of the second semiconductor chip .
前記第１半導体チップの前記整流用縦型ＭＯＳＦＥＴと前記第２半導体チップの前記転流用縦型ＭＯＳＦＥＴとを制御する制御回路を備え、前記制御回路と電気的に接続された第１電極パッドと第２電極パッドとが配置された主面を有する第３半導体チップをさらに有し、
前記第１半導体チップの前記第１主面には、前記整流用縦型ＭＯＳＦＥＴのゲート電極と電気的に接続されたゲート電極パッドが配置され、
前記第２半導体チップの前記第２主面には、前記転流用縦型ＭＯＳＦＥＴのゲート電極と電気的に接続されたゲート電極パッドが配置され、
前記第３半導体チップの前記第１電極パッドは、前記第１半導体チップの前記ゲート電極パッドと第１金属ワイヤを介して電気的に接続され、前記第３半導体チップの前記第２電極パッドは、前記第２半導体チップの前記ゲート電極パッドと前記第２金属ワイヤを介して電気的に接続されている。 The semiconductor device according to claim 1,
A control circuit that controls the vertical MOSFET for rectification of the first semiconductor chip and the vertical MOSFET for commutation of the second semiconductor chip; and a first electrode pad electrically connected to the control circuit and a first electrode pad A third semiconductor chip having a main surface on which two electrode pads are disposed;
A gate electrode pad electrically connected to a gate electrode of the rectifying vertical MOSFET is disposed on the first main surface of the first semiconductor chip,
A gate electrode pad electrically connected to the gate electrode of the commutation vertical MOSFET is disposed on the second main surface of the second semiconductor chip,
The first electrode pad of the third semiconductor chip is electrically connected to the gate electrode pad of the first semiconductor chip via a first metal wire, and the second electrode pad of the third semiconductor chip is The second electrode is electrically connected to the gate electrode pad of the second semiconductor chip via the second metal wire.
前記第３半導体チップは、前記封止体で封止されている。 The semiconductor device according to claim 2,
The third semiconductor chip is sealed with the sealing body.
前記第３半導体チップは、前記第２半導体チップ上に積層されている。 The semiconductor device according to claim 3.
The third semiconductor chip is stacked on the second semiconductor chip.
前記第１リード端子の前記下面は、前記封止体から露出している。 The semiconductor device according to claim 1,
The lower surface of the first lead terminal is exposed from the sealing body.
前記第１半導体チップは、前記第１半導体チップの前記第２主面が前記第１リード端子の前記上面と対向するように前記第１リード端子の前記上面上に搭載されていることにより、前記第１半導体チップの前記ドレイン電極と前記第１リード端子とが電気的に直列に接続されている。 The semiconductor device according to claim 1,
The first semiconductor chip is mounted on the upper surface of the first lead terminal so that the second main surface of the first semiconductor chip faces the upper surface of the first lead terminal. The drain electrode of the first semiconductor chip and the first lead terminal are electrically connected in series.
前記第２半導体チップと電気的に接続された第２金属板と、
前記第１および出力リード端子とは電気的に分離された第２リード端子と、を有し、
前記第２金属板は、前記第２半導体チップの前記第３主面と対向するように前記第２半導体チップの前記第３主面上に搭載されていることにより、前記第２半導体チップの前記ソース電極パッドと電気的に直列に接続され、
前記第２金属板は、前記第２リード端子と電気的に接続されている。 The semiconductor device according to claim 6.
A second metal plate electrically connected to the second semiconductor chip;
A second lead terminal electrically separated from the first and output lead terminals;
The second metal plate is mounted on the third main surface of the second semiconductor chip so as to face the third main surface of the second semiconductor chip. Electrically connected in series with the source electrode pad,
The second metal plate is electrically connected to the second lead terminal.
前記第１リード端子は、外部から電源電圧が供給される電源リード端子であり、前記第２リード端子は、外部から接地電圧が供給されるＧＮＤリード端子である。 The semiconductor device according to claim 7,
The first lead terminal is a power supply lead terminal to which a power supply voltage is supplied from the outside, and the second lead terminal is a GND lead terminal to which a ground voltage is supplied from the outside.
前記第２リード端子の一部は、前記封止体により封止されている。 The semiconductor device according to claim 7,
A part of the second lead terminal is sealed with the sealing body.
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